Advanced Configuration and Power Interface Specification 3.0a

Converted from ACPI.info

Advanced Configuration and Power Interface Specification

There now exists version 4.0 and 4.0a. Version 5.0 is un:wder Development! as of 9/23/10.
4.0a Apr. 2010 Removed text concerning government requirement of mechanical off Clarified URL update document, Corrected section references for APIC, SLIT, SRAT in Table 5-5, Update URLs and reformated Table 5-6 Corrected reference to Interrupt Source Override Structure Corrected name for CPEP table Corrected reference to SMBus, should be IPMI Clarified BusCheck and DeviceCheck notifications in Table 5-53 Added link to non-ACPI Plug and Play ID reference document Added missing _ATT and _GAI names, Corrected page/section references in Table 5-67 Corrected EndTag name value. Was 0x78, correct value is 0x79 Table 6-33 Consumer/Producer bit is ignored (Restored 2.0C change that had been lost) Clarified use of _GLK (Global Lock) object Corrected definition of _TSD, object _PSD object , table name (CPEP) Corrected 'maximum positive adjustment' value. Was 500%, correct value is 50%, Updated description of example ' 300 to 400 lux, Eliminated hardcoded package lengths in examples, Changed 'brightness' to 'highest ambient light value' Corrected reference to _IDE, should be _GTM. Corrected table reference Clarified GPE Block Device Description Corrected _PLD object examples Repaired diagram that would not display properly Figure 10-2 Added missing _BCT method to Table 10-3 Clarified that OEM Information field should contain NULL string if not supported in Table 10-4 &Table 10-5 Corrected description of _BTM arguments and return value Clarified description of _BCT return value Corrected HID for Power Source device. Was ACPI0003, correct value is ACPI0004 Corrected _PIF example. First package element was a Buffer, should be Integer, Clarified that OEM Information field should contain NULL string if not supported Table 10-10 Corrected description of _SHL method Table 10-11 Clarified _PRL return value, a list of References Corrected _PMC example. First package element was a Buffer, should be Integer Clarified that OEM Information field should contain NULL string if not supported Table 10-12 Repaired diagram that would not display properly Figure 15-1 Corrected error conditions from 'fatal' to 'corrected Clarified number of Generic Error Data Entry structures is >=1 (not Zero) Added new section clarifying SCI notification for generic error sources Added new section describing Firmware First error handling Clarified purpose of the codes Table 17-17 Added reference to table of COMMAND_STATUS codes Table 17-23 Clarified purpose of the command status codes in Table 17-27 and the error type definitions in Table 17-28 Added _ATT resource descriptor field name Clarified rules for Buffer vs. Integer return types from a field unit Corrected section/page reference 4.0 June 2009 Major specification revision. Clock Domains, x2APIC Support, Logical Processor Idling, Corrected Platform Error Polling Table, Maximum System Characteristics Table, Power Metering and Budgeting, IPMI Operation Region, USB3 Support in _PLD, Re-evaluation of _PPC acknowledgement via _OST, Thermal Model Enhancements, _OSC at \_SB, Wake Alarm Device, Battery Related Extensions, Memory Bandwidth Monitoring and Reporting, ACPI Hardware Error Interfaces, D3hot.

Hewlett-Packard Corporation, Intel Corporation ,Microsoft Corporation, Phoenix Technologies Ltd., Toshiba Corporation
Revision 3.0b October 10

Revision

Change Description

Affected Sections

3.0b
Oct. 2006

Table 5-6 changes. Added BERT, DMAR, ERST, HEST, IBFT, UEFI, & WAET Table signatures, corrected BOOTand TCPA table urls.
Added PCIe ASPM Controls to Boot Architecture Flags Table 5-11
Clarified DSDT loading.
Clarified SSDTs are ALL loaded during init.
Added a section describing guidelines for the ordering of processors in the MADT to support proper boot processor and multi-threaded logical processor operation.
Clarified _STA object description.
Clarified _INI object description.
Clarified _CST entry type field is 1,2, or 3 only.
Clarified _PTC ASL definition, Corrected _PTC ASL examples

Clarified _PCT ASL definition.
Added section describing PCI Bus and Segment Group Numbers under Module Devices
Corrected LoadTable invocation in thermal zone with multiple devices example.
Corrected RegisterTerm definition to include optional DescriptorName field.

Corrected Buffer declaration example.
Corrected DMA Resource Descriptor Macro Descriptor Name description.
Corrected DWORD IO Resource Descriptor Macro Descriptor Name description.
Corrected DWORD Memory Resource Descriptor Macro Descriptor Name description.

Corrected DWORD Space Resource Descriptor Macro Descriptor Name description.

Corrected Extended IO Resource Descriptor Macro Descriptor Name description.

Corrected Extended Memory Resource Descriptor Macro Descriptor Name description.

Corrected Extended Space Resource Descriptor Macro Descriptor Name description.

Clarified External object ReturnType and ParamterTypes.

Clarified Function object ParamterTypes.
Clarified IndexField object operation.
Corrected IO Resource Descriptor Macro Descriptor Name description.
Corrected Interrupt Resource Descriptor Macro Descriptor Name description.

Corrected IRQNoFlags Interrupt Resource Descriptor Macro Descriptor Name description.

Clarified LoadTable is not used to load tables with "SSDT" signature.
Clarified Match Object SearchPackage argument and description.
Corrected Memory24 Memory Resource Descriptor Macro Descriptor Name description. Corrected AddressAlignment field bits.
Corrected Memory32 Memory Resource Descriptor Macro Descriptor Name description.

Corrected Memory32Fixed Memory Resource Descriptor Macro Descriptor Name description.

Clarified Method object ParamterTypes.
Corrected QwordIO Resource Descriptor Macro Descriptor Name description.
Corrected Qword Memory Resource Descriptor Macro Descriptor Name description.

Corrected QwordSpace Resource Descriptor Macro Descriptor Name description.

Added Descriptor Name argument description to Register Resource Descriptor Macro definition.
Corrected VendorLong Resource Descriptor Macro Descriptor Name description.

Corrected VendorShort Resource Descriptor Macro Descriptor Name description.

Clarified Wait object TimeoutValue range.

Corrected WordBusNumber Resource Descriptor Macro Descriptor Name description.

Corrected WordIO Resource Descriptor Macro Descriptor Name description.
Corrected WordSpace Resource Descriptor Macro Descriptor Name description.

5.2.6

5.2.9.3
5.,2.11.1
5.2.11.2
5.2.11.4.1

6.3.7
6.5.1
8.4.2.1
8.4.3.1, 8.4.3.4
8.4.4.1
9.12.1

11.6.3

17.1.8
17.5.9
17.5.30
17.5.31

17.5.32

17.5.33

17.5.39

17.5.40

17.5.41

17.5.42
17.5.49
17.5.54
17.5.56
17.5.57
17.5.58

17.5.68
17.5.71
17.5.72

17.5.73

17.5.74

17.5.75
17.5.94
17.5.95

17.5.96

17.5.98

17.5.127

17.5.128

17.5.129
17.5.131

17.5.132
17.5.133

3.0a
Dec. 2005

Errata corrected and clarifications added.
Table 5-6 changes.Updated HPET web link, added WSPT and WDAT, updated WDRT description and web link
Clarified that the endian-ness of data value encodings in externally defined data tables is specified by the external data table specifications
Added MSI_Not_Supported bit to IA-PC Boot Architecture Flags Table 5-11
Corrected X_Firmware_Waking_Vector description in Table 5-12
_ADR object encoding for USB Ports clarified as 1-n in Table 6-2
Updated and clarified _HPX object description and setting record types
Clarified Resource Data Type descriptions – readability / usability
Clarified Small Resource Data Type description - Tables 6-21, 6-22
Corrected IRQ Descriptior ASL macro reference
Corrected description text of General Flags field for _MAF and _MIF bits in Address Space Descriptors
Updated _PDC ASL example invoking _OSC and accompanying description
Corrected processor Throttling State (T-state) control interface definitions
Clarified OSPM processing of _TPC notifies on platforms supporting P-states
Clarified _PSS entry power field is maximum power consumed in the P-state
Clarified _CRS encoding of registers for the GPE Block device
Corrected OpCode definitions for DerefOfTerm and IndexTerm
Added ProcessorObj to ObjectTypeKeyword
Clarified Data Type Conversion Rules in Table 17-8
Clarified creation of zero bit-length field using CreateField causes fatal exception
Clarified DMA Resource Descriptor Macro DmaChannelList description
Function object ParameterTypes >description corrected. Fixed StringObj type in example
Clarified Interrupt Resource Descriptor Macros InterruptList description
Corrected Interrupt Resource Descriptor Macro description
Corrected Package declaration

Clarified Return object ASL syntax providing implicit zero return argument when no parenthesis follow the Return statement
ToBuffer - Clarified string null terminator is copied

Clarified ASL Resource Macros - ResourceSourceIndex > and ResourceSource argument requirements and ASL compiler behavior

Corrected AML definition - data types Const -> Data
Removed the 200 byte length limitation on ASCII strings

Clarified that definition blocks loaded by the Load operator must be in memory marked as AddressRangeReserved or AddressRangeNVS

5.2.6

5.2.6

5.2.9.3
5.2.10
6.1.1
6.2.7
6.4
6.4.2
6.4.2.1
6.4.3.5.1-4

8.4.1
8.4.3
8.4.3.3
8.4.4.2
9.11
17.1.5
17.1.7
17.2.5.7
17.5.19

17.5.30
17.5.49

17.5.55,57,58
17.5.57
17.5.91
17.5.102

17.5.119
17.5.31,32,33,55,94,95,96,131,132,133
18.2.1
17.2.2.2, 17.2.5, 17.2.5.7, 17.5.123
17.5.67

3.0
Sept. 2004

Major specification revision. General configuration enhancements. Inter-Processor power, performance, and throttling state dependency support added. Support for > 256 processors added. NUMA Distancing support added. PCI Express support added. SATA support added. Ambient Light Sensor and User Presence device support added. Thermal model extended beyond processor-centric support.

2.0c
Aug.. 2003

Errata corrected and clarifications added.

2.0b
Oct. 2002

Errata corrected and clarifications added.

2.0a
Mar. 2002

Errata corrected and clarifications added. ACPI 2.0 Errata Document Revision 1.0 through 1.5 integrated.

ACPI 2.0 Errata Doc. Rev

Errata corrected and clarifications added.

ACPI 2.0 Errata Doc. Rev

Errata corrected and clarifications added.

ACPI 2.0 Errata Doc. Rev

Errata corrected and clarifications added.

ACPI 2.0 Errata Doc. Rev

Errata corrected and clarifications added.

ACPI 2.0 Errata Doc. Rev

Errata corrected and clarifications added.

ACPI 2.0 Errata Doc. Rev

Errata corrected and clarifications added.

2.0
Aug. 2000

Major specification revision. 64-bit addressing support added. Processor and device performance state support added. Numerous multiprocessor workstation and server-related enhancements. Consistency and readability enhancements throughout.

1.0b
Feb. 1999

Errata corrected and clarifications added. New interfaces added.

1.0a
Jul. 1998

Errata corrected and clarifications added. New interfaces added.

1.0
Dec. 1996

Original Release.

Revision	Change Description	Affected Sections
3.0b Oct. 2006	Table 5-6 changes. Added BERT, DMAR, ERST, HEST, IBFT, UEFI, & WAET Table signatures, corrected BOOTand TCPA table urls. Added PCIe ASPM Controls to Boot Architecture Flags Table 5-11 Clarified DSDT loading. Clarified SSDTs are ALL loaded during init. Added a section describing guidelines for the ordering of processors in the MADT to support proper boot processor and multi-threaded logical processor operation. Clarified _STA object description. Clarified _INI object description. Clarified _CST entry type field is 1,2, or 3 only. Clarified _PTC ASL definition, Corrected _PTC ASL examples Clarified _PCT ASL definition. Added section describing PCI Bus and Segment Group Numbers under Module Devices Corrected LoadTable invocation in thermal zone with multiple devices example. Corrected RegisterTerm definition to include optional DescriptorName field. Corrected Buffer declaration example. Corrected DMA Resource Descriptor Macro Descriptor Name description. Corrected DWORD IO Resource Descriptor Macro Descriptor Name description. Corrected DWORD Memory Resource Descriptor Macro Descriptor Name description. Corrected DWORD Space Resource Descriptor Macro Descriptor Name description. Corrected Extended IO Resource Descriptor Macro Descriptor Name description. Corrected Extended Memory Resource Descriptor Macro Descriptor Name description. Corrected Extended Space Resource Descriptor Macro Descriptor Name description. Clarified External object ReturnType and ParamterTypes. Clarified Function object ParamterTypes. Clarified IndexField object operation. Corrected IO Resource Descriptor Macro Descriptor Name description. Corrected Interrupt Resource Descriptor Macro Descriptor Name description. Corrected IRQNoFlags Interrupt Resource Descriptor Macro Descriptor Name description. Clarified LoadTable is not used to load tables with "SSDT" signature. Clarified Match Object SearchPackage argument and description. Corrected Memory24 Memory Resource Descriptor Macro Descriptor Name description. Corrected AddressAlignment field bits. Corrected Memory32 Memory Resource Descriptor Macro Descriptor Name description. Corrected Memory32Fixed Memory Resource Descriptor Macro Descriptor Name description. Clarified Method object ParamterTypes. Corrected QwordIO Resource Descriptor Macro Descriptor Name description. Corrected Qword Memory Resource Descriptor Macro Descriptor Name description. Corrected QwordSpace Resource Descriptor Macro Descriptor Name description. Added Descriptor Name argument description to Register Resource Descriptor Macro definition. Corrected VendorLong Resource Descriptor Macro Descriptor Name description. Corrected VendorShort Resource Descriptor Macro Descriptor Name description. Clarified Wait object TimeoutValue range. Corrected WordBusNumber Resource Descriptor Macro Descriptor Name description. Corrected WordIO Resource Descriptor Macro Descriptor Name description. Corrected WordSpace Resource Descriptor Macro Descriptor Name description.	5.2.6 5.2.9.3 5.,2.11.1 5.2.11.2 5.2.11.4.1 6.3.7 6.5.1 8.4.2.1 8.4.3.1, 8.4.3.4 8.4.4.1 9.12.1 11.6.3 17.1.8 17.5.9 17.5.30 17.5.31 17.5.32 17.5.33 17.5.39 17.5.40 17.5.41 17.5.42 17.5.49 17.5.54 17.5.56 17.5.57 17.5.58 17.5.68 17.5.71 17.5.72 17.5.73 17.5.74 17.5.75 17.5.94 17.5.95 17.5.96 17.5.98 17.5.127 17.5.128 17.5.129 17.5.131 17.5.132 17.5.133
3.0a Dec. 2005	Errata corrected and clarifications added. Table 5-6 changes.Updated HPET web link, added WSPT and WDAT, updated WDRT description and web link Clarified that the endian-ness of data value encodings in externally defined data tables is specified by the external data table specifications Added MSI_Not_Supported bit to IA-PC Boot Architecture Flags Table 5-11 Corrected X_Firmware_Waking_Vector description in Table 5-12 _ADR object encoding for USB Ports clarified as 1-n in Table 6-2 Updated and clarified _HPX object description and setting record types Clarified Resource Data Type descriptions – readability / usability Clarified Small Resource Data Type description - Tables 6-21, 6-22 Corrected IRQ Descriptior ASL macro reference Corrected description text of General Flags field for _MAF and _MIF bits in Address Space Descriptors Updated _PDC ASL example invoking _OSC and accompanying description Corrected processor Throttling State (T-state) control interface definitions Clarified OSPM processing of _TPC notifies on platforms supporting P-states Clarified _PSS entry power field is maximum power consumed in the P-state Clarified _CRS encoding of registers for the GPE Block device Corrected OpCode definitions for DerefOfTerm and IndexTerm Added ProcessorObj to ObjectTypeKeyword Clarified Data Type Conversion Rules in Table 17-8 Clarified creation of zero bit-length field using CreateField causes fatal exception Clarified DMA Resource Descriptor Macro DmaChannelList description Function object ParameterTypes >description corrected. Fixed StringObj type in example Clarified Interrupt Resource Descriptor Macros InterruptList description Corrected Interrupt Resource Descriptor Macro description Corrected Package declaration Clarified Return object ASL syntax providing implicit zero return argument when no parenthesis follow the Return statement ToBuffer - Clarified string null terminator is copied Clarified ASL Resource Macros - ResourceSourceIndex > and ResourceSource argument requirements and ASL compiler behavior Corrected AML definition - data types Const -> Data Removed the 200 byte length limitation on ASCII strings Clarified that definition blocks loaded by the Load operator must be in memory marked as AddressRangeReserved or AddressRangeNVS	5.2.6 5.2.6 5.2.9.3 5.2.10 6.1.1 6.2.7 6.4 6.4.2 6.4.2.1 6.4.3.5.1-4 8.4.1 8.4.3 8.4.3.3 8.4.4.2 9.11 17.1.5 17.1.7 17.2.5.7 17.5.19 17.5.30 17.5.49 17.5.55,57,58 17.5.57 17.5.91 17.5.102 17.5.119 17.5.31,32,33,55,94,95,96,131,132,133 18.2.1 17.2.2.2, 17.2.5, 17.2.5.7, 17.5.123 17.5.67
3.0 Sept. 2004	Major specification revision. General configuration enhancements. Inter-Processor power, performance, and throttling state dependency support added. Support for > 256 processors added. NUMA Distancing support added. PCI Express support added. SATA support added. Ambient Light Sensor and User Presence device support added. Thermal model extended beyond processor-centric support.
2.0c Aug.. 2003	Errata corrected and clarifications added.
2.0b Oct. 2002	Errata corrected and clarifications added.
2.0a Mar. 2002	Errata corrected and clarifications added. ACPI 2.0 Errata Document Revision 1.0 through 1.5 integrated.
ACPI 2.0 Errata Doc. Rev	Errata corrected and clarifications added.
ACPI 2.0 Errata Doc. Rev	Errata corrected and clarifications added.
ACPI 2.0 Errata Doc. Rev	Errata corrected and clarifications added.
ACPI 2.0 Errata Doc. Rev	Errata corrected and clarifications added.
ACPI 2.0 Errata Doc. Rev	Errata corrected and clarifications added.
ACPI 2.0 Errata Doc. Rev	Errata corrected and clarifications added.
2.0 Aug. 2000	Major specification revision. 64-bit addressing support added. Processor and device performance state support added. Numerous multiprocessor workstation and server-related enhancements. Consistency and readability enhancements throughout.
1.0b Feb. 1999	Errata corrected and clarifications added. New interfaces added.
1.0a Jul. 1998	Errata corrected and clarifications added. New interfaces added.
1.0 Dec. 1996	Original Release.

1 Introduction
The Advanced Configuration and Power Interface (ACPI) specification was developed to establish industry common interfaces enabling robust operating system (OS)-directed motherboard device configuration and power management of both devices and entire systems. ACPI is the key element in Operating System-directed configuration and Power Management (OSPM).
ACPI evolves the existing collection of power management BIOS code, Advanced Power Management (APM) application programming interfaces (APIs, PNPBIOS APIs, Multiprocessor Specification (MPS) tables and so on into a well-defined power management and configuration interface specification. ACPI provides the means for an orderly transition from existing (legacy) hardware to ACPI hardware, and it allows for both ACPI and legacy mechanisms to exist in a single machine and to be used as needed.
Further, new system architectures are being built that stretch the limits of current Plug and Play interfaces. ACPI evolves the existing motherboard configuration interfaces to support these advanced architectures in a more robust, and potentially more efficient manner.
The interfaces and OSPM concepts defined within this specification are suitable to all classes of computers including (but not limited to) desktop, mobile, workstation, and server machines. From a power management perspective, OSPM/ACPI promotes the concept that systems should conserve energy by transitioning unused devices into lower power states including placing the entire system in a low-power state (sleeping state) when possible.
This document describes ACPI hardware interfaces, ACPI software interfaces and ACPI data structures that, when implemented, enable support for robust OS-directed configuration and power management (OSPM).

1.1   Principal Goals
ACPI is the key element in implementing OSPM. ACPI-defined interfaces are intended for wide adoption to encourage hardware and software vendors to build ACPI-compatible (and, thus, OSPM-compatible) implementations.
The principal goals of ACPI and OSPM are to:
1.     Enable all computer systems to implement motherboard configuration and power management functions, using appropriate cost/function tradeoffs.
·       Computer systems include (but are not limited to) desktop, mobile, workstation, and server machines.
·       Machine implementers have the freedom to implement a wide range of solutions, from the very simple to the very aggressive, while still maintaining full OS support.
·       Wide implementation of power management will make it practical and compelling for applications to support and exploit it. It will make new uses of PCs practical and existing uses of PCs more economical.
2.    Enhance power management functionality and robustness.
·       Power management policies too complicated to implement in a ROM BIOS can be implemented and supported in the OS, allowing inexpensive power managed hardware to support very elaborate power management policies.
·       Gathering power management information from users, applications, and the hardware together into the OS will enable better power management decisions and execution.
·       Unification of power management algorithms in the OS will reduce conflicts between the firmware and OS and will enhance reliability.

3.    Facilitate and accelerate industry-wide implementation of power management.
·       OSPM and ACPI will reduce the amount of redundant investment in power management throughout the industry, as this investment and function will be gathered into the OS. This will allow industry participants to focus their efforts and investments on innovation rather than simple parity.
·       The OS can evolve independently of the hardware, allowing all ACPI-compatible machines to gain the benefits of OS improvements and innovations.
4.    Create a robust interface for configuring motherboard devices.
·       Enable new advanced designs not possible with existing interfaces.
1.2   Power Management Rationale
It is necessary to move power management into the OS and to use an abstract interface (ACPI) between the OS and the hardware to achieve the principal goals set forth above.
·       Minimal support for power management inhibits application vendors from supporting or exploiting it.
        Moving power management functionality into the OS makes it available on every machine on which the OS is installed. The level of functionality (power savings, and so on) varies from machine to machine, but users and applications will see the same power interfaces and semantics on all OSPM machines.
        This will enable application vendors to invest in adding power management functionality to their products.
·       Legacy power management algorithms were restricted by the information available to the BIOS that implemented them. This limited the functionality that could be implemented.
        Centralizing power management information and directives from the user, applications, and hardware in the OS allows the implementation of more powerful functionality. For example, an OS can have a policy of dividing I/O operations into normal and lazy. Lazy I/O operations (such as a word processor saving files in the background) would be gathered up into clumps and done only when the required I/O device is powered up for some other reason. A non-lazy I/O request made when the required device was powered down would cause the device to be powered up immediately, the non-lazy I/O request to be carried out, and any pending lazy I/O operations to be done. Such a policy requires knowing when I/O devices are powered up, knowing which application I/O requests are lazy, and being able to assure that such lazy I/O operations do not starve.
        Appliance functions, such as answering machines, require globally coherent power decisions. For example, a telephone-answering application could call the OS and assert, "I am waiting for incoming phone calls; any sleep state the system enters must allow me to wake and answer the telephone in 1 second." Then, when the user presses the "off" button, the system would pick the deepest sleep state consistent with the needs of the phone answering service.
·       BIOS code has become very complex to deal with power management. It is difficult to make work with an OS and is limited to static configurations of the hardware.
        There is much less state information for the BIOS to retain and manage (because the OS manages it).
        Power management algorithms are unified in the OS, yielding much better integration between the OS and the hardware.
        Because additional ACPI tables (Definition Blocks) can be loaded, for example, when a mobile system docks, the OS can deal with dynamic machine configurations.
        Because the BIOS has fewer functions and they are simpler, it is much easier (and therefore cheaper) to implement and support.

·       The existing structure of the PC platform constrains OS and hardware designs.
·       Because ACPI is abstract, the OS can evolve separately from the hardware and, likewise, the hardware from the OS.
·       ACPI is by nature more portable across operating systems and processors. ACPI control methods allow for very flexible implementations of particular features.
1.3   Legacy Support
ACPI provides support for an orderly transition from legacy hardware to ACPI hardware, and allows for both mechanisms to exist in a single machine and be used as needed.
Table 1‑1    Hardware Type vs. OS Type Interaction

Hardware\OS	Legacy OS	ACPI OS with OSPM
Legacy hardware	A legacy OS on legacy hardware does what it always did.	If the OS lacks legacy support, legacy support is completely contained within the hardware functions.
Legacy and ACPI hardware support in machine	It works just like a legacy OS on legacy hardware.	During boot, the OS tells the hardware to switch from legacy to OSPM/ACPI mode and from then on, the system has full OSPM/ACPI support.
ACPI-only hardware	There is no power management.	There is full OSPM/ACPI support.

1.4   OEM Implementation Strategy
Any OEM is, as always, free to build hardware as they see fit. Given the existence of the ACPI specification, two general implementation strategies are possible:
·      An original equipment manufacturer (OEM) can adopt the OS vendor-provided ACPI OSPM software and implement the hardware part of the ACPI specification (for a given platform) in one of many possible ways.
·      An OEM can develop a driver and hardware that are not ACPI-compatible. This strategy opens up even more hardware implementation possibilities. However, OEMs who implement hardware that is OSPM-compatible but not ACPI-compatible will bear the cost of developing, testing, and distributing drivers for their implementation.
1.5   Power and Sleep Buttons
OSPM provides a new appliance interface to consumers particular, it provides for a sleep button that is a "soft" button that does not turn the machine physically off but signals the OS to put the machine in a soft off or sleeping state. ACPI defines two types of these "soft" buttons: one for putting the machine to sleep and one for putting the machine in soft off.
This gives the OEM two different ways to implement machines: A one-button model or a two-button model. The one-button model has a single button that can be used as a power button or a sleep button as determined by user settings. The two-button model has an easily accessible sleep button and a separate power button. In either model, an override feature that forces the machine to the soft-off state without OSPM interaction is also needed to deal with various rare, but problematic, situations.

1.6 ACPI Specification and the Structure Of ACPI
This specification defines ACPI hardware interfaces, ACPI software interfaces and ACPI data structures. This specification also defines the semantics of these interfaces.
Figure 1-1 lays out the software and hardware components relevant to OSPM/ACPI and how they relate to each other. This specification describes the interfaces between components, the contents of the ACPI System Description Tables, and the related semantics of the other ACPI components. Notice that the ACPI System Description Tables, which describe a particular platform's hardware, are at heart of the ACPI implementation and the role of the ACPI System Firmware is primarily to supply the ACPI Tables (rather than a native instruction API).
ACPI is not a software specification; it is not a hardware specification, although it addresses both software and hardware and how they must behave. ACPI is, instead, an interface specification comprised of both software and hardware elements.

Figure 1-1 OSPM/ACPI Global System

There are three run-time components to ACPI:
·       ACPI System Description Tables. Describe the interfaces to the hardware. Some descriptions limit what can be built (for example, some controls are embedded in fixed blocks of registers and the table specifies the address of the register block). Most descriptions allow the hardware to be built in arbitrary ways and can describe arbitrary operation sequences needed to make the hardware function. ACPI Tables containing "Definition Blocks" can make use of a pseudo-code type of language, the interpretation of which is performed by the OS. That is, OSPM contains and uses an interpreter that executes procedures encoded in the pseudo-code language and stored in the ACPI tables containing "Definition Blocks." The pseudo-code language, known as ACPI Machine Language (AML), is a compact, tokenized, abstract type of machine language.
·       ACPI Registers. The constrained part of the hardware interface, described (at least in location) by the ACPI System Description Tables.
·       ACPI System Firmware. Refers to the portion of the firmware that is compatible with the ACPI specifications. Typically, this is the code that boots the machine (as legacy BIOSs have done) and implements interfaces for sleep, wake, and some restart operations. It is called rarely, compared to a legacy BIOS. The ACPI Description Tables are also provided by the ACPI System Firmware.
1.7   OS and Platform Compliance
The ACPI specification contains only interface specifications. ACPI does not contain any platform compliance requirements following sections provide guidelines for class specific platform implementations that reference ACPI-defined interfaces and guidelines for enhancements that operating systems may require to completely support OSPM/ACPI. The minimum feature implementation requirements of an ACPI-compatible OS are also provided.
1.7.1   Platform Implementations of ACPI-defined Interfaces
System platforms implement ACPI-defined hardware interfaces via the platform hardware and ACPI-defined software interfaces and system description tables via the ACPI system firmware. Specific ACPI-defined interfaces and OSPM concepts while appropriate for one class of machine (for example, a mobile system), may not be appropriate for another class of machine (for example, a multi-domain enterprise server). It is beyond the capability and scope of this specification to specify all platform classes and the appropriate ACPI-defined interfaces that should be required for the platform class.
Platform design guide authors are encouraged to require the appropriate ACPI-defined interfaces and hardware requirements suitable to the particular system platform class addressed in a particular design guide. Platform design guides should not define alternative interfaces that provide similar functionality to those defined in the ACPI specification.
1.7.1.1   Recommended Features and Interface Descriptions for Design Guides
Common description text and category names should be used in design guides to describe all features, concepts, and interfaces defined by the ACPI specification as requirements for a platform class. Listed below is the recommended set of high-level text and category names to be used to describe the features, concepts, and interfaces defined by ACPI.
Note: Where definitions or relational requirements of interfaces are localized to a specific section, the section number is provided. The interface definitions and relational requirements of the interfaces specified below are generally spread throughout the ACPI specification. The ACPI specification defines:
System address map reporting interfaces (Section 14)
ACPI System Description Tables (Section 5.2):
Root System Description Pointer (RSDP)
System Description Table Header
Root System Description Table (RSDT)
Fixed ACPI Description Table (FADT)
Firmware ACPI Control Structure (FACS)
Differentiated System Description Table (DSDT)
Secondary System Description Table (SSDT)
Multiple APIC Description Table (MADT)
Smart Battery Table (SBST)
Extended System Description Table (XSDT)
Embedded Controller Boot Resources Table
System Resource Affinity Table (SRAT)
System Locality Information Table (SLIT)
ACPI-defined Fixed Registers Interfaces (Section 4, Section 5.2.9):
Power management timer control/status
Power or sleep button with S5 override (also possible in generic space)
Real time clock wakeup alarm control/status
SCI /SMI routing control/status for Power Management and General-purpose events
System power state controls (sleeping/wake control) (Section 10)
Processor power state control (c states) (Section 8)
Processor throttling control/status (Section 8)
Processor performance state control/status (Section 8)
General-purpose event control/status
Global Lock control/status
System Reset control (Section 4.7.3.6)
Embedded Controller control/status (Section 12)
SMBus Host Controller (HC) control/status (Section 13)
Smart Battery Subsystem (Section 10.1)
ACPI-defined Generic Register Interfaces and object definitions in the ACPI Namespace (Section 4.2, Section 5.6.5):
General-purpose event processing
Motherboard device identification, configuration, and insertion/removal (Section 6)
Thermal zones (Section 11)
Power resource control (Section 7.1)
Device power state control (Section 7.2)
System power state control (Section 7.3)
System indicators (Section 9.1)
Devices and device controls (Section 9):
Processor (Section 8)
Control Method Battery (Section 10)
Smart Battery Subsystem (Section 10)
Mobile Lid
Power or sleep button with S5 override (also possible in fixed space)
Embedded controller (Section 12)
Fan
Generic Bus Bridge
ATA Controller
Floppy Controller
GPE Block
Module
Memory
Global Lock related interfaces

ACPI Event programming model (Section 5.6)

ACPI-defined System BIOS Responsibilities (Section 15)

ACPI-defined State Definitions (Section 2):
Global system power states (G-states, S0, S5)
System sleeping states (S-states S1-S4) (Section 15)
Device power states (D-states (Appendix B))
Processor power states (C-states) (Section 8)
Device and processor performance states (P-states) (Section 3, Section 8)
1.7.1.2   Terminology Examples for Design Guides
The following provides an example of how a client platform design guide, whose goal is to require robust configuration and power management for the system class, could use the recommended terminology to define ACPI requirements.
Important: This example is provided as a guideline for how ACPI terminology can be used should not be interpreted as a statement of ACPI requirements.
Platforms compliant with this platform design guide must implement the following ACPI defined system features, concepts, and interfaces, along with their associated event models:
System address map reporting interfaces
ACPI System Description Tables provided in the system firmware
ACPI-defined Fixed Registers Interfaces:
Power management timer control/status
Power or sleep button with S5 override (may also be implemented in generic register space)
Real time clock wakeup alarm control/status
General-purpose event control/status
SCI /SMI routing control/status for Power Management and General-purpose events
(control required only if system supports legacy mode)
System power state controls (sleeping/wake control)
Processor power state control (for C1)
Global Lock control/status (if Global Lock interfaces are required by the system)

· ACPI-defined Generic Register Interfaces and object definitions in the ACPI Namespace:
General-purpose event processing
Motherboard device identification, configuration, and insertion/removal (Section 6)
System power state control ( Section 7.3)
Devices and device controls:
Processor
Control Method Battery (or Smart Battery Subsystem on a mobile system)
Smart Battery Subsystem (or Control Method Battery on a mobile system)
Power or sleep button with S5 override (may also be implemented in fixed register space)
Global Lock related interfaces when a logical register in the hardware is shared between OS and firmware environments
· ACPI Event programming model (Section 5.6)
· ACPI-defined System BIOS Responsibilities (Section 15)
· ACPI-defined State Definitions:
System sleeping states (At least one system sleeping state, S1-S4, must be implemented)
Device power states (D-states must be implemented in accordance with device class specifications)
Processor power states (All processors must support the C1 Power State)
The following provides an example of how a design guide for systems that execute multiple OS instances, whose goal is to require robust configuration and continuous availability for the system class, could use the recommended terminology to define ACPI related requirements.
Important: This example is provided as a guideline for how ACPI terminology can be used should not be interpreted as a statement of ACPI requirements.
Platforms compliant with this platform design guide must implement the following ACPI defined system features and interfaces, along with their associated event models:
System address map reporting interfaces
ACPI System Description Tables provided in the system firmware
ACPI-defined Fixed Registers Interfaces:
Power management timer control/status
General-purpose event control/status
SCI /SMI routing control/status for Power Management and General-purpose events
(control required only if system supports legacy mode)
System power state controls (sleeping/wake control)
Processor power state control (for C1)
Global Lock control/status (if Global Lock interfaces are required by the system)

·      ACPI-defined Generic Register Interfaces and object definitions in the ACPI Namespace:
General-purpose event processing
Motherboard device identification, configuration, and insertion/removal (Section 6)
System power state control (Section 7.3)
System indicators
Devices and device controls:
Processor
Global Lock related interfaces when a logical register in the hardware is shared between OS and firmware environments
· ACPI Event programming model ( Section 5.6)
· ACPI-defined System BIOS Responsibilities (Section 15)
· ACPI-defined State Definitions:
Processor power states (All processors must support the C1 Power State)
1.7.2   OSPM Implementations
OS enhancements are needed to support ACPI-defined features, concepts, and interfaces, along with their associated event models appropriate to the system platform class upon which the OS executes. This is the implementation of OSPM following outlines the OS enhancements and elements necessary to support all ACPI-defined interfaces. To support ACPI through the implementation of OSPM, the OS needs to be modified to:
·       Use system address map reporting interfaces.
·       Find and consume the ACPI System Description Tables.
·       Interpret ACPI machine language (AML).
·       Enumerate and configure motherboard devices described in the ACPI Namespace.
·       Interface with the power management timer.
·       Interface with the real-time clock wake alarm.
·       Enter ACPI mode (on legacy hardware systems).
·       Implement device power management policy.
·       Implement power resource management.
·       Implement processor power states in the scheduler idle handlers.
·       Control processor and device performance states.
·       Implement the ACPI thermal model.
·       Support the ACPI Event programming model including handling SCI interrupts, managing fixed events, general-purpose events, embedded controller interrupts, and dynamic device support.
·       Support acquisition and release of the Global Lock.
·       Use the reset register to reset the system.
·       Provide APIs to influence power management policy.
·       Implement driver support for ACPI-defined devices.
·       Implement APIs supporting the system indicators.
·       Support all system states S1–S5.
1.7.3   OS Requirements
The following list describes the minimum requirements for an OSPM/ACPI-compatible OS:
·      Use system address map reporting interfaces to get the system address map on Intel Architecture (IA) platforms:
·       INT 15H, E820H - Query System Address Map interface (see section 14, "System Address Map Interfaces")
·       EFI GetMemoryMap() Boot Services Function (see section 14, "System Address Map Interfaces")
·      Find and consume the ACPI System Description Tables (see section 5, "ACPI Software Programming Model").
·      Implementation of an AML interpreter supporting all defined AML grammar elements (see section 18, ACPI Machine Language Specification").
·      Support for the ACPI Event programming model including handling SCI interrupts, managing fixed events, general-purpose events, embedded controller interrupts, and dynamic device support.
·      Enumerate and configure motherboard devices described in the ACPI Namespace.
·      Implement support for the following ACPI devices defined within this specification:
·       Embedded Controller Device (see section 12, "ACPI Embedded Controller Interface Specification")
·       GPE Block Device (see section 9.11, "GPE Block Device")
·       Module Device (see section 9.12, "Module Device")
·      Implementation of the ACPI thermal model (see section 11, "Thermal Management").
·      Support acquisition and release of the Global Lock.
·      OS-directed power management support (device drivers are responsible for maintaining device context as described by the Device Power Management Class Specifications described in Appendix A).
1.8   Target Audience
This specification is intended for the following users:
·      OEMs building hardware containing ACPI-compatible interfaces
·      Operating system and device driver developers
·      BIOS and ACPI system firmware developers
·      CPU and chip set vendors
·      Peripheral vendors
1.9   Document Organization
The ACPI specification document is organized into the following four parts:
·      The first part of the specification (sections 1 through 3) introduces ACPI and provides an executive overview.
·      The second part (sections 4 and 5) defines the ACPI hardware and software programming models.
·      The third part (sections 6 through 16) specifies the ACPI implementation details; this part of the specification is primarily for developers.
·      The fourth part (sections 17 and 18) is technical reference material; section 17 is the ACPI Source Language (ASL) reference, parts of which are referred to by most of the other sections in the document.
·      Appendices contain device class specifications, describing power management characteristics of specific classes of devices, and device class-specific ACPI interfaces.
1.9.1   ACPI Introduction and Overview
The first three sections of the specification provide an executive overview of ACPI.
Section 1:Introduction. Discusses the purpose and goals of the specification, presents an overview of the ACPI-compatible system architecture, specifies the minimum requirements for an ACPI-compatible system, and provides references to related specifications.
Section 2:Definition of Terms. Defines the key terminology used in this specification. In particular, the global system states (Mechanical Off, Soft Off, Sleeping, Working, and Non-Volatile Sleep) are defined in this section, along with the device power state definitions: Off (D3), D2, D1, and Fully-On (D0). Device and processor performance states (P0, P1, �Pn) are also discussed.
Section 3: ACPI Overview. Gives an overview of the ACPI specification in terms of the functional areas covered by the specification: system power management, device power management, processor power management, Plug and Play, handling of system events, battery management, and thermal management.
1.9.2   Programming Models
Sections 4 and 5 define the ACPI hardware and software programming models. This part of the specification is primarily for system designers, developers, and project managers.
All of the implementation-oriented, reference, and platform example sections of the specification that follow (all the rest of the sections of the specification) are based on the models defined in sections 4 and 5. These sections are the heart of the ACPI specification. There are extensive cross-references between the two sections.
Section 4:ACPI Hardware Specification. Defines a set of hardware interfaces that meet the goals of this specification.
Section 5:ACPI Software Programming Model. Defines a set of software interfaces that meet the goals of this specification.
1.9.3   Implementation Details
The third part of the specification defines the implementation details necessary to actually build components that work on an ACPI-compatible platform. This part of the specification is primarily for developers.
Section 6:Configuration. Defines the reserved Plug and Play objects used to configure and assign resources to devices, and share resources and the reserved objects used to track device insertion and removal. Also defines the format of ACPI-compatible resource descriptors.
Section 7:Power and Performance Management. Defines the reserved device power-management objects and the reserved-system power-management objects.
Section 8:Processor Control. Defines how the OS manages the processors' power consumption and other controls while the system is in the working state.
Section 9:ACPI-Specific Device Objects. Lists the integrated devices that need support for some device-specific ACPI controls, along with the device-specific ACPI controls that can be provided. Most device objects are controlled through generic objects and control methods and have generic device IDs; this section discusses the exceptions.
Section 10:Power Source Devices. Defines the reserved battery device and AC adapter objects.
Section 11:Thermal Management. Defines the reserved thermal management objects.
Section 12:ACPI Embedded Controller Interface Specification. Defines the interfaces between an ACPI-compatible OS and an embedded controller.
Section 13:ACPI System Management Bus Interface Specification. Defines the interfaces between an ACPI-compatible OS and a System Management Bus (SMBus) host controller.
Section 14: System Address Map Interfaces. Explains the special INT 15 call for use in ISA/EISA/PCI bus-based systems. This call supplies the OS with a clean memory map indicating address ranges that are reserved and ranges that are available on the motherboard. EFI-based memory address map reporting interfaces are also described. Also describes memory devices.
Section 15:Waking and Sleeping. Defines in detail the transitions between system working and sleeping states and their relationship to wake events. Refers to the reserved objects defined in sections 6, 7, and 8.
Section 16:Non-Uniform Memory Access (NUMA) Architecture Platforms. Discusses in detail how ACPI define interfaces can be used to describe a NUMA architecture platform. Refers to the reserved objects defined in sections 5, 6, 8, and 9.

1.9.4   Technical Reference
The fourth part of the specification contains reference material for developers.
Section 17:ACPI Source Language Reference. Defines the syntax of all the ASL statements that can be used to write ACPI control methods, along with example syntax usage.
Section 18:ACPI Machine Language Specification. Defines the grammar of the language of the ACPI virtual machine language ASL translator (compiler) outputs AML.
Appendix A:Device class specifications. Describes device-specific power management behavior on a per device-class basis.
Appendix B:Video Extensions. Contains video device class-specific ACPI interfaces.
1.10   Related Documents
Power management and Plug and Play specifications for legacy hardware platforms are the following, available from http://www.microsoft.com/whdc/resources/respec/specs/default.mspx:
·      Advanced Power Management (APM) BIOS Specification, Revision 1.2.

· Plug and Play BIOS Specification, Version 1.0a.
Intel Architecture specifications are available from http://developer.intel.com:
Intel� Itanium^TM Architecture Software Developer's Manual, Volumes 1–4, Revision 2.1, Intel Corporation, October 2002.
Itanium^TM Processor Family System Abstraction Layer Specification, Intel Corporation, December 2003 (June 2004 Update).

Extensible Firmware Interface Specification, Version 1.10, December 2002(November 2003 Update).
Documentation and specifications for the Smart Battery System components and the SMBus are available from http://www.sbs-forum.org:
·      Smart Battery Charger Specification, Revision 1.1, Smart Battery System Implementers Forum, December, 1998.
·      Smart Battery Data Specification, Revision 1.1, Smart Battery System Implementers Forum, December, 1998.
·      Smart Battery Selector Specification, Revision 1.1, Smart Battery System Implementers Forum, December, 1998.
·      Smart Battery System Manager Specification, Revision 1.0, Smart Battery System Implementers Forum, December, 1998.
·      System Management Bus Specification, Revision 1.1, Smart Battery System Implementers Forum, December, 1998.

2 Definition of Terms
This specification uses a particular set of terminology, defined in this section. This section has three parts:
General ACPI terms are defined and presented alphabetically.
The ACPI global system states (working, sleeping, soft off, and mechanical off) are defined. Global system states apply to the entire system, and are visible to the user.
The ACPI device power states are defined. Device power states are states of particular devices; as such, they are generally not visible to the user. For example, some devices may be in the off state even though the system as a whole is in the working state. Device states apply to any device on any bus.
2.1 General ACPI Terminology
Advanced Configuration and Power Interface (ACPI)

As defined in this document, ACPI is a method for describing hardware interfaces in terms abstract enough to allow flexible and innovative hardware implementations and concrete enough to allow shrink-wrap OS code to use such hardware interfaces.
ACPI Hardware
Computer hardware with the features necessary to support OSPM and with the interfaces to those features described using the Description Tables as specified by this document.
ACPI Namespace
A hierarchical tree structure in OS-controlled memory that contains named objects. These objects may be data objects, control method objects, bus/device package objects, and so on. The OS dynamically changes the contents of the namespace at run-time by loading and/or unloading definition blocks from the ACPI Tables that reside in the ACPI BIOS. All the information in the ACPI Namespace comes from the Differentiated System Description Table (DSDT), which contains the Differentiated Definition Block, and one or more other definition blocks.
ACPI Machine Language (AML)
Pseudo-code for a virtual machine supported by an ACPI-compatible OS and in which ACPI control methods and objects are written. The AML encoding definition is provided in section 18, "ACPI Machine Language (AML) Specification."
Advanced Programmable Interrupt Controller (APIC)
An interrupt controller architecture commonly found on Intel Architecture-based 32-bit PC systems. The APIC architecture supports multiprocessor interrupt management (with symmetric interrupt distribution across all processors), multiple I/O subsystem support, 8259A compatibility, and inter-processor interrupt support. The architecture consists of local APICs commonly attached directly to processors and I/O APICs commonly in chip sets.
ACPI Source Language (ASL)
The programming language equivalent for AML. ASL is compiled into AML images. The ASL statements are defined in section 17, "ACPI Source Language (ASL) Reference."

Control Method
A control method is a definition of how the OS can perform a simple hardware task. For example, the OS invokes control methods to read the temperature of a thermal zone. Control methods are written in an encoded language called AML that can be interpreted and executed by the ACPI-compatible OS. An ACPI-compatible system must provide a minimal set of control methods in the ACPI tables. The OS provides a set of well-defined control methods that ACPI table developers can reference in their control methods. OEMs can support different revisions of chip sets with one BIOS by either including control methods in the BIOS that test configurations and respond as needed or including a different set of control methods for each chip set revision.
Central Processing Unit (CPU) or Processor
The part of a platform that executes the instructions that do the work. An ACPI-compatible OS can balance processor performance against power consumption and thermal states by manipulating the processor performance controls. The ACPI specification defines a working state, labeled G0 (S0), in which the processor executes instructions. Processor sleeping states, labeled C1 through C3, are also defined. In the sleeping states, the processor executes no instructions, thus reducing power consumption and, potentially, operating temperatures. The ACPI specification also defines processor performance states, where the processor (while in C0) executes instructions, but with lower performance and (potentially) lower power consumption and operating temperature. For more information, see section 8, "Processor Power and Performance State Configuration and Control."
Definition Block
A definition block contains information about hardware implementation and configuration details in the form of data and control methods, encoded in AML. An OEM can provide one or more definition blocks in the ACPI Tables. One definition block must be provided: the Differentiated Definition Block, which describes the base system. Upon loading the Differentiated Definition Block, the OS inserts the contents of the Differentiated Definition Block into the ACPI Namespace. Other definition blocks, which the OS can dynamically insert and remove from the active ACPI Namespace, can contain references to the Differentiated Definition Block more information, see section 5.2.11, "Definition Blocks."
Device
Hardware component outside the core chip set of a platform. Examples of devices are liquid crystal display (LCD) panels, video adapters, Integrated Drive Electronics (IDE) CD-ROM and hard disk controllers, COM ports, and so on. In the ACPI scheme of power management, buses are devices. For more information, see section 3.3.2, "Device Power States."
Device Context
The variable data held by the device; it is usually volatile. The device might forget this information when entering or leaving certain states (for more information, see section 2.3, "Device Power State Definitions."), in which case the OS software is responsible for saving and restoring the information. Device Context refers to small amounts of information held in device peripherals. See System Context.
Differentiated System Description Table (DSDT)
An OEM must supply a DSDT to an ACPI-compatible OS. The DSDT contains the Differentiated Definition Block, which supplies the implementation and configuration information about the base system. The OS always inserts the DSDT information into the ACPI Namespace at system boot time and never removes it.
Extensible Firmware Interface (EFI)
An interface between the OS and the platform firmware. The interface is in the form of data tables that contain platform related information, and boot and run-time service calls that are available to the OS and loader. Together, these provide a standard environment for booting an OS.

Embedded Controller
The general class of microcontrollers used to support OEM-specific implementations, mainly in mobile environments. The ACPI specification supports embedded controllers in any platform design, as long as the microcontroller conforms to one of the models described in this section. The embedded controller performs complex low-level functions through a simple interface to the host microprocessor(s).
Embedded Controller Interface
A standard hardware and software communications interface between an OS driver and an embedded controller. This allows any OS to provide a standard driver that can directly communicate with an embedded controller in the system, thus allowing other drivers within the system to communicate with and use the resources of system embedded controllers (for example, Smart Battery and AML code). This in turn enables the OEM to provide platform features that the OS and applications can use.
Firmware ACPI Control Structure (FACS)
A structure in read/write memory that the BIOS uses for handshaking between the firmware and the OS. The FACS is passed to an ACPI-compatible OS via the Fixed ACPI Description Table (FADT). The FACS contains the system's hardware signature at last boot, the firmware waking vector, and the Global Lock.
Fixed ACPI Description Table (FADT)
A table that contains the ACPI Hardware Register Block implementation and configuration details that the OS needs to directly manage the ACPI Hardware Register Blocks, as well as the physical address of the DSDT, which contains other platform implementation and configuration details. An OEM must provide an FADT to an ACPI-compatible OS in the RSDT/XSDT. The OS always inserts the namespace information defined in the Differentiated Definition Block in the DSDT into the ACPI Namespace at system boot time, and the OS never removes it.
Fixed Features
A set of features offered by an ACPI interface ACPI specification places restrictions on where and how the hardware programming model is generated. All fixed features, if used, are implemented as described in this specification so that OSPM can directly access the fixed feature registers.
Fixed Feature Events
A set of events that occur at the ACPI interface when a paired set of status and event bits in the fixed feature registers are set at the same time. When a fixed feature event occurs, a system control interrupt (SCI is raised. For ACPI fixed feature events, OSPM (or an ACPI-aware driver) acts as the event handler.
Fixed Feature Registers
A set of hardware registers in fixed feature register space at specific address locations in system I/O address space. ACPI defines register blocks for fixed features (each register block gets a separate pointer from the FADT). For more information, see section 4.6, "ACPI Hardware Features."
General-Purpose Event Registers
The general-purpose event registers contain the event programming model for generic features. All general-purpose events generate SCIs.
Generic Feature
A generic feature of a platform is value-added hardware implemented through control methods and general-purpose events.

Global System States
Global system states apply to the entire system, and are visible to the user. The various global system states are labeled G0 through G3 in the ACPI specification. For more information, see section 2.2, "Global System State Definitions."
Ignored Bits
Some unused bits in ACPI hardware registers are designated as "ignored" in the ACPI specification. Ignored bits are undefined and can return zero or one (in contrast to reserved bits, which always return zero). Software ignores ignored bits in ACPI hardware registers on reads and preserves ignored bits on writes.
Intel Architecture-Personal Computer (IA-PC)
A general descriptive term for computers built with processors conforming to the architecture defined by the Intel processor family based on the Intel Architecture instruction set and having an industry-standard PC architecture.
I/O APIC
An Input/Output Advanced Programmable Interrupt Controller routes interrupts from devices to the processor's local APIC.
I/O SAPIC
An Input/Output Streamlined Advanced Programmable Interrupt Controller routes interrupts from devices to the processor's local APIC.
Legacy
A computer state where power management policy decisions are made by the platform hardware/firmware shipped with the system. The legacy power management features found in today's systems are used to support power management in a system that uses a legacy OS that does not support the OS-directed power management architecture.
Legacy Hardware
A computer system that has no ACPI or OSPM power management support.
Legacy OS
An OS that is not aware of and does not direct the power management functions of the system. Included in this category are operating systems with APM 1.x support.
Local APIC
A local Advanced Programmable Interrupt Controller receives interrupts from the I/O APIC.
Local SAPIC
A local Streamlined Advanced Programmable Interrupt Controller receives interrupts from the I/O SAPIC.
Multiple APIC Description Table (MADT)
The Multiple APIC Description Table (MADT) is used on systems supporting the APIC and SAPIC to describe the APIC implementation. Following the MADT is a list of APIC/SAPIC structures that declare the APIC/SAPIC features of the machine.
Object
The nodes of the ACPI Namespace are objects inserted in the tree by the OS using the information in the system definition tables. These objects can be data objects, package objects, control method objects, and so on. Package objects refer to other objects. Objects also have type, size, and relative name.
Object name
Part of the ACPI Namespace. There is a set of rules for naming objects.

Operating System-directed Power Management (OSPM)
A model of power (and system) management in which the OS plays a central role and uses global information to optimize system behavior for the task at hand.
Package
An array of objects.
Power Button
A user push button or other switch contact device that switches the system from the sleeping/soft off state to the working state, and signals the OS to transition to a sleeping/soft off state from the working state.
Power Management
Mechanisms in software and hardware to minimize system power consumption, manage system thermal limits, and maximize system battery life. Power management involves trade-offs among system speed, noise, battery life, processing speed, and alternating current (AC) power consumption. Power management is required for some system functions, such as appliance (for example, answering machine, furnace control) operations.
Power Resources
Resources (for example, power planes and clock sources) that a device requires to operate in a given power state.
Power Sources
The battery (including a UPS battery) and AC line powered adapters or power supplies that supply power to a platform.
Register Grouping
Consists of two register blocks (it has two pointers to two different blocks of registers). The fixed-position bits within a register grouping can be split between the two register blocks. This allows the bits within a register grouping to be split between two chips.
Reserved Bits
Some unused bits in ACPI hardware registers are designated as "Reserved" in the ACPI specification. For future extensibility, hardware-register reserved bits always return zero, and data writes to them have no side effects. OSPM implementations must write zeros to all reserved bits in enable and status registers and preserve bits in control registers.
Root System Description Pointer (RSDP)
An ACPI-compatible system must provide an RSDP in the system's low address space. This structure's only purpose is to provide the physical address of the RSDT and XSDT.
Root System Description Table (RSDT)
A table with the signature 'RSDT,' followed by an array of physical pointers to other system description tables. The OS locates that RSDT by following the pointer in the RSDP structure.
Secondary System Description Table (SSDT)
SSDTs are a continuation of the DSDT. Multiple SSDTs can be used as part of a platform description. After the DSDT is loaded into the ACPI Namespace, each secondary description table listed in the RSDT/XSDT with a unique OEM Table ID is loaded. This allows the OEM to provide the base support in one table, while adding smaller system options in other tables.
Note: Additional tables can only add data; they cannot overwrite data from previous tables.
Sleep Button
A user push button that switches the system from the sleeping/soft off state to the working state, and signals the OS to transition to a sleeping state from the working state.

Smart Battery Subsystem
A battery subsystem that conforms to the following specifications: Smart Battery and either Smart Battery System Manager or Smart Battery Charger and Selector—and the additional ACPI requirements.
Smart Battery Table
An ACPI table used on platforms that have a Smart Battery subsystem. This table indicates the energy-level trip points that the platform requires for placing the system into different sleeping states and suggested energy levels for warning the user to transition the platform into a sleeping state.
System Management Bus (SMBus)
A two-wire interface based upon the I�C protocol SMBus is a low-speed bus that provides positive addressing for devices, as well as bus arbitration.
SMBus Interface
A standard hardware and software communications interface between an OS bus driver and an SMBus controller.
Streamlined Advanced Programmable Interrupt Controller (SAPIC)
An advanced APIC commonly found on Intel Itanium Processor Family-based 64-bit systems.
System Context
The volatile data in the system that is not saved by a device driver.
System Control Interrupt (SCI)
A system interrupt used by hardware to notify the OS of ACPI events. The SCI is an active, low, shareable, level interrupt.
System Management Interrupt (SMI)

An OS-transparent interrupt generated by interrupt events on legacy systems. By contrast, on ACPI systems, interrupt events generate an OS-visible interrupt that is shareable (edge-style interrupts will not work). Hardware platforms that want to support both legacy operating systems and ACPI systems must support a way of re-mapping the interrupt events between SMIs and SCIs when switching between ACPI and legacy models.
Thermal States
Thermal states represent different operating environment temperatures within thermal zones of a system. A system can have one or more thermal zones; each thermal zone is the volume of space around a particular temperature-sensing device. The transitions from one thermal state to another are marked by trip points, which are implemented to generate an SCI when the temperature in a thermal zone moves above or below the trip point temperature.
Extended Root System Description Table (XSDT)
The XSDT provides identical functionality to the RSDT but accommodates physical addresses of DESCRIPTION HEADERs that are larger than 32-bits. Notice that both the XSDT and the RSDT can be pointed to by the RSDP structure.

2.2   Global System State Definitions
Global system states (Gx states) apply to the entire system and are visible to the user.
Global system states are defined by six principal criteria:
1.     Does application software run?
2.     What is the latency from external events to application response?
3.     What is the power consumption?
4.     Is an OS reboot required to return to a working state?
5.     Is it safe to disassemble the computer?
6.     Can the state be entered and exited electronically?
Following is a list of the system states:
G3 Mechanical Off
A computer state that is entered and left by a mechanical means (for example, turning off the system's power through the movement of a large red switch). Various government agencies and countries require this operating mode. It is implied by the entry of this off state through a mechanical means that no electrical current is running through the circuitry and that it can be worked on without damaging the hardware or endangering service personnel. The OS must be restarted to return to the Working state. No hardware context is retained. Except for the real-time clock, power consumption is zero.
G2/S5 Soft Off
A computer state where the computer consumes a minimal amount of power. No user mode or system mode code is run. This state requires a large latency in order to return to the Working state. The system's context will not be preserved by the hardware. The system must be restarted to return to the Working state. It is not safe to disassemble the machine in this state.
G1 Sleeping
A computer state where the computer consumes a small amount of power, user mode threads are not being executed, and the system "appears" to be off (from an end user's perspective, the display is off, and so on). Latency for returning to the Working state varies on the wake environment selected prior to entry of this state (for example, whether the system should answer phone calls). Work can be resumed without rebooting the OS because large elements of system context are saved by the hardware and the rest by system software. It is not safe to disassemble the machine in this state.
G0 Working
A computer state where the system dispatches user mode (application) threads and they execute. In this state, peripheral devices (peripherals) are having their power state changed dynamically. The user can select, through some UI, various performance/power characteristics of the system to have the software optimize for performance or battery life system responds to external events in real time. It is not safe to disassemble the machine in this state.

S4 Non-Volatile Sleep
A special global system state that allows system context to be saved and restored (relatively slowly) when power is lost to the motherboard. If the system has been commanded to enter S4, the OS will write all system context to a file on non-volatile storage media and leave appropriate context markers. The machine will then enter the S4 state. When the system leaves the Soft Off or Mechanical Off state, transitioning to Working (G0) and restarting the OS, a restore from a NVS file can occur. This will only happen if a valid non-volatile sleep data set is found, certain aspects of the configuration of the machine have not changed, and the user has not manually aborted the restore. If all these conditions are met, as part of the OS restarting, it will reload the system context and activate it. The net effect for the user is what looks like a resume from a Sleeping (G1) state (albeit slower). The aspects of the machine configuration that must not change include, but are not limited to, disk layout and memory size. It might be possible for the user to swap a PC Card or a Device Bay device, however.
Notice that for the machine to transition directly from the Soft Off or Sleeping states to S4, the system context must be written to non-volatile storage by the hardware; entering the Working state first so that the OS or BIOS can save the system context takes too long from the user's point of view. The transition from Mechanical Off to S4 is likely to be done when the user is not there to see it.
Because the S4 state relies only on non-volatile storage, a machine can save its system context for an arbitrary period of time (on the order of many years).
Table 2-1 Summary of Global Power States

Global system state	Software runs	Latency	Power consumption	OS restart required	Safe to disassemble computer	Exit state electronically
G0 Working	Yes	0	Large	No	No	Yes
G1 Sleeping	No	>0, varies with sleep state	Smaller	No	No	Yes
G2/S5 Soft Off	No	Long	Very near 0	Yes	No	Yes
G3 Mechanical Off	No	Long	RTC battery	Yes	Yes	No

Notice that the entries for G2/S5 and G3 in the Latency column of the above table are "Long." This implies that a platform designed to give the user the appearance of "instant-on," similar to a home appliance device, will use the G0 and G1 states almost exclusively (the G3 state may be used for moving the machine or repairing it).
2.3   Device Power State Definitions
Device power states are states of particular devices; as such, they are generally not visible to the user. For example, some devices may be in the Off state even though the system as a whole is in the Working state.
Device states apply to any device on any bus. They are generally defined in terms of four principal criteria:
·      Power consumption. How much power the device uses.
·      Device context. How much of the context of the device is retained by the hardware. The OS is responsible for restoring any lost device context (this may be done by resetting the device).
·      Device driver. What the device driver must do to restore the device to full on.
·      Restore time. How long it takes to restore the device to full on.
The device power states are defined below, although very generically. Many devices do not have all four power states defined. Devices may be capable of several different low-power modes, but if there is no user-perceptible difference between the modes, only the lowest power mode will be used. The Device Class Power Management Specifications, included in Appendix A of this specification, describe which of these power states are defined for a given type (class) of device and define the specific details of each power state for that device class. For a list of the available Device Class Power Management Specifications, see "Appendix A:Device Class Specifications."
D3 Off
Power has been fully removed from the device device context is lost when this state is entered, so the OS software will reinitialize the device when powering it back on. Since device context and power are lost, devices in this state do not decode their address lines. Devices in this state have the longest restore times. All classes of devices define this state.
D2
The meaning of the D2 Device State is defined by each device class. Many device classes may not define D2. In general, D2 is expected to save more power and preserve less device context than D1 or D0. Buses in D2 may cause the device to lose some context (for example, by reducing power on the bus, thus forcing the device to turn off some of its functions).
D1
The meaning of the D1 Device State is defined by each device class. Many device classes may not define D1. In general, D1 is expected to save less power and preserve more device context than D2.
D0 Fully-On
This state is assumed to be the highest level of power consumption. The device is completely active and responsive, and is expected to remember all relevant context continuously.

Table 2-2 Summary of Device Power States

Device State	Power Consumption	Device Context Retained	Driver Restoration
D0 - Fully-On	As needed for operation	All	None
D1	D0>D1>D2>D3	>D2	<D2
D2	D0>D1>D2>D3	<D1	>D1
D3 - Off	0	None	Full initialization and load

Note: Devices often have different power modes within a given state. Devices can use these modes as long as they can automatically transparently switch between these modes from the software, without violating the rules for the current Dx state the device is in. Low-power modes that adversely affect performance (in other words, low speed modes) or that are not transparent to software cannot be done automatically in hardware; the device driver must issue commands to use these modes.
2.4 Sleeping State Definitions
Sleeping states (Sx states) are types of sleeping states within the global sleeping state, G1 Sx states are briefly defined below. For a detailed definition of the system behavior within each Sx state, see section 7.3.4, "System \_Sx style='font-style:normal'> States." For a detailed definition of the transitions between each of the Sx states, see section 15.1, "Sleeping States."
S1 Sleeping State
The S1 sleeping state is a low wake latency sleeping state. In this state, no system context is lost (CPU or chip set) and hardware maintains all system context.
S2 Sleeping State
The S2 sleeping state is a low wake latency sleeping state. This state is similar to the S1 sleeping state except that the CPU and system cache context is lost (the OS is responsible for maintaining the caches and CPU context). Control starts from the processor's reset vector after the wake event.
S3 Sleeping State
The S3 sleeping state is a low wake latency sleeping state where all system context is lost except system memory. CPU, cache, and chip set context are lost in this state. Hardware maintains memory context and restores some CPU and L2 configuration context. Control starts from the processor's reset vector after the wake event.
S4 Sleeping State
The S4 sleeping state is the lowest power, longest wake latency sleeping state supported by ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices. Platform context is maintained.
S5 Soft Off State
The S5 state is similar to the S4 state except that the OS does not save any context system is in the "soft" off state and requires a complete boot when it wakes. Software uses a different state value to distinguish between the S5 state and the S4 state to allow for initial boot operations within the BIOS to distinguish whether or not the boot is going to wake from a saved memory image.

2.5 Processor Power State Definitions
Processor power states (Cx states) are processor power consumption and thermal management states within the global working state, G0. The Cx states possess specific entry and exit semantics and are briefly defined below. For a more detailed definition of each Cx state, see section 8.1, "Processor Power States."

C0 Processor Power State
While the processor is in this state, it executes instructions.
C1 Processor Power State
This processor power state has the lowest latency hardware latency in this state must be low enough that the operating software does not consider the latency aspect of the state when deciding whether to use it. Aside from putting the processor in a non-executing power state, this state has no other software-visible effects.
C2 Processor Power State
The C2 state offers improved power savings over the C1 state. The worst-case hardware latency for this state is provided via the ACPI system firmware and the operating software can use this information to determine when the C1 state should be used instead of the C2 state. Aside from putting the processor in a non-executing power state, this state has no other software-visible effects.
C3 Processor Power State
The C3 state offers improved power savings over the C1 and C2 states. The worst-case hardware latency for this state is provided via the ACPI system firmware and the operating software can use this information to determine when the C2 state should be used instead of the C3 state. While in the C3 state, the processor's caches maintain state but ignore any snoops operating software is responsible for ensuring that the caches maintain coherency.
2.6   Device and Processor Performance State Definitions
Device and Processor performance states (Px states) are power consumption and capability states within the active/executing states, C0 for processors and D0 for devices Px states are briefly defined below. For a more detailed definition of each Px state from a processor perspective, see section 8.4.4, "Processor Performance Control." For a more detailed definition of each Px state from a device perspective see section 3.6, "Device and Processor Performance States," and the device class specifications in Appendix A.
P0 Performance State
While a device or processor is in this state, it uses its maximum performance capability and may consume maximum power.
P1 Performance State
In this performance power state, the performance capability of a device or processor is limited below its maximum and consumes less than maximum power.
Pn Performance State
In this performance state, the performance capability of a device or processor is at its minimum level and consumes minimal power while remaining in an active state. State n is a maximum number and is processor or device dependent. Processors and devices may define support for an arbitrary number of performance states not to exceed 16.

3   ACPI Overview
Platforms compliant with the ACPI specification provide OSPM with direct and exclusive control over the power management and motherboard device configuration functions of a computer. During OS initialization, OSPM takes over these functions from legacy implementations such as the APM BIOS, SMM-based firmware, legacy applications, and the PNPBIOS. Having done this, OSPM is responsible for handling motherboard device configuration events as well as for controlling the power, performance, and thermal status of the system based on user preference, application requests and OS imposed Quality of Service (QOS) / usability goals. ACPI provides low-level interfaces that allow OSPM to perform these functions. The functional areas covered by the ACPI specification are:
·       System power management. ACPI defines mechanisms for putting the computer as a whole in and out of system sleeping states. It also provides a general mechanism for any device to wake the computer.
·       Device power management. ACPI tables describe motherboard devices, their power states, the power planes the devices are connected to, and controls for putting devices into different power states. This enables the OS to put devices into low-power states based on application usage.
·       Processor power management. While the OS is idle but not sleeping, it will use commands described by ACPI to put processors in low-power states.
·       Device and processor performance management. While the system is active, OSPM will transition devices and processors into different performance states, defined by ACPI, to achieve a desirable balance between performance and energy conservation goals as well as other environmental requirements (for example, visibility and acoustics).
·       Configuration / Plug and Play. ACPI specifies information used to enumerate and configure motherboard devices. This information is arranged hierarchically so when events such as docking and undocking take place, the OS has precise, a priori knowledge of which devices are affected by the event.
·       System Events. ACPI provides a general event mechanism that can be used for system events such as thermal events, power management events, docking, device insertion and removal, and so on. This mechanism is very flexible in that it does not define specifically how events are routed to the core logic chip set.
·       Battery management. Battery management policy moves from the APM BIOS to the ACPI OS. An ACPI-compatible battery device needs either a Smart Battery subsystem interface, which is controlled by the OS directly through the embedded controller interface, or a Control Method Battery interface. A Control Method Battery interface is completely defined by AML control methods, allowing an OEM to choose any type of the battery and any kind of communication interface supported by ACPI. The battery must comply with the requirements of its interface, as described either herein or in other applicable standards. The OS may choose to alter the behavior of the battery, for example, by adjusting the Low Battery or Battery Warning trip point. When there are multiple batteries present, the battery subsystem is not required to perform any synthesis of a "composite battery" from the data of the separate batteries. In cases where the battery subsystem does not synthesize a "composite battery" from the separate battery's data, the OS must provide that synthesis.
·       Thermal management. Since the OS controls the power and performance states of devices and processors, ACPI also addresses system thermal management. It provides a simple, scaleable model that allows OEMs to define thermal zones, thermal indicators, and methods for cooling thermal zones.

·       Embedded Controller. ACPI defines a standard hardware and software communications interface between an OS bus enumerator and an embedded controller. This allows any OS to provide a standard bus enumerator that can directly communicate with an embedded controller in the system, thus allowing other drivers within the system to communicate with and use the resources of system embedded controllers. This in turn enables the OEM to provide platform features that the OS and applications can use.
·       SMBus Controller. ACPI defines a standard hardware and software communications interface between an OS bus driver and an SMBus Controller. This allows any OS to provide a standard bus driver that can directly communicate with SMBus devices in the system. This in turn enables the OEM to provide platform features that the OS and applications can use.
OSPM's mission is to optimally configure the platform and to optimally manage the system's power, performance, and thermal status given the user's preferences and while supporting OS imposed Quality of Service (QOS) / usability goals achieve these goals, ACPI requires that once an ACPI compliant platform is in ACPI mode, the platform's hardware, firmware, or other non-OS software must not manipulate the platform's configuration, power, performance, and thermal control interfaces independently of OSPM. OSPM alone is responsible for coordinating the configuration, power management, performance management, and thermal control policy of the system. Manipulation of these interfaces independently of OSPM undermines the purpose of OSPM/ACPI and may adversely impact the system's configuration, power, performance, and thermal policy goals. There are two exceptions to this requirement. The first is in the case of the possibility of damage to a system from an excessive thermal conditions where an ACPI compatible OS is present and OSPM latency is insufficient to remedy an adverse thermal condition. In this case, the platform may exercise a failsafe thermal control mechanism that reduces the performance of a system component to avoid damage. If this occurs, the platform must notify OSPM of the performance reduction if the reduction is of significant duration (in other words, if the duration of reduced performance could adversely impact OSPM's power or performance control policy - operating system vendors can provide guidance in this area). The second exception is the case where the platform contains Active cooling devices but does not contain Passive cooling temperature trip points or controls,. In this case, a hardware based Active cooling mechanism may be implemented without impacting OSPM's goals. Any platform that requires both active and passive cooling must allow OSPM to manage the platform thermals via ACPI defined active and passive cooling interfaces.
3.1   System Power Management
Under OSPM, the OS directs all system and device power state transitions. Employing user preferences and knowledge of how devices are being used by applications, the OS puts devices in and out of low-power states. Devices that are not being used can be turned off. Similarly, the OS uses information from applications and user settings to put the system as a whole into a low- power state. The OS uses ACPI to control power state transitions in hardware.

3.2 Power States
From a user-visible level, the system can be thought of as being in one of the states in the following diagram:

Figure 3-1 Global System Power States and Transitions
See section 2.2, "Global System State Definitions," for detailed definitions of these states.
In general use, computers alternate between the Working and Sleeping states. In the Working state, the computer is used to do work. User-mode application threads are dispatched and running. Individual devices can be in low-power (Dx) states and processors can be in low-power (Cx) states if they are not being used. Any device the system turns off because it is not actively in use can be turned on with short latency. (What "short" means depends on the device. An LCD display needs to come on in sub-second times, while it is generally acceptable to wait a few seconds for a printer to wake.)
The net effect of this is that the entire machine is functional in the Working state. Various Working sub-states differ in speed of computation, power used, heat produced, and noise produced. Tuning within the Working state is largely about trade-offs among speed, power, heat, and noise.

When the computer is idle or the user has pressed the power button, the OS will put the computer into one of the sleeping (Sx) states. No user-visible computation occurs in a sleeping state. The sleeping sub-states differ in what events can arouse the system to a Working state, and how long this takes. When the machine must awaken to all possible events or do so very quickly, it can enter only the sub-states that achieve a partial reduction of system power consumption. However, if the only event of interest is a user pushing on a switch and a latency of minutes is allowed, the OS could save all system context into an NVS file and transition the hardware into the S4 sleeping state. In this state, the machine draws almost zero power and retains system context for an arbitrary period of time (years or decades if needed).
The other states are used less often. Computers that support legacy BIOS power management interfaces boot in the Legacy state and transition to the Working state when an ACPI OS loads. A system without legacy support (for example, a RISC system) transitions directly from the Mechanical Off state to the Working state. Users typically put computers into the Mechanical Off state by flipping the computer's mechanical switch or by unplugging the computer.
3.2.1   Power Button
In legacy systems, the power button typically either forces the machine into Soft Off or Mechanical Off or, on a laptop, forces it to some sleeping state. No allowance is made for user policy (such as the user wants the machine to "come on" in less than 1 second with all context as it was when the user turned the machine "off"), system alert functions (such as the system being used as an answering machine or fax machine), or application function (such as saving a user file).
In an OSPM system, there are two switches. One is to transition the system to the Mechanical Off state. A mechanism to stop current flow is required for legal reasons in some jurisdictions (for example, in some European countries). The other is the "main" power button. This is in some obvious place (for example, beside the keyboard on a laptop). Unlike legacy on/off buttons, all it does is send a request to the system. What the system does with this request depends on policy issues derived from user preferences, user function requests, and application data.
3.2.2   Platform Power Management Characteristics
3.2.2.1   Mobile PC
Mobile PCs will continue to have aggressive power management functionality. Going to OSPM/ACPI will allow enhanced power savings techniques and more refined user policies.
Aspects of mobile PC power management in the ACPI specification are thermal management (see section 11, "Thermal Management") and the embedded controller interface (see section 12, "ACPI Embedded Controller Interface Specification").

3.2.2.2   Desktop PCs
Power-managed desktops will be of two types, though the first type will migrate to the second over time.
·       Ordinary "Green PC." Here, new appliance functions are not the issue. The machine is really only used for productivity computations. At least initially, such machines can get by with very minimal function. In particular, they need the normal ACPI timers and controls, but don't need to support elaborate sleeping states, and so on. They, however, do need to allow the OS to put as many of their devices/resources as possible into device standby and device off states, as independently as possible (to allow for maximum compute speed with minimum power wasted on unused devices). Such PCs will also need to support wake from the sleeping state by means of a timer, because this allows administrators to force them to turn on just before people are to show up for work.
·       Home PC. Computers are moving into home environments where they are used in entertainment centers and to perform tasks like answering the phone. A home PC needs all of the functionality of the ordinary green PC. In fact, it has all of the ACPI power functionality of a laptop except for docking and lid events (and need not have any legacy power management). Note that there is also a thermal management aspect to a home PC, as a home PC user wants the system to run as quietly as possible, often in a thermally constrained environment.
3.2.2.3   Multiprocessor and Server PCs
Perhaps surprisingly, server machines often get the largest absolute power savings. Why? Because they have the largest hardware configurations and because it's not practical for somebody to hit the off switch when they leave at night.
·       Day Mode. In day mode, servers are power-managed much like a corporate ordinary green PC, staying in the Working state all the time, but putting unused devices into low-power states whenever possible. Because servers can be very large and have, for example, many disk spindles, power management can result in large savings. OSPM allows careful tuning of when to do this, thus making it workable.
·       Night Mode. In night mode, servers look like home PCs. They sleep as deeply as they can and are still able to wake and answer service requests coming in over the network, phone links, and so on, within specified latencies. So, for example, a print server might go into deep sleep until it receives a print job at 3 A.M., at which point it wakes in perhaps less than 30 seconds, prints the job, and then goes back to sleep the print request comes over the LAN, then this scenario depends on an intelligent LAN adapter that can wake the system in response to an interesting received packet.
3.3   Device Power Management
This section describes ACPI-compatible device power management. The ACPI device power states are introduced, the controls and information an ACPI-compatible OS needs to perform device power management are discussed, the wake operation devices use to wake the computer from a sleeping state is described, and an example of ACPI-compatible device management using a modem is given.

3.3.1 Power Management Standards
To manage power of all the devices in the system, the OS needs standard methods for sending commands to a device. These standards define the operations used to manage power of devices on a particular I/O interconnect and the power states that devices can be put into. Defining these standards for each I/O interconnect creates a baseline level of power management support the OS can utilize. Independent Hardware Vendors (IHVs) do not have to spend extra time writing software to manage power of their hardware, because simply adhering to the standard gains them direct OS support. For OS vendors, the I/O interconnect standards allow the power management code to be centralized in the driver for each I/O interconnect. Finally, I/O interconnect-driven power management allows the OS to track the states of all devices on a given I/O interconnect. When all the devices are in a given state (or example, D3 - off), the OS can put the entire I/O interconnect into the power supply mode appropriate for that state (for example, D3 - off).
I/O interconnect-level power management specifications are written for a number of buses including:
· PCI

· PCI Express
· CardBus

· USB

·       IEEE 1394
3.3.2   Device Power States
To unify nomenclature and provide consistent behavior across devices, standard definitions are used for the power states of devices. Generally, these states are defined in terms of the following criteria:
·       Power consumption.             How much power the device uses.
·       Device context                      How much of the context of the device is retained by the hardware.
·       Device driver.                      What the device driver must do to restore the device to fully on.
·       Restore latency.                    How long it takes to restore the device to fully on.
More specifically, power management specifications for each class of device (for example, modem, network adapter, hard disk, and so on) more precisely define the power states and power policy for the class section 2.3, "Device Power State Definitions," for the detailed description of the four general device power states (D0-D3).
3.3.3   Device Power State Definitions
The device power state definitions are device-independent, but classes of devices on a bus must support some consistent set of power-related characteristics. For example, when the bus-specific mechanism to set the device power state to a given level is invoked, the actions a device might take and the specific sorts of behaviors the OS can assume while the device is in that state will vary from device type to device type. For a fully integrated device power management system, these class-specific power characteristics must also be standardized:
·      Device Power State Characteristics. Each class of device has a standard definition of target power consumption levels, state-change latencies, and context loss.
·      Minimum Device Power Capabilities. Each class of device has a minimum standard set of power capabilities.
·      Device Functional Characteristics. Each class of device has a standard definition of what subset of device functionality or features is available in each power state (for example, the net card can receive, but cannot transmit; the sound card is fully functional except that the power amps are off, and so on).
·      Device Wakeup Characteristics. Each class of device has a standard definition of its wake policy.
The Microsoft Device Class Power Management specifications define these power state characteristics for each class of device.

3.4   Controlling Device Power
ACPI interfaces provides control and information needed to perform device power management. ACPI interfaces describe to OSPM the capabilities of all the devices it controls. It also gives the OS the control methods used to set the power state or get the power status for each device. Finally, it has a general scheme for devices to wake the machine.
Note: Other buses enumerate some devices on the main board. For example, PCI devices are reported through the standard PCI enumeration mechanisms. Power management of these devices is handled through their own bus specification (in this case, PCI) other devices on the main board are handled through ACPI Specifically, the ACPI table lists legacy devices that cannot be reported through their own bus specification, the root of each bus in the system, and devices that have additional power management or configuration options not covered by their own bus specification.
For more detailed information see section 7, "Power and Performance Management."
3.4.1   Getting Device Power Capabilities
As the OS enumerates devices in the system, it gets information about the power management features that the device supports Differentiated Definition Block given to the OS by the BIOS describes every device handled by ACPI. This description contains the following information:
·      A description of what power resources (power planes and clock sources) the device needs in each power state that the device supports example, a device might need a high power bus and a clock in the D0 state but only a low-power bus and no clock in the D2 state.
·      A description of what power resources a device needs in order to wake the machine (or none to indicate that the device does not support wake). The OS can use this information to infer what device and system power states from which the device can support wake.
·      The optional control method the OS can use to set the power state of the device and to get and set resources.
In addition to describing the devices handled by ACPI, the table lists the power planes and clock sources themselves and the control methods for turning them on and off. For detailed information, see section 7, "Power and Performance Management."
3.4.2   Setting Device Power States
OSPM uses the Set Power State operation to put a device into one of the four power states.
When a device is put in a lower power state, it configures itself to draw as little power from the bus as possible. The OS tracks the state of all devices on the bus, and will put the bus in the best power state based on the current device requirements on that bus. For example, if all devices on a bus are in the D3 state, the OS will send a command to the bus control chip set to remove power from the bus (thus putting the bus in the D3 state). If a particular bus supports a low-power supply state, the OS puts the bus in that state if all devices are in the D1 or D2 state. Whatever power state a device is in, the OS must be able to issue a Set Power State command to resume the device.
Note: The device does not need to have power to do this. The OS must turn on power to the device before it can send commands to the device.
OSPM also uses the Set Power State operation to enable power management features such as wake (described in section 7, "Power and Performance Management.").

When a device is to be set in a particular power state using the ACPI interface, the OS first decides which power resources will be used and which can be turned off. The OS tracks all the devices on a given power resource. When all the devices on a resource have been turned off, the OS turns off that power resource by running a control method. If a power resource is turned off and one of the devices on that resource needs to be turned on, the OS first turns on the power resource using a control method and then signals the device to turn on. The time that the OS must wait for the power resource to stabilize after turning it on or off is described in the description table. The OS uses the time base provided by the Power Management Timer to measure these time intervals.
Once the power resources have been switched, the OS executes the appropriate control method to put the device in that power state. Notice that this might not mean that power is removed from the device. If other active devices are sharing a power resource, the power resources will remain on.
3.4.3 Getting Device Power Status
OSPM uses the Get Power Status operation to determine the current power configuration (states and features), as well as the status of any batteries supported by the device. The device can signal an SCI to inform the OS of changes in power status. For example, a device can trigger an interrupt to inform the OS that the battery has reached low power level.
Devices use the ACPI event model to signal power status changes (for example, battery status changes) to OSPM. The platform signals events to the OS via the SCI interrupt. An SCI interrupt status bit is set to indicate the event to the OS. The OS runs the control method associated with the event. This control method signals to the OS which device has changed.
ACPI supports two types of batteries: batteries that report only basic battery status information and batteries that support the Smart Battery System Implementers Forum Smart Battery Specification. For batteries that report only basic battery status information (such as total capacity and remaining capacity), the OS uses control methods from the battery's description table to read this information. To read status information for Smart Batteries, the OS can use a standard Smart Battery driver that directly interfaces to Smart Batteries through the appropriate bus enumerator.
3.4.4 Waking the Computer
The wake operation enables devices to wake the computer from a sleeping power state. This operation must not depend on the CPU because the CPU will not be executing instructions.
The OS ensures any bridges between the device and the core logic are in the lowest power state in which they can still forward the wake signal. When a device with wake enabled decides to wake the machine, it sends the defined signal on its bus. Bus bridges must forward this signal to upstream bridges using the appropriate signal for that bus. Thus, the signal eventually reaches the core chip set (for example, an ACPI chip set), which in turn wakes the machine.
Before putting the machine in a sleeping power state, the OS determines which devices are needed to wake the machine based on application requests, and then enables wake on those devices in a device and bus specific manner.
The OS enables the wake feature on devices by setting that device's SCI Enable bit. The location of this bit is listed in the device's entry in the description table. Only devices that have their wake feature enabled can wake the machine. The OS keeps track of the power states that the wake devices support, and keeps the machine in a power state in which the wake can still wake the machine^[1] (based on capabilities reported in the description table).

When the computer is in the Sleeping state and a wake device decides to wake the machine, it signals to the ACPI chip set. The SCI status bit corresponding to the device waking the machine is set, and the ACPI chip set resumes the machine. After the OS is running again, it clears the bit and handles the event that caused the wake. The control method for this event then uses the Notify command to tell the OS which device caused the wake.
Note: Besides using ACPI mechanism to enable a particular device to wake the system, an ACPI platform must also be able to record and report the wake source to OSPM. When a system is woken from certain states (such as the S4 state), it may start out in non-ACPI mode. In this case, the SCI status bit may be cleared when ACPI mode is re-entered. However the platform must still attempt to record the wake source for retrieval by OSPM at a later point.
Note: Although the above description explains how a device can wake the system, note that a device can also be put into a low power state during the S0 system state, and that this device may generate a wake signal in the S0 state as the following example illustrates.
3.4.5   Example: Modem Device Power Management
To illustrate how these power management methods function in ACPI, consider an integrated modem. (This example is greatly simplified for the purposes of this discussion.) The power states of a modem are defined as follows (this is an excerpt from the Modem Device Class Power Management Specification):
D0        Modem controller on
Phone interface on
Speaker on
Can be on hook or off hook
Can be waiting for answer
D1        Modem controller in low-power mode (context retained by device)
Phone interface powered by phone line or in low-power mode
Speaker off
Must be on hook
D2        Same as D3
D3        Modem controller off (context lost)
Phone interface powered by phone line or off
Speaker off
On hook
The power policy for the modem is defined as follows:
D3 � D0            COM port opened
D0, D1 � D3      COM port closed
D0 � D1            Modem put in answer mode
D1 � D0            Application requests dial or the phone rings while the modem is in answer mode
The wake policy for the modem is very simple: When the phone rings and wake is enabled, wake the machine.

Based on that policy, the modem and the COM port to which it is attached can be implemented in hardware as shown in Figure 3-2. This is just an example for illustrating features of ACPI. This example is not intended to describe how OEMs should build hardware.

Figure 3-2   Example Modem and COM Port Hardware
Note: Although not shown above, each discrete part has some isolation logic so that the part is isolated when power is removed from it. Isolation logic controls are implemented as power resources in the ACPI Differentiated Description Block so that devices are isolated as power planes are sequenced off.
3.4.5.1   Obtaining the Modem Capabilities
The OS determines the capabilities of this modem when it enumerates the modem by reading the modem's entry in the Differentiated Definition Block. In this case, the entry for the modem would report:
The device supports D0, D1, and D3:

D0 requires PWR1 and PWR2 as power resources
D1 requires PWR1 as a power resource
(D3 implicitly requires no power resources)
To wake the machine, the modem needs no power resources (implying it can wake the machine from D0, D1, and D3)

Control methods for setting power state and resources
3.4.5.2   Setting the Modem Power State
While the OS is running (G0 state), it switches the modem to different power states according to the power policy defined for modems.
When an application opens the COM port, the OS turns on the modem by putting it in the D0 state. Then if the application puts the modem in answer mode, the OS puts the modem in the D1 state to wait for the call make this state transition, the ACPI first checks to see what power resources are no longer needed. In this case, PWR2 is not needed. Then it checks to make sure no other device in the system requires the use of the PWR2 power resource. If the resource is no longer needed, the OSPM uses the _OFF control method associated with that power resource in the Differentiated Definition Block to turn off the PWR2 power plane. This control method sends the appropriate commands to the core chip set to stop asserting the PWR2_EN line. Then, OSPM runs a control method (_PS1) provided in the modem's entry to put the device in the D1 state. This control method asserts the MDM_D1 signal that tells the modem controller to go into a low-power mode.
OSPM does not always turn off power resources when a given device is put in a lower power state. For example, assume that the PWR1 power plane also powers an active line printer (LPT) port. Suppose the user terminates the modem application, causing the COM port to be closed, and therefore causing the modem to be shut off (state D3). As always, OSPM checks to see which power resources are no longer needed. Because the LPT port is still active, PWR1 is in use. OSPM does not turn off the PWR1 resource continues the state transition process by running the modem's control method to switch the device to the D3 power state. The control method causes the MDM_D3 line to be asserted. The modem controller now turns off all its major functions so that it draws little power, if any, from the PWR1 line. Because the COM port is closed, the same sequence of events will take place to put it in the D3 state. Notice that these registers might not be in the device itself example, the control method could read the register that controls MDM_D3.
3.4.5.3   Obtaining the Modem Power Status
Integrated modems have no batteries; the only power status information for the device is the power state of the modem. To determine the modem's current power state (D0-D3), OSPM runs a control method (_PSC) supplied in the modem's entry in the Differentiated Definition Block. This control method reads from the necessary registers to determine the modem's power state.
3.4.5.4   Waking the Computer
As indicated in the modem capabilities, this modem can wake the machine from any device power state. Before putting the computer in a sleep state, the OS enables wake on any devices that applications have requested to be able to wake the machine. Then, it chooses the lowest sleeping state that can still provide the power resources necessary to allow all enabled wake devices to wake the machine. Next, the OS puts each of those devices in the appropriate power state, and puts all other devices in the D3 state. In this case, the OS puts the modem in the D3 state because it supports wake from that state. Finally, the OS saves a resume vector and puts the machine into a sleep state through an ACPI register.
Waking the computer via modem starts with the modem's phone interface asserting its ring indicate (RI) line when it detects a ring on the phone line. This line is routed to the core chip set to generate a wake event. The chip set then wakes the system and the hardware will eventually passes control back to the OS (the wake mechanism differs depending on the sleeping state). After the OS is running, it puts the device in the D0 state and begins handling interrupts from the modem to process the event.

3.5   Processor Power Management
To further save power in the Working state, the OS puts the CPU into low-power states (C1, C2, and C3) when the OS is idle. In these low-power states, the CPU does not run any instructions, and wakes when an interrupt, such as the OS scheduler's timer interrupt, occurs.
The OS determines how much time is being spent in its idle loop by reading the ACPI Power Management Timer. This timer runs at a known, fixed frequency and allows the OS to precisely determine idle time. Depending on this idle time estimate, the OS will put the CPU into different quality low-power states (which vary in power and latency) when it enters its idle loop.
The CPU states are defined in detail in section 8, "Processor Power and Performance State Configuration and Control."
3.6   Device and Processor Performance States
This section describes the concept of device and processor performance states. Device and processor performance states (Px states) are power consumption and capability states within the active/executing states, C0 for processors and D0 for devices. Performance states allow OSPM to make tradeoffs between performance and energy conservation. Device and processor performance states have the greatest impact when the states invoke different device and processor efficiency levels as opposed to a linear scaling of performance and energy consumption. Since performance state transitions occur in the active/executing device states, care must be taken to ensure that performance state transitions do not adversely impact the system.
Examples of device performance states include:
·      A hard drive that provides levels of maximum throughput that correspond to levels of power consumption.
·      An LCD panel that supports multiple brightness levels that correspond to levels of power consumption.
·      A graphics component that scales performance between 2D and 3D drawing modes that corresponds to levels of power consumption.
·      An audio subsystem that provides multiple levels of maximum volume that correspond to levels of maximum power consumption.
·      A Direct-RDRAM^TM controller that provides multiple levels of memory throughput performance, corresponding to multiple levels of power consumption, by adjusting the maximum bandwidth throttles.
Processor performance states are described in Section 8, "Processor Power and Performance State Configuration and Control."
3.7   Configuration and "Plug and Play"
In addition to power management, ACPI interfaces provide controls and information that enable OSPM to configure the required resources of motherboard devices along with their dynamic insertion and removal. ACPI Definition Blocks, including the Differentiated System Description Table (DSDT) and Secondary System Description Tables (SSDTs), describe motherboard devices in a hierarchical format called the ACPI namespace. The OS enumerates motherboard devices simply by reading through the ACPI Namespace looking for devices with hardware IDs.
Each device enumerated by ACPI includes ACPI-defined objects in the ACPI Namespace that report the hardware resources that the device could occupy, an object that reports the resources that are currently used by the device, and objects for configuring those resources information is used by the Plug and Play OS (OSPM) to configure the devices.

ACPI is used primarily to enumerate and configure motherboard devices that do not have other hardware standards for enumeration and configuration. For example, PCI devices on the motherboard need not be enumerated by ACPI; Plug and Play information for these devices need not be included in the APCI Namespace. However, power management information and insertion/removal control for these devices can still appear in the namespace if the devices' power management and/or insertion/removal is to be controlled by OSPM via ACPI-defined interfaces.
Note: When preparing to boot a computer, the BIOS only needs to configure boot devices. This includes boot devices described in the ACPI system description tables as well as devices that are controlled through other standards.
3.7.1   Device Configuration Example:Configuring the Modem
Returning to the modem device example above, the OS will find the modem and load a driver for it when the OS finds it in the DSDT. This table will have control methods that give the OS the following information:
·      The device can use IRQ 3, I/O 3F8-3FF or IRQ 4, I/O 2E8-2EF
·      The device is currently using IRQ 3, I/O 3F8-3FF
The OS configures the modem's hardware resources using Plug and Play algorithms. It chooses one of the supported configurations that does not conflict with any other devices. Then, OSPM configures the device for those resources by running a control method supplied in the modem's section of the Differentiated Definition Block. This control method will write to any I/O ports or memory addresses necessary to configure the device to the given resources.
3.7.2   NUMA Nodes

Systems employing a Non Uniform Memory Access (NUMA) architecture contain collections of hardware resources including processors, memory, and I/O buses, that comprise what is commonly known as a "NUMA node". Processor accesses to memory or I/O resources within the local NUMA node is generally faster than processor accesses to memory or I/O resources outside of the local NUMA node. ACPI defines interfaces that allow the platform to convey NUMA node topology information to OSPM both statically at boot time and dynamically at run time as resources are added or removed from the system.
3.8 System Events
ACPI includes a general event model used for Plug and Play, Thermal, and Power Management events. There are two registers that make up the event model: an event status register and an event enable register.
When an event occurs, the core logic sets a bit in the status register to indicate the event. If the corresponding bit in the enable register is set, the core logic will assert the SCI to signal the OS. When the OS receives this interrupt, it will run the control methods corresponding to any bits set in the event status register. These control methods use AML commands to tell the OS what event occurred.
For example, assume a machine has all of its Plug and Play, Thermal, and Power Management events connected to the same pin in the core logic. The event status and event enable registers would only have one bit each: the bit corresponding to the event pin.
When the computer is docked, the core logic sets the status bit and signals the SCI. The OS, seeing the status bit set, runs the control method for that bit. The control method checks the hardware and determines the event was a docking event (for example). It then signals to the OS that a docking event has occurred, and can tell the OS specifically where in the device hierarchy the new devices will appear.

Since the event model registers are generalized, they can describe many different platform implementations. The single pin model above is just one example. Another design might have Plug and Play, Thermal, and Power Management events wired to three different pins so there would be three status bits (and three enable bits). Yet another design might have every individual event wired to its own pin and status bit. This design, at the opposite extreme from the single pin design, allows very complex hardware, yet very simple control methods. Countless variations in wiring up events are possible. However, note that care must be taken to ensure that if events share a signal that the event that generated the signal can be determined in the corresponding event handling control method allowing the proper device notification to be sent.
3.9   Battery Management
Battery management policy moves from the APM BIOS to the ACPI-compatible OS. Batteries must comply with the requirements of their associated interfaces, as described either herein or in other applicable standards. The OS may choose to alter the behavior of the battery, for example, by adjusting the Low Battery or Battery Warning trip point. When there are multiple batteries present, the battery subsystem is not required to perform any synthesis of a "composite battery" from the data of the separate batteries. In cases where the battery subsystem does not synthesize a "composite battery" from the separate battery's data, the OS must provide that synthesis.
An ACPI-compatible battery device needs either a Smart Battery subsystem interface or a Control Method Battery interface.
·       Smart Battery is controlled by the OS directly through the embedded controller (EC). For more information about the ACPI Embedded Controller SMBus interface, see section 12.9, "SMBus Host Controller Interface via Embedded Controller." For additional information about the Smart Battery subsystem interface, see section 10.1, "Smart Battery Subsystems."
·       Control Method Battery is completely accessed by AML code control methods, allowing the OEM to choose any type of battery and any kind of communication interface supported by ACPI. For more information about the Control Method Battery Interface, see section 10.2, "Control Method Batteries."
This section describes concepts common to all battery types.
3.9.1   Battery Communications
Both the Smart Battery and Control Method Battery interfaces provide a mechanism for the OS to query information from the platform's battery system. This information may include full charged capacity, present battery capacity, rate of discharge, and other measures of the battery's condition. All battery system types must provide notification to the OS when there is a change such as inserting or removing a battery, or when a battery starts or stops discharging. Smart Batteries and some Control Method Batteries are also able to give notifications based on changes in capacity. Smart batteries provide extra information such as estimated run-time, information about how much power the battery is able to provide, and what the run-time would be at a predetermined rate of consumption.

3.9.2   Battery Capacity
Each battery must report its designed capacity, latest full-charged capacity, and present remaining capacity. Remaining capacity decreases during usage, and it also changes depending on the environment. Therefore, the OS must use latest full-charged capacity to calculate the battery percentage. In addition the battery system must report warning and low battery levels at which the user must be notified and the system transitioned to a sleeping state. See Figure 3-3 for the relation of these five values.
A system may use either rate and capacity [mA/mAh] or power and energy [mW/mWh] for the unit of battery information calculation and reporting. Mixing [mA] and [mW] is not allowed on a system.

Figure 3-3   Reporting Battery Capacity
3.9.3   Battery Gas Gauge
At the most basic level, the OS calculates Remaining Battery Percentage [%] using the following formula:

Control Method Battery also reports the Present Drain Rate [mA or mW] for calculating the remaining battery life. At the most basic level, Remaining Battery life is calculated by following formula:

Smart Batteries also report the present rate of drain, but since they can directly report the estimated run-time, this function should be used instead as it can more accurately account for variations specific to the battery.
3.9.4 Low Battery Levels
A system has an OEM-designed initial capacity for warning, initial capacity for low, and a critical battery level or flag. The values for warning and low represent the amount of energy or battery capacity needed by the system to take certain actions. The critical battery level or flag is used to indicate when the batteries in the system are completely drained. OSPM can determine independent warning and low battery capacity values based on the OEM-designed levels, but cannot set these values lower than the OEM-designed values, as shown in the figure below

Figure 3-4 Low Battery and Warning

Each Control Method Battery in a system reports the OEM-designed initial warning capacity and OEM-designed initial low capacity as well as a flag to report when that battery has reached or is below its critical energy level. Unlike Control Method Batteries, Smart Batteries are not necessarily specific to one particular machine type, so the OEM-designed warning, low, and critical levels are reported separately in a Smart Battery Table described in section 5.2.13.

The table below describes how these values should be set by the OEM and interpreted by the OS.
Table 3-1 Low Battery Levels

Level	Description
Warning	When the total available energy (mWh) or capacity (mAh) in the batteries falls below this level, the OS will notify the user through the UI. This value should allow for a few minutes of run-time before the "Low" level is encountered so the user has time to wrap up any important work, change the battery, or find a power outlet to plug the system in.
Low	This value is an estimation of the amount of energy or battery capacity required by the system to transition to any supported sleeping state. When the OS detects that the total available battery capacity is less than this value, it will transition the system to a user defined system state (S1-S5). In most situations this should be S4 so that system state is not lost if the battery eventually becomes completely empty. The design of the OS should consider that users of a multiple battery system may remove one or more of the batteries in an attempt replace or charge it. This might result in the remaining capacity falling below the "Low" level not leaving sufficient battery capacity for the OS to safely transition the system into the sleeping state. Therefore, if the batteries are discharging simultaneously, the action might need to be initiated at the point when both batteries reach this level.
Critical	The Critical battery state indicates that all available batteries are discharged and do not appear to be able to supply power to run the system any longer. When this occurs, the OS must attempt to perform an emergency shutdown as described below. For a smart battery system, this would typically occur when all batteries reach a capacity of 0, but an OEM may choose to put a larger value in the Smart Battery Table to provide an extra margin of safely. For a Control Method Battery system with multiple batteries, the flag is reported per battery. If any battery in the system is in a critically low state and is still providing power to the system (in other words, the battery is discharging), the system is considered to be in a critical energy state. The _BST control method is required to return the Critical flag on a discharging battery only when all batteries have reached a critical state; the ACPI BIOS is otherwise required to switch to a non-critical battery.

3.9.4.1 Emergency Shutdown
Running until all batteries in a system are critical is not a situation that should be encountered normally, since the system should be put into a sleeping state when the battery becomes low. In the case that this does occur, the OS should take steps to minimize any damage to system integrity emergency shutdown procedure should be designed to minimize bad effects based on the assumption that power may be lost at any time. For example, if a hard disk is spun down, the OS should not try to spin it up to write any data, since spinning up the disk and attempting to write data could potentially corrupt files if the write were not completed. Even if a disk is spun up, the decision to attempt to save even system settings data before shutting down would have to be evaluated since reverting to previous settings might be less harmful than having the potential to corrupt the settings if power was lost halfway through the write operation.
3.9.5 Battery Calibration

The reported capacity of many batteries generally degrade over time, providing less run time for the user. However, it is possible with many battery systems to provide more useable runtime on an old battery if a calibration or conditioning cycle is run occasionally. The user has typically been able to perform a calibration cycle either by going into the BIOS setup menu, or by running a custom driver and calibration application provided by the OEM. The calibration process typically takes several hours, and the laptop must be plugged in during this time. Ideally the application that controls this should make this as good of a user experience as possible, for example allowing the user to schedule the system to wake up and perform the calibration at some time when the system will not be in use. Since the calibration user experience does not need to be different from system to system it makes sense for this service to be provided by the OSPM. .In this way OSPM can provide a common experience for end users and eliminate the need for OEMs to develop custom battery calibration software.
In order for OSPM to perform generic battery calibration, generic interfaces to control the two basic calibration functions are required. These functions are defined in section 10.2.2.5 and 10.2.2.6. First, there is a means to detect when it would be beneficial to calibrate the battery. Second there is a means to perform that calibration cycle. Both of those functions may be implemented by dedicated hardware such as a battery controller chip, by firmware in the embedded controller, by the BIOS, or by OSPM. From here on any function implemented through AML, whether or not the AML code relies on hardware, will be referred to as "AML controlled" since the interface is the same whether the AML passes control to the hardware or not.
Detection of when calibration is necessary can be implemented by hardware or AML code and be reported through the _BMD method. Alternately, the _BMD method may simply report the number of cycles before calibration should be performed and let the OS attempt to count the cycles counter implemented by the hardware or the BIOS will generally be more accurate since the batteries can be used without the OS running, but in some cases, a system designer may opt to simplify the hardware or BIOS implementation.
When calibration is desirable and the user has scheduled the calibration to occur, the calibration cycle can be AML controlled or OSPM controlled. OSPM can only implement a very simple algorithm since it doesn't have knowledge of the specifics of the battery system. It will simply discharge the battery until it quits discharging, then charge it until it quits charging. In the case where the AC adapter cannot be controlled through the _BMC, it will prompt the user to unplug the AC adapter and reattach it after the system powers off. If the calibration cycle is controlled by AML, the OS will initiate the calibration cycle by calling _BMC. That method will either give control to the hardware, or will control the calibration cycle itself the control of the calibration cycle is implemented entirely in AML code, the BIOS may avoid continuously running AML code by having the initial call to _BMC start the cycle, set some state flags, and then exit. Control of later parts of the cycle can be accomplished by putting code that checks these state flags in the battery event handler (_Qxx, _Lxx, or _Exx).
Details of the control methods for this interface are defined in section 10.2.

3.10 Thermal Management
ACPI allows the OS to play a role in the thermal management of the system while maintaining the platform's ability to mandate cooling actions as necessary. In the passive cooling mode, OSPM can make cooling decisions based on application load on the CPU as well as the thermal heuristics of the system. OSPM can also gracefully shutdown the computer in case of high temperature emergencies.
The ACPI thermal design is based around regions called thermal zones. Generally, the entire PC is one large thermal zone, but an OEM can partition the system into several logical thermal zones if necessary. Figure 3-5 is an example mobile PC diagram that depicts a single thermal zone with a central processor as the thermal-coupled device. In this example, the whole notebook is covered as one large thermal zone. This notebook uses one fan for active cooling and the CPU for passive cooling.

Figure 3-5 Thermal Zone
The following sections are an overview of the thermal control and cooling characteristics of a computer. For some thermal implementation examples on an ACPI platform, see section 11.5, "Thermal Zone Interface Requirements."

3.10.1   Active and Passive Cooling Modes
ACPI defines two cooling modes, Active and Passive:
·       Passive cooling. OS reduces the power consumption of devices at the cost of system performance to reduce the temperature of the machine.
·       Active cooling. OS increases the power consumption of the system (for example, by turning on a fan) to reduce the temperature of the machine.
These two cooling modes are inversely related to each other. Active cooling requires increased power to reduce the heat within the system while Passive cooling requires reduced power to decrease the temperature. The effect of this relationship is that Active cooling allows maximum system performance, but it may create undesirable fan noise, while Passive cooling reduces system performance, but is inherently quiet.
3.10.2   Performance vs. Energy Conservation
A robust OSPM implementation provides the means for the end user to convey to OSPM a preference (or a level of preference) for either performance or energy conservation. Allowing the end user to choose this preference is most critical to mobile system users where maximizing system run-time on a battery charge often has higher priority over realizing maximum system performance.
A user's preference for performance corresponds to the Active cooling mode while a user's preference for energy conservation corresponds to the Passive cooling mode. ACPI defines an interface to convey the cooling mode to the platform. Active cooling can be performed with minimal OSPM thermal policy intervention. For example, the platform indicates through thermal zone parameters that crossing a thermal trip point requires a fan to be turned on. Passive cooling requires OSPM thermal policy to manipulate device interfaces that reduce performance to reduce thermal zone temperature.
3.10.3   Acoustics (Noise)
Active cooling mode generally implies that fans will be used to cool the system and fans vary in their audible output. Fan noise can be quite undesirable given the loudness of the fan and the ambient noise environment. In this case, the end user's physical requirement for fan silence may override the preference for either performance or energy conservation.
A user's desire for fan silence corresponds to the Passive cooling mode. Accordingly, a user's desire for fan silence also means a preference for energy conservation.
For more information on thermal management and examples of platform settings for active and passive cooling, see section 11, "Thermal Management."
3.10.4   Multiple Thermal Zones
The basic thermal management model defines one thermal zone, but in order to provide extended thermal control in a complex system, ACPI specifies a multiple thermal zone implementation. Under a multiple thermal zone model, OSPM will independently manage several thermal-coupled devices and a designated thermal zone for each thermal-coupled device, using Active and/or Passive cooling methods available to each thermal zone. Each thermal zone can have more than one Passive and Active cooling device. Furthermore, each zone might have unique or shared cooling resources. In a multiple thermal zone configuration, if one zone reaches a critical state then OSPM must shut down the entire system.

4   ACPI Hardware Specification
ACPI defines standard interface mechanisms that allow an ACPI-compatible OS to control and communicate with an ACPI-compatible hardware platform. This section describes the hardware aspects of ACPI.
ACPI defines "hardware" as a programming model and its behavior. ACPI strives to keep much of the existing legacy programming model the same; however, to meet certain feature goals, designated features conform to a specific addressing and programming scheme. Hardware that falls within this category is referred to as "fixed."
Although ACPI strives to minimize these changes, hardware engineers should read this section carefully to understand the changes needed to convert a legacy-only hardware model to an ACPI/Legacy hardware model or an ACPI-only hardware model.
ACPI classifies hardware into two categories: Fixed or Generic. Hardware that falls within the fixed category meets the programming and behavior specifications of ACPI. Hardware that falls within the generic category has a wide degree of flexibility in its implementation.
4.1   Fixed Hardware Programming Model
Because of the changes needed for migrating legacy hardware to the fixed category, ACPI limits the features specified by fixed hardware. Fixed hardware features are defined by the following criteria:
·      Performance sensitive features
·      Features that drivers require during wake
·      Features that enable catastrophic OS software failure recovery
ACPI defines register-based interfaces to fixed hardware. CPU clock control and the power management timer are defined as fixed hardware to reduce the performance impact of accessing this hardware, which will result in more quickly reducing a thermal condition or extending battery life. If this logic were allowed to reside in PCI configuration space, for example, several layers of drivers would be called to access this address space. This takes a long time and will either adversely affect the power of the system (when trying to enter a low-power state) or the accuracy of the event (when trying to get a time stamp value).
Access to fixed hardware by OSPM allows OSPM to control the wake process without having to load the entire OS. For example, if PCI configuration space access is needed, the bus enumerator is loaded with all drivers used by the enumerator. Defining these interfaces in fixed hardware at addresses with which OSPM can communicate without any other driver's assistance, allows OSPM to gather information prior to making a decision as to whether it continues loading the entire OS or puts it back to sleep.
If elements of the OS fail, it may be possible for OSPM to access address spaces that need no driver support. In such a situation, OSPM will attempt to honor fixed power button requests to transition the system to the G2 state. In the case where OSPM event handler is no longer able to respond to power button events, the power button override feature provides a back-up mechanism to unconditionally transition the system to the soft-off state.

4.1.1 Functional Fixed Hardware
ACPI defines the fixed hardware low-level interfaces as a means to convey to the system OEM the minimum interfaces necessary to achieve a level of capability and quality for motherboard configuration and system power management. Additionally, the definition of these interfaces, as well as others defined in this specification, conveys to OS Vendors (OSVs) developing ACPI-compatible operating systems, the necessary interfaces that operating systems must manipulate to provide robust support for system configuration and power management.
While the definition of low-level hardware interfaces defined by ACPI 1.0 afforded OSPM implementations a certain level of stability, controls for existing and emerging diverse CPU architectures cannot be accommodated by this model as they can require a sequence of hardware manipulations intermixed with native CPU instructions to provide the ACPI-defined interface function. In this case, an ACPI-defined fixed hardware interface can be functionally implemented by the CPU manufacturer through an equivalent combination of both hardware and software and is defined by ACPI as Functional Fixed Hardware.
In IA-32-based systems, functional fixed hardware can be accommodated in an OS independent manner by using System Management Mode (SMM) based system firmware. Unfortunately, the nature of SMM-based code makes this type of OS independent implementation difficult if not impossible to debug such, this implementation approach is not recommended. In some cases, Functional Fixed Hardware implementations may require coordination with other OS components. As such, an OS independent implementation may not be viable.
OS-specific implementations of functional fixed hardware can be implemented using technical information supplied by the CPU manufacturer. The downside of this approach is that functional fixed hardware support must be developed for each OS. In some cases, the CPU manufacturer may provide a software component providing this support. In other cases support for the functional fixed hardware may be developed directly by the OS vendor.
The hardware register definition was expanded, in ACPI 2.0, to allow registers to exist in address spaces other than the System I/O address space. This is accomplished through the specification of an address space ID in the register definition (see section 5.2.3.1, "Generic Address Structure," for more information). When specifically directed by the CPU manufacturer, the system firmware may define an interface as functional fixed hardware by supplying a special address space identifier, FfixedHW (0x7F), in the address space ID field for register definitions. It is emphasized that functional fixed hardware definitions may be declared in the ACPI system firmware only as indicated by the CPU Manufacturer for specific interfaces as the use of functional fixed hardware requires specific coordination with the OS vendor.
Only certain ACPI-defined interfaces may be implemented using functional fixed hardware and only when the interfaces are common across machine designs for example, systems sharing a common CPU architecture that does not support fixed hardware implementation of an ACPI-defined interface. OEMs are cautioned not to anticipate that functional fixed hardware support will be provided by OSPM differently on a system-by-system basis. The use of functional fixed hardware carries with it a reliance on OS specific software that must be considered. OEMs should consult OS vendors to ensure that specific functional fixed hardware interfaces are supported by specific operating systems.

4.2   Generic Hardware Programming Model
Although the fixed hardware programming model requires hardware registers to be defined at specific address locations, the generic hardware programming model allows hardware registers to reside in most address spaces and provides system OEMs with a wide degree of flexibility in the implementation of specific functions in hardware. OSPM directly accesses the fixed hardware registers, but relies on OEM-provided ACPI Machine Language (AML) code to access generic hardware registers.
AML code allows the OEM to provide the means for OSPM to control a generic hardware feature's control and event logic.
The section entitled "ACPI Source Language Reference" describes the ACPI Source Language (ASL)—a programming language that OEMs use to create AML. The ASL language provides many of the operators found in common object-oriented programming languages, but it has been optimized to enable the description of platform power management and configuration hardware. An ASL compiler converts ASL source code to AML, which is a very compact machine language that the ACPI AML code interpreter executes.
AML does two things:
·      Abstracts the hardware from OSPM
·      Buffers OEM code from the different OS implementations
One goal of ACPI is to allow the OEM "value added" hardware to remain basically unchanged in an ACPI configuration. One attribute of value-added hardware is that it is all implemented differently. To enable OSPM to execute properly on different types of value added hardware, ACPI defines higher level "control methods" that it calls to perform an action. The OEM provides AML code, which is associated with control methods, to be executed by OSPM. By providing AML code, generic hardware can take on almost any form.
Another important goal of ACPI is to provide OS independence. To do this, the OEM AML code has to execute the same under any ACPI-compatible OS. ACPI allows for this by making the AML code interpreter part of OSPM. This allows OSPM to take care of synchronizing and blocking issues specific to each particular OS.
The generic feature model is represented in the following block diagram. In this model the generic feature is described to OSPM through AML code. This description takes the form of an object that sits in the ACPI Namespace associated with the hardware to which it is adding value.

Figure 4-1   Generic Hardware Feature Model

As an example of a generic hardware control feature, a platform might be designed such that the IDE HDD's D3 state has value-added hardware to remove power from the drive. The IDE drive would then have a reference to the AML PowerResource object (which controls the value added power plane) in its namespace, and associated with that object would be control methods that OSPM invokes to control the D3 state of the drive:
·       _PS0 >. A control method to sequence the IDE drive to the D0 state.
·       _PS3 >. A control method to sequence the IDE drive to the D3 state.
·       _PSC >. A control method that returns the status of the IDE drive (on or off).
The control methods under this object provide an abstraction layer between OSPM and the hardware. OSPM understands how to control power planes (turn them on or off or to get their status) through its defined PowerResource object, while the hardware has platform-specific AML code (contained in the appropriate control methods) to perform the desired function. In this example, the platform would describe its hardware to the ACPI OS by writing and placing the AML code to turn the hardware off within the _PS3 control method. This enables the following sequence:
When OSPM decides to place the IDE drive in the D3 state, it calls the IDE driver and tells it to place the drive into the D3 state (at which point the driver saves the device's context).
When the IDE driver returns control, OSPM places the drive in the D3 state.
OSPM finds the object associated with the HDD and then finds within that object any AML code associated with the D3 state.
OSPM executes the appropriate _PS3 control method to control the value-added "generic" hardware to place the HDD into an even lower power state.
As an example of a generic event feature, a platform might have a docking capability. In this case, it will want to generate an event. Notice that all ACPI events generate an SCI, which can be mapped to any shareable system interrupt. In the case of docking, the event is generated when a docking has been detected or when the user requests to undock the system. This enables the following sequence:
OSPM responds to the SCI and calls the AML code event handler associated with that generic event. The ACPI table associates the hardware event with the AML code event handler.
The AML-code event handler collects the appropriate information and then executes an AML Notify command to indicate to OSPM that a particular bus needs re-enumeration.
The following sections describe the fixed and generic hardware feature set of ACPI. These sections enable a reader to understand the following:
·       Which hardware registers are required or optional when an ACPI feature, concept or interface is required by a design guide for a platform class
·       How to design fixed hardware features
·       How to design generic hardware features
·       The ACPI Event Model

4.3 Diagram Legends
The hardware section uses simplified logic diagrams to represent how certain aspects of the hardware are implemented. The following symbols are used in the logic diagrams to represent programming bits.

Write-only control bit

Enable, control or status bit

Sticky status bit

            Query value
The half round symbol with an inverted "V" represents a write-only control bit. This bit has the behavior that it generates its control function when it is set. Reads to write-only bits are treated as ignore by software (the bit position is masked off and ignored).
The round symbol with an "X" represents a programming bit. As an enable or control bit, software setting or clearing this bit will result in the bit being read as set or clear (unless otherwise noted). As a status bit it directly represents the value of the signal.
The square symbol represents a sticky status bit. A sticky status bit is set by the level (not edge) of a hardware signal (active high or active low). The bit is only cleared by software writing a "1" to its bit position.
The rectangular symbol represents a query value from the embedded controller. This is the value the embedded controller returns to the system software upon a query command in response to an SCI event. The query value is associated with the event control method that is scheduled to execute upon an embedded controller event.
4.4   Register Bit Notation
Throughout this section there are logic diagrams that reference bits within registers. These diagrams use a notation that easily references the register name and bit position. The notation is as follows:
            Registername.Bit

Registername contains the name of the register as it appears in this specification
Bit contains a zero-based decimal value of the bit position.
For example, the SLP_EN bit resides in the PM1x_CNT register bit 13 and would be represented in diagram notation as:
            SLP_EN
            PM1x_CNT.13
4.5   The ACPI Hardware Model
The ACPI hardware model is defined to allow OSPM to sequence the platform between the various global system states (G0-G3) as illustrated in the following figure by manipulating the defined interfaces. When first powered on, the platform finds itself in the global system state G3 or "Mechanical Off." This state is defined as one where power consumption is very close to zero—the power plug has been removed;however, the real-time clock device still runs off a battery. The G3 state is entered by any power failure, defined as accidental or user-initiated power loss.
The G3 state transitions into either the G0 working state or the Legacy state depending on what the platform supports. If the platform is an ACPI-only platform, then it allows a direct boot into the G0 working state by always returning the status bit SCI_EN set (1) (for more information, see section 4.7.2.5, "Legacy/ACPI Select and the SCI Interrupt"). If the platform supports both legacy and ACPI operations (which is necessary for supporting a non-ACPI OS), then it would always boot into the Legacy state (illustrated by returning the SCI_EN clear (0)). In either case, a transition out of the G3 state requires a total boot of OSPM.
The Legacy system state is the global state where a non-ACPI OS executes. This state can be entered from either the G3 "Mechanical Off," the G2 "Soft Off," or the G0 "Working" states only if the hardware supports both Legacy and ACPI modes. In the Legacy state, the ACPI event model is disabled (no SCIs are generated) and the hardware uses legacy power management and configuration mechanisms. While in the Legacy state, an ACPI-compliant OS can request a transition into the G0 working state by performing an ACPI mode request. OSPM performs this transition by writing the ACPI_ENABLE value to the SMI_CMD, which generates an event to the hardware to transition the platform into ACPI mode. When hardware has finished the transition, it sets the SCI_EN bit and returns control back to OSPM. While in the G0 "working state," OSPM can request a transition to Legacy mode by writing the ACPI_DISABLE value to the SMI_CMD register, which results in the hardware going into legacy mode and resetting the SCI_EN bit LOW (for more information, see section 4.7.2.5, "Legacy/ACPI Select and the SCI Interrupt").
The G0 "Working" state is the normal operating environment of an ACPI machine. In this state different devices are dynamically transitioning between their respective power states (D0, D1, D2 or D3) and processors are dynamically transitioning between their respective power states (C0, C1, C2 or C3). In this state, OSPM can make a policy decision to place the platform into the system G1 "sleeping" state. The platform can only enter a single sleeping state at a time (referred to as the global G1 state); however, the hardware can provide up to four system sleeping states that have different power and exit latencies represented by the S1, S2, S3, or S4 states. When OSPM decides to enter a sleeping state it picks the most appropriate sleeping state supported by the hardware (OS policy examines what devices have enabled wake events and what sleeping states these support). OSPM initiates the sleeping transition by enabling the appropriate wake events and then programming the SLP_TYPx field with the desired sleeping state and then setting the SLP_ENx bit. The system will then enter a sleeping state; when one of the enabled wake events occurs, it will transition the system back to the working state (for more information, see section 15, "Waking and Sleeping").
Another global state transition option while in the G0 "working" state is to enter the G2 "soft off" or the G3 "mechanical off" state. These transitions represent a controlled transition that allows OSPM to bring the system down in an orderly fashion (unloading applications, closing files, and so on). The policy for these types of transitions can be associated with the ACPI power button, which when pressed generates an event to the power button driver. When OSPM is finished preparing the operating environment for a power loss, it will either generate a pop-up message to indicate to the user to remove power, in order to enter the G3 "Mechanical Off" state, or it will initiate a G2 "soft-off" transition by writing the value of the S5 "soft off" system state to the SLP_TYPx register and setting the SLP_EN bit.
The G1 sleeping state is represented by four possible sleeping states that the hardware can support. Each sleeping state has different power and wake latency characteristics. The sleeping state differs from the working state in that the user's operating environment is frozen in a low-power state until awakened by an enabled wake event. No work is performed in this state, that is, the processors are not executing instructions. Each system sleeping state has requirements about who is responsible for system context and wake sequences (for more information, see section 15, Waking and Sleeping").
The G2 "soft off" state is an OS initiated system shutdown. This state is initiated similar to the sleeping state transition (SLP_TYPx is set to the S5 value and setting the SLP_EN bit initiates the sequence). Exiting the G2 soft-off state requires rebooting the system. In this case, an ACPI-only machine will re-enter the G0 state directly (hardware returns the SCI_EN bit set), while an ACPI/Legacy machine transitions to the Legacy state (SCI_EN bit is clear).

Figure 4-2   Global States and Their Transitions
The ACPI architecture defines mechanisms for hardware to generate events and control logic to implement this behavior model. Events are used to notify OSPM that some action is needed, and control logic is used by OSPM to cause some state transition. ACPI-defined events are "hardware" or "interrupt" events. A hardware event is one that causes the hardware to unconditionally perform some operation. For example, any wake event will sequence the system from a sleeping state (S1, S2, S3, and S4 in the global G1 state) to the G0 working state (see Figure 15-1).
An interrupt event causes the execution of an event handler (AML code or an ACPI-aware driver), which allows the software to make a policy decision based on the event. For ACPI fixed-feature events, OSPM or an ACPI-aware driver acts as the event handler. For generic logic events OSPM will schedule the execution of an OEM-supplied AML control method associated with the event.
For legacy systems, an event normally generates an OS-transparent interrupt, such as a System Management Interrupt, or SMI ACPI systems the interrupt events need to generate an OS-visible interrupt that is shareable; edge-style interrupts will not work. Hardware platforms that want to support both legacy operating systems and ACPI systems support a way of re-mapping the interrupt events between SMIs and SCIs when switching between ACPI and legacy models. This is illustrated in the following block diagram.

Figure 4-3   Example Event Structure for a Legacy/ACPI Compatible Event Model
This example logic illustrates the event model for a sample platform that supports both legacy and ACPI event models. This example platform supports a number of external events that are power-related (power button, LID open/close, thermal, ring indicate) or Plug and Play-related (dock, status change). The logic represents the three different types of events:
·       OS Transparent Events. These events represent OEM-specific functions that have no OS support and use software that can be operated in an OS-transparent fashion (that is, SMIs).
·       Interrupt Events. These events represent features supported by ACPI-compatible operating systems, but are not supported by legacy operating systems. When a legacy OS is loaded, these events are mapped to the transparent interrupt (SMI# in this example), and when in ACPI mode they are mapped to an OS-visible shareable interrupt (SCI#). This logic is represented by routing the event logic through the decoder that routes the events to the SMI# arbiter when the SCI_EN bit is cleared, or to the SCI# arbiter when the SCI_EN bit is set.
·       Hardware events. These events are used to trigger the hardware to initiate some hardware sequence such as waking, resetting, or putting the machine to sleep unconditionally.
In this example, the legacy power management event logic is used to determine device/system activity or idleness based on device idle timers, device traps, and the global standby timer. Legacy power management models use the idle timers to determine when a device should be placed in a low-power state because it is idle—that is, the device has not been accessed for the programmed amount of time. The device traps are used to indicate when a device in a low-power state is being accessed by OSPM global standby timer is used to determine when the system should be allowed to go into a sleeping state because it is idle—that is, the user interface has not been used for the programmed amount of time.
These legacy idle timers, trap monitors, and global standby timer are not used by OSPM in the ACPI mode. This work is handled by different software structures in an ACPI-compatible OS. For example, the driver model of an ACPI-compatible OS is responsible for placing its device into a low-power state (D1, D2, or D3) and transitioning it back to the On state (D0) when needed. And OSPM is responsible for determining when the system is idle by profiling the system (using the PM Timer) and other knowledge it gains through its operating structure environment (which will vary from OS to OS). When the system is placed into the ACPI mode, these events no longer generate SMIs, as OSPM handles this function. These events are disabled through some OEM-proprietary method.
On the other hand, many of the hardware events are shared between the ACPI and legacy models (docking, the power button, and so on) and this type of interrupt event changes to an SCI event when enabled for ACPI ACPI OS will generate a request to the platform's hardware (BIOS) to enter into the ACPI mode. The BIOS sets the SCI_EN bit to indicate that the system has successfully entered into the ACPI mode, so this is a convenient mechanism to map the desired interrupt (SMI or SCI) for these events (as shown in Figure 4-3).
The ACPI architecture specifies some dedicated hardware not found in the legacy hardware model: the power management timer (PM Timer). This is a free running timer that the ACPI OS uses to profile system activity frequency of this timer is explicitly defined in this specification and must be implemented as described.
Although the ACPI architecture reuses most legacy hardware as is, it does place restrictions on where and how the programming model is generated. If used, all fixed hardware features are implemented as described in this specification so that OSPM can directly access the fixed hardware feature registers.
Generic hardware features are manipulated by ACPI control methods residing in the ACPI Namespace. These interfaces can be very flexible;however, their use is limited by the defined ACPI control methods (for more information, see section 9, "ACPI Devices and Device Specific Objects"). Generic hardware usually controls power planes, buffer isolation, and device reset resources. Additionally, "child" interrupt status bits can be accessed via generic hardware interfaces; however, they have a "parent" interrupt status bit in the GP_STS register. ACPI defines seven address spaces that may be accessed by generic hardware implementations. These include:
·       System I/O space
·       System memory space
·       PCI configuration space
·       Embedded controller space
·       System Management Bus (SMBus) space
·       CMOS

·       PCI BAR Target
Generic hardware power management features can be implemented accessing spare I/O ports residing in any of these address spaces. The ACPI specification defines an optional embedded controller and SMBus interfaces needed to communicate with these associated address spaces.
4.5.1   Hardware Reserved Bits
ACPI hardware registers are designed such that reserved bits always return zero, and data writes to them have no side affects. OSPM implementations must write zeros to reserved bits in enable and status registers and preserve bits in control registers, and they will treat these bits as ignored.
4.5.2   Hardware Ignored Bits
ACPI hardware registers are designed such that ignored bits are undefined and are ignored by software. Hardware-ignored bits can return zero or one. When software reads a register with ignored bits, it masks off ignored bits prior to operating on the result. When software writes to a register with ignored bit fields, it preserves the ignored bit fields.
4.5.3   Hardware Write-Only Bits
ACPI hardware defines a number of write-only control bits. These bits are activated by software writing a 1 to their bit position. Reads to write-only bit positions generate undefined results. Upon reads to registers with write-only bits, software masks out all write-only bits.
4.5.4   Cross Device Dependencies
Cross Device Dependency is a condition in which an operation to a device interferes with the operation of other unrelated devices, or allows other unrelated devices to interfere with its behavior. This condition is not supportable and can cause platform failures. ACPI provides no support for cross device dependencies and suggests that devices be designed to not exhibit this behavior. The following two examples describe cross device dependencies:
4.5.4.1   Example 1: Related Device Interference
This example illustrates a cross device dependency where a device interferes with the proper operation of other unrelated devices. Device A has a dependency that when it is being configured it blocks all accesses that would normally be targeted for Device B. Thus, the device driver for Device B cannot access Device B while Device A is being configured; therefore, it would need to synchronize access with the driver for Device A. High performance, multithreaded operating systems cannot perform this kind of synchronization without seriously impacting performance.
To further illustrate the point, assume that Device A is a serial port and Device B is a hard drive controller. If these devices demonstrate this behavior, then when a software driver configures the serial port, accesses to the hard drive need to block. This can only be done if the hard disk driver synchronizes access to the disk controller with the serial driver. Without this synchronization, hard drive data will be lost when the serial port is being configured.
4.5.4.2   Example 2: Unrelated Device Interference
This example illustrates a cross-device dependency where a device demonstrates a behavior that allows other unrelated devices to interfere with its proper operation. Device A exhibits a programming behavior that requires atomic back-to-back write accesses to successfully write to its registers; if any other platform access is able to break between the back-to-back accesses, then the write to Device A is unsuccessful. If the Device A driver is unable to generate atomic back-to-back accesses to its device, then it relies on software to synchronize accesses to its device with every other driver in the system; then a device cross dependency is created and the platform is prone to Device A failure.
4.6   ACPI Hardware Features
This section describes the different hardware features defined by the ACPI interface. These features are categorized as the following:
·       Fixed Hardware Features
·       Generic Hardware Features
Fixed hardware features reside in a number of the ACPI-defined address spaces at the locations described by the ACPI programming model. Generic hardware features reside in one of four address spaces (system I/O, system memory, PCI configuration, embedded controller, or serial device I/O space) and are described by the ACPI Namespace through the declaration of AML control methods.
Fixed hardware features have exact definitions for their implementation. Although many fixed hardware features are optional, if implemented they must be implemented as described since OSPM manipulates the registers of fixed hardware devices and expects the defined behavior. Functional fixed hardware provides functional equivalents of the fixed hardware feature interfaces as described in section 4.1.1, "Functional Fixed Hardware."
Generic hardware feature implementation is flexible. This logic is controlled by OEM-supplied AML code (for more information, see section 5, "ACPI Software Programming Model"), which can be written to support a wide variety of hardware. Also, ACPI provides specialized control methods that provide capabilities for specialized devices. For example, the Notify command can be used to notify OSPM from a generic hardware event handler (control method) that a docking or thermal event has taken place. A good understanding of this section and section 5 of this specification will give designers a good understanding of how to design hardware to take full advantage of an ACPI-compatible OS.
Notice that the generic features are listed for illustration only, the ACPI specification can support many types of hardware not listed.
Table 4-1   Feature/Programming Model Summary

Feature Name	Description	Programming Model
Power Management Timer	24-bit or 32-bit free running timer.	Fixed Hardware Feature Control Logic
Power Button	User pushes button to switch the system between the working and sleeping states.	Fixed Hardware Event and Control Logic or Generic Hardware Event and Logic
Sleep Button	User pushes button to switch the system between the working and sleeping state.	Fixed Hardware Event and Control Logic or Generic Hardware Event and Logic
Power Button Override	User sequence (press the power button for 4 seconds) to turn off a hung system.
Real Time Clock Alarm	Programmed time to wake the system.	Optional Fixed Hardware Event[2]
Sleep/Wake Control Logic	Logic used to transition the system between the sleeping and working states.	Fixed Hardware Control and Event Logic
Embedded Controller Interface	ACPI Embedded Controller protocol and interface, as described in section 12, "ACPI Embedded Controller Interface Specification."	Generic Hardware Event Logic, must reside in the general-purpose register block
Legacy/ACPI Select	Status bit that indicates the system is using the legacy or ACPI power management model (SCI_EN).	Fixed Hardware Control Logic
Lid switch	Button used to indicate whether the system's lid is open or closed (mobile systems only).	Generic Hardware Event Feature
C1 Power State	Processor instruction to place the processor into a low-power state.	Processor ISA
C2 Power Control	Logic to place the processor into a C2 power state.	Fixed Hardware Control Logic
C3 Power Control	Logic to place the processor into a C3 power state.	Fixed Hardware Control Logic
Thermal Control	Logic to generate thermal events at specified trip points.	Generic Hardware Event and Control Logic (See description of thermal logic in section 3.10, "Thermal Management.")
Device Power Management	Control logic for switching between different device power states.	Generic Hardware control logic
AC Adapter	Logic to detect the insertion and removal of the AC adapter.	Generic Hardware event logic
Docking/device insertion and removal	Logic to detect device insertion and removal events.	Generic Hardware event logic

4.7   ACPI Register Model
ACPI hardware resides in one of six address spaces:
·       System I/O
·       System memory
·       PCI configuration
·       SMBus
·       Embedded controller
·       Functional Fixed Hardware
Different implementations will result in different address spaces being used for different functions. The ACPI specification consists of fixed hardware registers and generic hardware registers. Fixed hardware registers are required to implement ACPI-defined interfaces. The generic hardware registers are needed for any events generated by value-added hardware.
ACPI defines register blocks. An ACPI-compatible system provides an ACPI table (the FADT, built in memory at boot-up) that contains a list of pointers to the different fixed hardware register blocks used by OSPM. The bits within these registers have attributes defined for the given register block. The types of registers that ACPI defines are:
·       Status/Enable Registers (for events)
·       Control Registers
If a register block is of the status/enable type, then it will contain a register with status bits, and a corresponding register with enable bits. The status and enable bits have an exact implementation definition that needs to be followed (unless otherwise noted), which is illustrated by the following diagram:

Figure 4-4 Block Diagram of a Status/Enable Cell
Notice that the status bit, which hardware sets by the Event Input being set in this example, can only be cleared by software writing a 1 to its bit position. Also, the enable bit has no effect on the setting or resetting of the status bit; it only determines if the SET status bit will generate an "Event Output," which generates an SCI when set if its enable bit is set.
ACPI also defines register groupings. A register grouping consists of two register blocks, with two pointers to two different blocks of registers, where each bit location within a register grouping is fixed and cannot be changed. The bits within a register grouping, which have fixed bit positions, can be split between the two register blocks. This allows the bits within a register grouping to reside in either or both register blocks, facilitating the ability to map bits within several different chips to the same register thus providing the programming model with a single register grouping bit structure.
OSPM treats a register grouping as a single register; but located in multiple places. To read a register grouping, OSPM will read the "A" register block, followed by the "B" register block, and then will logically "OR" the two results together (the SLP_TYP field is an exception to this rule). Reserved bits, or unused bits within a register block always return zero for reads and have no side effects for writes (which is a requirement).
The SLP_TYPx field can be different for each register grouping. The respective sleeping object \_Sx contains a SLP_TYPa and a SLP_TYPb field. That is, the object returns a package with two integer values of 0-7 in it. OSPM will always write the SLP_TYPa value to the "A" register block followed by the SLP_TYPb value within the field to the "B" register block. All other bit locations will be written with the same value. Also, OSPM does not read the SLP_TYPx value but throws it away.

Figure 4-5   Example Fixed Hardware Feature Register Grouping
As an example, the above diagram represents a register grouping consisting of register block A and register block b. Bits "a" and "d" are implemented in register block B and register block A returns a zero for these bit positions. Bits "b", "c" and "e" are implemented in register block A and register block B returns a zero for these bit positions. All reserved or ignored bits return their defined ACPI values.
When accessing this register grouping, OSPM must read register block a, followed by reading register block b. OSPM then does a logical OR of the two registers and then operates on the results.
When writing to this register grouping, OSPM will write the desired value to register group A followed by writing the same value to register group B.
ACPI defines the following fixed hardware register blocks. Each register block gets a separate pointer from the FADT. These addresses are set by the OEM as static resources, so they are never changed—OSPM cannot re-map ACPI resources. The following register blocks are defined:

Figure 4-6   Register Blocks versus Register Groupings
The PM1 EVT grouping consists of the PM1a_EVT and PM1b_EVT register blocks, which contain the fixed hardware feature event bits. Each event register block (if implemented) contains two registers: a status register and an enable register. Each register grouping has a defined bit position that cannot be changed; however, the bit can be implemented in either register block (A or B). The A and B register blocks for the events allow chipsets to vary the partitioning of events into two or more chips. For read operations, OSPM will generate a read to the associated A and B registers, OR the two values together, and then operate on this result. For write operations, OSPM will write the value to the associated register in both register blocks. Therefore, there are two rules to follow when implementing event registers:
·       Reserved or unimplemented bits always return zero (control or enable).
·       Writes to reserved or unimplemented bits have no affect.
The PM1 CNT grouping contains the fixed hardware feature control bits and consists of the PM1a_CNT_BLK and PM1b_CNT_BLK register blocks. Each register block is associated with a single control register. Each register grouping has a defined bit position that cannot be changed; however, the bit can be implemented in either register block (A or B). There are two rules to follow when implementing CNT registers:
·       Reserved or unimplemented bits always return zero (control or enable).
·       Writes to reserved or unimplemented bits have no affect.
The PM2_CNT_BLK register block currently contains a single bit for the arbiter disable function. The general-purpose event register contains the event programming model for generic features. All generic events, just as fixed events, generate SCIs. Generic event status bits can reside anywhere; however, the top-level generic event resides in one of the general-purpose register blocks. Any generic feature event status not in the general-purpose register space is considered a child or sibling status bit, whose parent status bit is in the general-purpose event register space. Notice that it is possible to have N levels of general-purpose events prior to hitting the GPE event status.
General-purpose event registers are described by two register blocks: The GPE0_BLK or the GPE1_BLK. Each register block is pointed to separately from within the FADT. Each register block is further broken into two registers: GPEx_STS and GPEx_EN. The status and enable registers in the general-purpose event registers follow the event model for the fixed hardware event registers.
4.7.1   ACPI Register Summary
The following tables summarize the ACPI registers:
Table 4-2   PM1 Event Registers

Register	Size (Bytes)	Address (relative to register block)
PM1a_STS	PM1_EVT_LEN/2	<PM1a_EVT_BLK >
PM1a_EN	PM1_EVT_LEN/2	<PM1a_EVT_BLK >+PM1_EVT_LEN/2
PM1b_STS	PM1_EVT_LEN/2	<PM1b_EVT_BLK >
PM1b_EN	PM1_EVT_LEN/2	<PM1b_EVT_BLK >+PM1_EVT_LEN/2

Table 4-3 PM1 Control Registers

Register	Size (Bytes)	Address (relative to register block)
PM1_CNTa	PM1_CNT_LEN	<PM1a_CNT_BLK >
PM1_CNTb	PM1_CNT_LEN	<PM1b_CNT_BLK >

Table 4-4 PM2 Control Register

Register	Size (Bytes)	Address (relative to register block)
PM2_CNT	PM2_CNT_LEN	<PM2_CNT_BLK >

Table 4-5 PM Timer Register

Register	Size (Bytes)	Address (relative to register block)
PM_TMR	PM_TMR_LEN	<PM_TMR_BLK >

Table 4-6 Processor Control Registers

Register	Size (Bytes)	Address (relative to register block)
P_CNT	4	Either <P_BLK> or specified by the PTC object (See section 8.3.1, "PTC [Processor Throttling Control].")
P_LVL2	1	<P_BLK>+4h
P_LVL3	1	<P_BLK>+5h

Table 4-7 General-Purpose Event Registers

Register	Size (Bytes)	Address (relative to register block)
GPE0_STS	GPE0_LEN/2	<GPE0_BLK>
GPE0_EN	GPE0_LEN/2	<GPE0_BLK>+GPE0_LEN/2
GPE1_STS	GPE1_LEN/2	<GPE1_BLK>
GPE1_EN	GPE1_LEN/2	<GPE1_BLK>+GPE1_LEN/2

4.7.1.1   PM1 Event Registers
The PM1 event register grouping contains two register blocks: the PM1a_EVT_BLK is a required register block when the following ACPI interface categories are required by a class specific platform design guide:
·      Power management timer control/status
·      Processor power state control/status
·      Global Lock related interfaces
·      Power or Sleep button (fixed register interfaces)
·      System power state controls (sleeping/wake control)
The PM1b_EVT_BLK is an optional register block. Each register block has a unique 32-bit pointer in the Fixed ACPI Table (FADT) to allow the PM1 event bits to be partitioned between two chips. If the PM1b_EVT_BLK is not supported, its pointer contains a value of zero in the FADT.
Each register block in the PM1 event grouping contains two registers that are required to be the same size: the PM1x_STS and PM1x_EN (where x can be "a" or "b"). The length of the registers is variable and is described by the PM1_EVT_LEN field in the FADT, which indicates the total length of the register block in bytes. Hence if a length of "4" is given, this indicates that each register contains two bytes of I/O space. The PM1 event register block has a minimum size of 4 bytes.
4.7.1.2   PM1 Control Registers
The PM1 control register grouping contains two register blocks: the PM1a_CNT_BLK is a required register block when the following ACPI interface categories are required by a class specific platform design guide:
·      SCI/SMI routing control/status for power management and general-purpose events
·      Processor power state control/status
·      Global Lock related interfaces
·      System power state controls (sleeping/wake control)
The PM1b_CNT_BLK is an optional register block. Each register block has a unique 32-bit pointer in the Fixed ACPI Table (FADT) to allow the PM1 event bits to be partitioned between two chips. If the PM1b_CNT_BLK is not supported, its pointer contains a value of zero in the FADT.
Each register block in the PM1 control grouping contains a single register: the PM1x_CNT. The length of the register is variable and is described by the PM1_CNT_LEN field in the FADT, which indicates the total length of the register block in bytes. The PM1 control register block must have a minimum size of 2 bytes.
4.7.1.3   PM2 Control Register
The PM2 control register is contained in the PM2_CNT_BLK register block. The FADT contains a length variable for this register block (PM2_CNT_LEN) that is equal to the size in bytes of the PM2_CNT register (the only register in this register block). This register block is optional, if not supported its block pointer and length contain a value of zero.
4.7.1.4   PM Timer Register
The PM timer register is contained in the PM_TMR_BLK register block, which is a required register block when the power management timer control/status ACPI interface category is required by a class specific platform design guide.
This register block contains the register that returns the running value of the power management timer. The FADT also contains a length variable for this register block (PM_TMR_LEN) that is equal to the size in bytes of the PM_TMR register (the only register in this register block).
4.7.1.5   Processor Control Block (P_BLK)
There is an optional processor control register block for each processor in the system. As this is a homogeneous feature, all processors must have the same level of support. The ACPI OS will revert to the lowest common denominator of processor control block support. The processor control block contains the processor control register (P_CNT-a 32-bit performance control configuration register), and the P_LVL2 and P_LVL3 CPU sleep state control registers. The 32-bit P_CNT register controls the behavior of the processor clock logic for that processor, the P_LVL2 register is used to place the CPU into the C2 state, and the P_LVL3 register is used to place the processor into the C3 state.
4.7.1.6   General-Purpose Event Registers
The general-purpose event registers contain the root level events for all generic features. To facilitate the flexibility of partitioning the root events, ACPI provides for two different general-purpose event blocks:GPE0_BLK and GPE1_BLK. These are separate register blocks and are not a register grouping, because there is no need to maintain an orthogonal bit arrangement. Also, each register block contains its own length variable in the FADT, where GPE0_LEN and GPE1_LEN represent the length in bytes of each register block.
Each register block contains two registers of equal length:GPEx_STS and GPEx_EN (where x is 0 or 1). The length of the GPE0_STS and GPE0_EN registers is equal to half the GPE0_LEN. The length of the GPE1_STS and GPE1_EN registers is equal to half the GPE1_LEN. If a generic register block is not supported then its respective block pointer and block length values in the FADT table contain zeros. The GPE0_LEN and GPE1_LEN do not need to be the same size.
4.7.2   Fixed Hardware Features
This section describes the fixed hardware features defined by ACPI.
4.7.2.1   Power Management Timer
The ACPI specification requires a power management timer that provides an accurate time value used by system software to measure and profile system idleness (along with other tasks). The power management timer provides an accurate time function while the system is in the working (G0) state. To allow software to extend the number of bits in the timer, the power management timer generates an interrupt when the last bit of the timer changes (from 0 to 1 or 1 to 0). ACPI supports either a 24-bit or 32-bit power management timer. The PM Timer is accessed directly by OSPM, and its programming model is contained in fixed register space. The programming model can be partitioned in up to three different register blocks. The event bits are contained in the PM1_EVT register grouping, which has two register blocks, and the timer value can be accessed through the PM_TMR_BLK register block. A block diagram of the power management timer is illustrated in the following figure:

Figure 4-7   Power Management Timer
The power management timer is a 24-bit or 32-bit fixed rate free running count-up timer that runs off a 3.579545 MHz clock. The ACPI OS checks the FADT to determine whether the PM Timer is a 32-bit or 24-bit timer. The programming model for the PM Timer consists of event logic, and a read port to the counter value. The event logic consists of an event status and enable bit. The status bit is set any time the last bit of the timer (bit 23 or bit 31) goes from set to clear or clear to set. If the TMR_EN bit is set, then the setting of the TMR_STS will generate an ACPI event in the PM1_EVT register grouping (referred to as PMTMR_PME in the diagram). The event logic is only used to emulate a larger timer.
OSPM uses the read-only TMR_VAL field (in the PM TMR register grouping) to read the current value of the timer. OSPM never assumes an initial value of the TMR_VAL field; instead, it reads an initial TMR_VAL upon loading OSPM and assumes that the timer is counting. It is allowable to stop the Timer when the system transitions out of the working (G0/S0) state. The only timer reset requirement is that the timer functions while in the working state.
The PM Timer's programming model is implemented as a fixed hardware feature to increase the accuracy of reading the timer.
4.7.2.2   Console Buttons
ACPI defines user-initiated events to request OSPM to transition the platform between the G0 working state and the G1 sleeping, G2 soft off and G3 mechanical off states. ACPI also defines a recommended mechanism to unconditionally transition the platform from a hung G0 working state to the G2 soft-off state.
ACPI operating systems use power button events to determine when the user is present. As such, these ACPI events are associated with buttons in the ACPI specification.
The ACPI specification supports two button models:
·      A single-button model that generates an event for both sleeping and entering the soft-off state. The function of the button can be configured using OSPM UI.
·      A dual-button model where the power button generates a soft-off transition request and a sleeping button generates a sleeping transition request. The type of button implies the function of the button.
Control of these button events is either through the fixed hardware programming model or the generic hardware programming model (control method based). The fixed hardware programming model has the advantage that OSPM can access the button at any time, including when the system is crashed. In a crashed system with a fixed hardware power button, OSPM can make a "best" effort to determine whether the power button has been pressed to transition to the system to the soft-off state, because it doesn't require the AML interpreter to access the event bits.
4.7.2.2.1   Power Button
The power button logic can be used in one of two models:single button or dual button. In the single-button model, the user button acts as both a power button for transitioning the system between the G0 and G2 states and a sleeping button for transitioning the system between the G0 and G1 states. The action of the user pressing the button is determined by software policy or user settings. In the dual-button model, there are separate buttons for sleeping and power control. Although the buttons still generate events that cause software to take an action, the function of the button is now dedicated:the sleeping button generates a sleeping request to OSPM and the power button generates a waking request.
Support for a power button is indicated by a combination of the PWR_BUTTON flag and the power button device object, as shown in the following:
Table 4-8   Power Button Support

Indicated Support	PWR_BUTTON Flag	Power Button Device Object
Fixed hardware power button	Clear	Absent
Control method power button	Set	Present

The power button can also have an additional capability to unconditionally transition the system from a hung working state to the G2 soft-off state. In the case where OSPM event handler is no longer able to respond to power button events, the power button override feature provides a back-up mechanism to unconditionally transition the system to the soft-off state. This feature can be used when the platform doesn't have a mechanical off button, which can also provide this function. ACPI defines that holding the power button active for four seconds or longer will generate a power button override event.
4.7.2.2.1.1 Fixed Power Button

Figure 4-8 Fixed Power Button Logic
The fixed hardware power button has its event programming model in the PM1x_EVT_BLK. This logic consists of a single enable bit and sticky status bit. When the user presses the power button, the power button status bit (PWRBTN_STS) is unconditionally set. If the power button enable bit (PWRBTN_EN) is set and the power button status bit is set (PWRBTN_STS) due to a button press while the system is in the G0 state, then an SCI is generated. OSPM responds to the event by clearing the PWRBTN_STS bit. The power button logic provides debounce logic that sets the PWRBTN_STS bit on the button press "edge."
While the system is in the G1 or G2 global states (S1, S2, S3, S4 or S5 states), any further power button press after the button press that transitioned the system into the sleeping state unconditionally sets the power button status bit and wakes the system, regardless of the value of the power button enable bit. OSPM responds by clearing the power button status bit and waking the system.
4.7.2.2.1.2 Control Method Power Button
The power button programming model can also use the generic hardware programming model. This allows the power button to reside in any of the generic hardware address spaces (for example, the embedded controller) instead of fixed space. If the power button is implemented using generic hardware, then the OEM needs to define the power button as a device with an _HID object value of "PNP0C0C," which then identifies this device as the power button to OSPM. The AML event handler then generates a Notify command to notify OSPM that a power button event was generated. While the system is in the working state, a power button press is a user request to transition the system into either the sleeping (G1) or soft-off state (G2). In these cases, the power button event handler issues the Notify command with the device specific code of 0x80. This indicates to OSPM to pass control to the power button driver (PNP0C0C) with the knowledge that a transition out of the G0 state is being requested. Upon waking from a G1 sleeping state, the AML event handler generates a notify command with the code of 0x2 to indicate it was responsible for waking the system.
The power button device needs to be declared as a device within the ACPI Namespace for the platform and only requires an _HID example definition follows.

This example ASL code performs the following:
· Creates a device named "PWRB" and associates the Plug and Play identifier (through the _HID object) of "PNP0C0C."
·       The Plug and Play identifier associates this device object with the power button driver.
· Creates an operational region for the control method power button's programming model: System I/O space at 0x200.
·       Fields that are not accessed are written as zeros. These status bits clear upon writing a 1 to their bit position, therefore preserved would fail in this case.
· Creates a field within the operational region for the power button status bit (called PBP). In this case the power button status bit is a child of the general-purpose event status bit 0. When this bit is set, it is the responsibility of the ASL-code to clear it (OSPM clears the general-purpose status bits). The address of the status bit is 0x200.0 (bit 0 at address 0x200).
· Creates an additional status bit called PBW for the power button wake event. This is the next bit and its physical address would be 0x200.1 (bit 1 at address 0x200).
· Generates an event handler for the power button that is connected to bit 0 of the general-purpose event status register 0. The event handler does the following:
·       Clears the power button status bit in hardware (writes a one to it).
·       Notifies OSPM of the event by calling the Notify command passing the power button object and the device specific event indicator 0x80.

// Define a control method power button
Device(\_SB.PWRB){
    Name(_HID, EISAID("PNP0C0C"))
    Name(_PRW, Package(){0, 0x4})

    OperationRegion(\PHO, SystemIO, 0x200, 0x1)
    Field(\PHO, ByteAcc, NoLock, WriteAsZeros){
        PBP, 1,              // sleep/off request
        PBW, 1            // wakeup request
    }
} // end of power button device object

Scope(\_GPE){         // Root level event handlers
    Method(_L00){     // uses bit 0 of GP0_STS register
       If(\PBP){
           Store(One, \PBP)          // clear power button status
           Notify(\_SB.PWRB, 0x80) // Notify OS of event
       }
       If(\PBW){
           Store(One, \PBW)
           Notify(\_SB.PWRB, 0x2)
       }
    } // end of _L00 handler
} // end of \_GPE scope
4.7.2.2.1.3   Power Button Override
The ACPI specification also allows that if the user presses the power button for more than four seconds while the system is in the working state, a hardware event is generated and the system will transition to the soft-off state. This hardware event is called a power button override reaction to the power button override event, the hardware clears the power button status bit (PWRBTN_STS).

4.7.2.2.2 Sleep Button
When using the two button model, ACPI supports a second button that when pressed will request OSPM to transition the platform between the G0 working and G1 sleeping states. Support for a sleep button is indicated by a combination of the SLEEP_BUTTON flag and the sleep button device object:
Table 4-9 Sleep Button Support

Indicated Support	SLEEP_BUTTON Flag	Sleep Button Device Object
No sleep button	Set	Absent
Fixed hardware sleep button	Clear	Absent
Control method sleep button	Set	Present

4.7.2.2.2.1 Fixed Hardware Sleeping Button

Figure 4-9 Fixed Hardware Sleep Button Logic
The fixed hardware sleep button has its event programming model in the PM1x_EVT_BLK. This logic consists of a single enable bit and sticky status bit. When the user presses the sleep button, the sleep button status bit (SLPBTN_STS) is unconditionally set. Additionally, if the sleep button enable bit (SLPBTN_EN) is set, and the sleep button status bit is set (SLPBTN_STS, due to a button press) while the system is in the G0 state, then an SCI is generated. OSPM responds to the event by clearing the SLPBTN_STS bit. The sleep button logic provides debounce logic that sets the SLPBTN_STS bit on the button press "edge."
While the system is sleeping (in either the S0, S1, S2, S3 or S4 states), any further sleep button press (after the button press that caused the system transition into the sleeping state) sets the sleep button status bit (SLPBTN_STS) and wakes the system if the SLP_EN bit is set. OSPM responds by clearing the sleep button status bit and waking the system.
4.7.2.2.2.2 Control Method Sleeping Button
The sleep button programming model can also use the generic hardware programming model. This allows the sleep button to reside in any of the generic hardware address spaces (for example, the embedded controller) instead of fixed space. If the sleep button is implemented via generic hardware, then the OEM needs to define the sleep button as a device with an _HID object value of "PNP0C0E", which then identifies this device as the sleep button to OSPM. The AML event handler then generates a Notify command to notify OSPM that a sleep button event was generated. While in the working state, a sleep button press is a user request to transition the system into the sleeping (G1) state. In these cases the sleep button event handler issues the Notify command with the device specific code of 0x80. This will indicate to OSPM to pass control to the sleep button driver (PNP0C0E) with the knowledge that the user is requesting a transition out of the G0 state. Upon waking-up from a G1 sleeping state, the AML event handler generates a Notify command with the code of 0x2 to indicate it was responsible for waking the system.

The sleep button device needs to be declared as a device within the ACPI Namespace for the platform and only requires an _HID example definition is shown below.
The AML code below does the following:
· Creates a device named "SLPB" and associates the Plug and Play identifier (through the _HID object) of "PNP0C0E."
·       The Plug and Play identifier associates this device object with the sleep button driver.
· Creates an operational region for the control method sleep button's programming model: System I/O space at 0x201.
·       Fields that are not accessed are written as "1s" (these status bits clear upon writing a "1" to their bit position, hence preserved would fail in this case).
· Creates a field within the operational region for the sleep button status bit (called PBP). In this case the sleep button status bit is a child of the general-purpose status bit 0. When this bit is set it is the responsibility of the AML code to clear it (OSPM clears the general-purpose status bits). The address of the status bit is 0x201.0 (bit 0 at address 0x201).
· Creates an additional status bit called PBW for the sleep button wake event. This is the next bit and its physical address would be 0x201.1 (bit 1 at address 0x201).
· Generates an event handler for the sleep button that is connected to bit 0 of the general-purpose status register 0. The event handler does the following:
·       Clears the sleep button status bit in hardware (writes a "1" to it).
·       Notifies OSPM of the event by calling the Notify command passing the sleep button object and the device specific event indicator 0x80.

// Define a control method sleep button
Device(\_SB.SLPB){
    Name(_HID, EISAID("PNP0C0E"))
    Name(_PRW, Package(){0x01, 0x04})
    OperationRegion(\Boo, SystemIO, 0x201, 0x1)
    Field(\Boo, ByteAcc, NoLock, WriteAsZeros){
       SBP, 1,           // sleep request
       SBW, 1         // wakeup request
    } // end of field definition
}
Scope(\_GPE){         // Root level event handlers
    Method(_L01){     // uses bit 1 of GP0_STS register
       If(\SBP){
           Store(One, \SBP)             // clear sleep button status
           Notify(\_SB.SLPB, 0x80)      // Notify OS of event
       }
       If(\SBW){
           Store(One, \SBW)
           Notify(\_SB.SLPB, 0x2)
       }
    } // end of _L01 handler
} // end of \_GPE scope

4.7.2.3 Sleeping/Wake Control
The sleeping/wake logic consists of logic that will sequence the system into the defined low-power hardware sleeping state (S1-S4) or soft-off state (S5) and will wake the system back to the working state upon a wake event. Notice that the S4BIOS state is entered in a different manner (for more information, see section 15.1.4.2, "The S4BIOS Transition").

Figure 4-10 Sleeping/Wake Logic
The logic is controlled via two bit fields: Sleep Enable (SLP_EN) and Sleep Type (SLP_TYPx). The type of sleep state desired is programmed into the SLP_TYPx field and upon assertion of the SLP_EN the hardware will sequence the system into the defined sleeping state. OSPM gets values for the SLP_TYPx field from the \_Sx objects defined in the static definition block. If the object is missing OSPM assumes the hardware does not support that sleeping state. Prior to entering the desired sleeping state, OSPM will read the designated \_Sx object and place this value in the SLP_TYP field.
Additionally ACPI defines a fail-safe Off protocol called the "power button override," which allows the user to initiate an Off sequence in the case where the system software is no longer able to recover the system (the system has hung). ACPI defines that this sequence be initiated by the user pressing the power button for over 4 seconds, at which point the hardware unconditionally sequences the system to the Off state. This logic is represented by the PWRBTN_OR signal coming into the sleep logic.
While in any of the sleeping states (G1), an enabled "Wake" event will cause the hardware to sequence the system back to the working state (G0). The "Wake Status" bit (WAK_STS) is provided for OSPM to "spin-on" after setting the SLP_EN/SLP_TYP bit fields. When waking from the S1 sleeping state, execution control is passed backed to OSPM immediately, whereas when waking from the S2-S5 states execution control is passed to the BIOS software (execution begins at the CPU's reset vector). The WAK_STS bit provides a mechanism to separate OSPM's sleeping and waking code during an S1 sequence. When the hardware has sequenced the system into the sleeping state (defined here as the processor is no longer able to execute instructions), any enabled wake event is allowed to set the WAK_STS bit and sequence the system back on (to the G0 state). If the system does not support the S1 sleeping state, the WAK_STS bit can always return zero.
-If more than a single sleeping state is supported, then the sleeping/wake logic is required to be able to dynamically sequence between the different sleeping states. This is accomplished by waking the system; OSPM programs the new sleep state into the SLP_TYP field, and then sets the SLP_EN bit–placing the system again in the sleeping state.

4.7.2.4 Real Time Clock Alarm
If implemented, the Real Time Clock (RTC) alarm must generate a hardware wake event when in the sleeping state. The RTC can be programmed to generate an alarm. An enabled RTC alarm can be used to generate a wake event when the system is in a sleeping state. ACPI provides for additional hardware to support OSPM in determining that the RTC was the source of the wake event: the RTC_STS and RTC_EN bits. Although these bits are optional, if supported they must be implemented as described here.
If the RTC_STS and RTC_EN bits are not supported, OSPM will attempt to identify the RTC as a possible wake source; however, it might miss certain wake events. If implemented, the RTC wake feature is required to work in the following sleeping states: S1-S3. S4 wake is optional and supported through the RTC_S4 flag within the FADT (if set, then the platform supports RTC wake in the S4 state)[3].

When the RTC generates a wake event the RTC_STS bit will be set. If the RTC_EN bit is set, an RTC hardware power management event will be generated (which will wake the system from a sleeping state, provided the battery low signal is not asserted).

Figure 4-11   RTC Alarm
The RTC wake event status and enable bits are an optional fixed hardware feature and a flag within the FADT (FIX_RTC) indicates if the register bits are to be used by OSPM. If the RTC wake event status and enable bits are implemented in fixed hardware, OSPM can determine if the RTC was the source of the wake event without loading the entire OS. This also gives the platform the capability of indicating an RTC wake source without consuming a GPE bit, as would be required if RTC wake was not implemented using the fixed hardware RTC feature. If the fixed hardware feature event bits are not supported, then OSPM will attempt to determine this by reading the RTC's status field. If the platform implements the RTC fixed hardware feature, and this hardware consumes resources, the _FIX method can be used to correlate these resources with the fixed hardware. See section 6.2.4, "_FIX (Fixed Register Resource Provide", for details.
OSPM supports enhancements over the existing RTC device (which only supports a 99 year date and 24-hour alarm). Optional extensions are provided for the following features:
·       Day Alarm. The DAY_ALRM field points to an optional CMOS RAM location that selects the day within the month to generate an RTC alarm.
·       Month Alarm. The MON_ALRM field points to an optional CMOS RAM location that selects the month within the year to generate an RTC alarm.
·       Centenary Value. The CENT field points to an optional CMOS RAM location that represents the centenary value of the date (thousands and hundreds of years).

The RTC_STS bit may be set through the RTC interrupt (IRQ8 in IA-PC architecture systems). OSPM will insure that the periodic and update interrupt sources are disabled prior to sleeping. This allows the RTC's interrupt pin to serve as the source for the RTC_STS bit generation. Note however that if the RTC interrupt pin is used for RTC_STS generation, the RTC_STS bit value may not be accurate when waking from S4. If this value is accurate when waking from S4, the platform should set the S4_RTC_STS_VALID flag, so that OSPM can utilize the RTC_STS information.
Table 4-10 Alarm Field Decodings within the FADT

Field	Value	Address (Location) in RTC CMOS RAM (Must be Bank 0)
DAY_ALRM	Eight bit value that can represent 0x01-0x31 days in BCD or 0x01-0x1F days in binary. Bits 6 and 7 of this field are treated as Ignored by software. The RTC is initialized such that this field contains a "don't care" value when the BIOS switches from legacy to ACPI mode. A don't care value can be any unused value (not 0x1-0x31 BCD or 0x01-0x1F hex) that the RTC reverts back to a 24 hour alarm.	The DAY_ALRM field in the FADT will contain a non-zero value that represents an offset into the RTC's CMOS RAM area that contains the day alarm value. A value of zero in the DAY_ALRM field indicates that the day alarm feature is not supported.
MON_ALRM	Eight bit value that can represent 01-12 months in BCD or 0x01-0xC months in binary. The RTC is initialized such that this field contains a don't care value when the BIOS switches from legacy to ACPI mode. A "don't care" value can be any unused value (not 1-12 BCD or x01-xC hex) that the RTC reverts back to a 24 hour alarm and/or 31 day alarm).	The MON_ALRM field in the FADT will contain a non-zero value that represents an offset into the RTC's CMOS RAM area that contains the month alarm value. A value of zero in the MON_ALRM field indicates that the month alarm feature is not supported. If the month alarm is supported, the day alarm function must also be supported.
CENTURY	8-bit BCD or binary value. This value indicates the thousand year and hundred year (Centenary) variables of the date in BCD (19 for this century, 20 for the next) or binary (x13 for this century, x14 for the next).	The CENTURY field in the FADT will contain a non-zero value that represents an offset into the RTC's CMOS RAM area that contains the Centenary value for the date. A value of zero in the CENTURY field indicates that the Centenary value is not supported by this RTC.

4.7.2.5 Legacy/ACPI Select and the SCI Interrupt
As mentioned previously, power management events are generated to initiate an interrupt or hardware sequence. ACPI operating systems use the SCI interrupt handler to respond to events, while legacy systems use some type of transparent interrupt handler to respond to these events (that is, an SMI interrupt handler). ACPI-compatible hardware can choose to support both legacy and ACPI modes or just an ACPI mode. Legacy hardware is needed to support these features for non-ACPI-compatible operating systems. When the ACPI OS loads, it scans the BIOS tables to determine that the hardware supports ACPI, and then if the it finds the SCI_EN bit reset (indicating that ACPI is not enabled), issues an ACPI activate command to the SMI handler through the SMI command port BIOS acknowledges the switching to the ACPI model of power management by setting the SCI_EN bit (this bit can also be used to switch over the event mechanism as illustrated below):

Figure 4-12 Power Management Events to SMI/SCI Control Logic
The interrupt events (those that generate SMIs in legacy mode and SCIs in ACPI mode) are sent through a decoder controlled by the SCI_EN bit. For legacy mode this bit is reset, which routes the interrupt events to the SMI interrupt logic. For ACPI mode this bit is set, which routes interrupt events to the SCI interrupt logic. This bit always returns set for ACPI-compatible hardware that does not support a legacy power management mode (in other words, the bit is wired to read as "1" and ignore writes).
The SCI interrupt is defined to be a shareable interrupt and is connected to an OS visible interrupt that uses a shareable protocol FADT has an entry that indicates what interrupt the SCI interrupt is mapped to (see section 5.2.6, "System Description Table Header").
If the ACPI platform supports both legacy and ACPI modes, it has a register that generates a hardware event (for example, SMI for IA-PC processors). OSPM uses this register to make the hardware switch in and out of ACPI mode. Within the FADT are three values that signify the address (SMI_CMD) of this port and the data value written to enable the ACPI state (ACPI_ENABLE), and to disable the ACPI state (ACPI_DISABLE).
To transition an ACPI/Legacy platform from the Legacy mode to the ACPI mode the following would occur:
· ACPI driver checks that the SCI_EN bit is zero, and that it is in the Legacy mode.
· OSPM does an OUT to the SMI_CMD port with the data in the ACPI_ENABLE field of the FADT.
· OSPM polls the SCI_EN bit until it is sampled as SET.

To transition an ACPI/Legacy platform from the ACPI mode to the Legacy mode the following would occur:
· ACPI driver checks that the SCI_EN bit is one, and that it is in the ACPI mode.
· OSPM does an OUT to the SMI_CMD port with the data in the ACPI_DISABLE field of the FADT.
· OSPM polls the SCI_EN bit until it is sampled as RESET.
Platforms that only support ACPI always return a 1 for the SCI_EN bit. In this case OSPM skips the Legacy to ACPI transition stated above.

4.7.2.6   Processor Control
The ACPI specification defines several processor controls including power state control, throttling control, and performance state control. See Section 8, "Processor Power and Performance State Configuration and Control," for a complete description of the processor controls.
4.7.3   Fixed Hardware Registers
The fixed hardware registers are manipulated directly by OSPM. The following sections describe fixed hardware features under the programming model. OSPM owns all the fixed hardware resource registers; these registers cannot be manipulated by AML code. Registers are accessed with any width up to its register width (byte granular).
4.7.3.1   PM1 Event Grouping
The PM1 Event Grouping has a set of bits that can be distributed between two different register blocks. This allows these registers to be partitioned between two chips, or all placed in a single chip. Although the bits can be split between the two register blocks (each register block has a unique pointer within the FADT), the bit positions are maintained. The register block with unimplemented bits (that is, those implemented in the other register block) always returns zeros, and writes have no side effects.
4.7.3.1.1   PM1 Status Registers

Register Location:    <PM1a_EVT_BLK / PM1b_EVT_BLK> System I/O or Memory Space
Default Value:    00h
Attribute:        Read/Write
Size:             PM1_EVT_LEN / 2
The PM1 status registers contain the fixed hardware feature status bits. The bits can be split between two registers: PM1a_STS or PM1b_STS. Each register grouping can be at a different 32-bit aligned address and is pointed to by the PM1a_EVT_BLK or PM1b_EVT_BLK. The values for these pointers to the register space are found in the FADT. Accesses to the PM1 status registers are done through byte or word accesses.
For ACPI/legacy systems, when transitioning from the legacy to the G0 working state this register is cleared by BIOS prior to setting the SCI_EN bit (and thus passing control to OSPM). For ACPI only platforms (where SCI_EN is always set), when transitioning from either the mechanical off (G3) or soft-off state to the G0 working state this register is cleared prior to entering the G0 working state.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates that the feature is not supported as a fixed hardware feature, then software treats these bits as ignored.
Table 4-11   PM1 Status Registers Fixed Hardware Feature Status Bits

Bit	Name	Description
0	TMR_STS	This is the timer carry status bit. This bit gets set any time the 23^rd/31^st bit of a 24/32-bit counter changes (whenever the MSB changes from clear to set or set to clear. While TMR_EN and TMR_STS are set, an interrupt event is raised.
1-3	Reserved	Reserved
4	BM_STS	This is the bus master status bit. This bit is set any time a system bus master requests the system bus, and can only be cleared by writing a "1" to this bit position. Notice that this bit reflects bus master activity, not CPU activity (this bit monitors any bus master that can cause an incoherent cache for a processor in the C3 state when the bus master performs a memory transaction).

Table 4-11 PM1 Status Registers Fixed Hardware Feature Status Bits (continued)

Bit	Name	Description
5	GBL_STS	This bit is set when an SCI is generated due to the BIOS wanting the attention of the SCI handler. BIOS will have a control bit (somewhere within its address space) that will raise an SCI and set this bit. This bit is set in response to the BIOS releasing control of the Global Lock and having seen the pending bit set.
6-7	Reserved	Reserved. These bits always return a value of zero.
8	PWRBTN_STS	This optional bit is set when the Power Button is pressed the system working state, while PWRBTN_EN and PWRBTN_STS are both set, an interrupt event is raised. In the sleeping or soft-off state, a wake event is generated when the power button is pressed (regardless of the PWRBTN_EN bit setting). This bit is only set by hardware and can only be reset by software writing a "1" to this bit position. ACPI defines an optional mechanism for unconditional transitioning a system that has stopped working from the G0 working state into the G2 soft-off state called the power button override. If the Power Button is held active for more than four seconds, this bit is cleared by hardware and the system transitions into the G2/S5 Soft Off state (unconditionally). Support for the power button is indicated by the PWR_BUTTON flag in the FADT being reset (zero). If the PWR_BUTTON flag is set or a power button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM. If the power button was the cause of the wake (from an S1-S4 state), then this bit is set prior to returning control to OSPM.
9	SLPBTN_STS	This optional bit is set when the sleep button is pressed the system working state, while SLPBTN_EN and SLPBTN_STS are both set, an interrupt event is raised. In the sleeping or soft-off states a wake event is generated when the sleeping button is pressed and the SLPBTN_EN bit is set. This bit is only set by hardware and can only be reset by software writing a "1" to this bit position. Support for the sleep button is indicated by the SLP_BUTTON flag in the FADT being reset (zero). If the SLP_BUTTON flag is set or a sleep button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM. If the sleep button was the cause of the wake (from an S1-S4 state), then this bit is set prior to returning control to OSPM.

Table 4-11 PM1 Status Registers Fixed Hardware Feature Status Bits (continued)

Bit	Name	Description
10	RTC_STS	This optional bit is set when the RTC generates an alarm (asserts the RTC IRQ signal). Additionally, if the RTC_EN bit is set then the setting of the RTC_STS bit will generate a power management event (an SCI, SMI, or resume event). This bit is only set by hardware and can only be reset by software writing a "1" to this bit position. If the RTC was the cause of the wake (from an S1-S3 state), then this bit is set prior to returning control to OSPM. If the RTC_S4 flag within the FADT is set, and the RTC was the cause of the wake from the S4 state), then this bit is set prior to returning control to OSPM.
11	Ignore	This bit field is ignored by software.
12-13	Reserved	Reserved. These bits always return a value of zero.
14	PCIEXP_WAKE_STS	This bit is required for chipsets that implement PCI Express. This bit is set by hardware to indicate that the system woke due to a PCI Express wakeup event. A PCI Express wakeup event is defined as the PCI Express WAKE# pin being active , one or more of the PCI Express ports being in the beacon state, or receipt of a PCI Express PME message at a root port. This bit should only be set when one of these events causes the system to transition from a non-S0 system power state to the S0 system power state. This bit is set independent of the state of the PCIEXP_WAKE_DIS bit. Software writes a 1 to clear this bit. If the WAKE# pin is still active during the write, one or more PCI Express ports is in the beacon state or the PME message received indication has not been cleared in the root port, then the bit will remain active (i.e. all inputs to this bit are level-sensitive). Note: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake.
15	WAK_STS	This bit is set when the system is in the sleeping state and an enabled wake event occurs. Upon setting this bit system will transition to the working state. This bit is set by hardware and can only be cleared by software writing a "1" to this bit position.

4.7.3.1.2   PM1 Enable Registers

Register Location:    <PM1a_EVT_BLK / PM1b_EVT_BLK>+ PM1_EVT_LEN / 2 System I/O or
                                                                    Memory Space
Default Value:    00h
Attribute:        Read/Write
Size:             PM1_EVT_LEN / 2
The PM1 enable registers contain the fixed hardware feature enable bits. The bits can be split between two registers: PM1a_EN or PM1b_EN. Each register grouping can be at a different 32-bit aligned address and is pointed to by the PM1a_EVT_BLK or PM1b_EVT_BLK. The values for these pointers to the register space are found in the FADT. Accesses to the PM1 Enable registers are done through byte or word accesses.
For ACPI/legacy systems, when transitioning from the legacy to the G0 working state the enables are cleared by BIOS prior to setting the SCI_EN bit (and thus passing control to OSPM). For ACPI-only platforms (where SCI_EN is always set), when transitioning from either the mechanical off (G3) or soft-off state to the G0 working state this register is cleared prior to entering the G0 working state.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates that the feature is not supported as a fixed hardware feature, then software treats the enable bits as write as zero.

Table 4-12 PM1 Enable Registers Fixed Hardware Feature Enable Bits

Bit	Name	Description
0	TMR_EN	This is the timer carry interrupt enable bit. When this bit is set then an SCI event is generated anytime the TMR_STS bit is set. When this bit is reset then no interrupt is generated when the TMR_STS bit is set.
1-4	Reserved	Reserved. These bits always return a value of zero.
5	GBL_EN	The global enable bit. When both the GBL_EN bit and the GBL_STS bit are set, an SCI is raised.
6-7	Reserved	Reserved
8	PWRBTN_EN	This optional bit is used to enable the setting of the PWRBTN_STS bit to generate a power management event (SCI or wake) PWRBTN_STS bit is set anytime the power button is asserted. The enable bit does not have to be set to enable the setting of the PWRBTN_STS bit by the assertion of the power button (see description of the power button hardware). Support for the power button is indicated by the PWR_BUTTON flag in the FADT being reset (zero). If the PWR_BUTTON flag is set or a power button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM.
9	SLPBTN_EN	This optional bit is used to enable the setting of the SLPBTN_STS bit to generate a power management event (SCI or wake) SLPBTN_STS bit is set anytime the sleep button is asserted. The enable bit does not have to be set to enable the setting of the SLPBTN_STS bit by the active assertion of the sleep button (see description of the sleep button hardware). Support for the sleep button is indicated by the SLP_BUTTON flag in the FADT being reset (zero). If the SLP_BUTTON flag is set or a sleep button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM.
10	RTC_EN	This optional bit is used to enable the setting of the RTC_STS bit to generate a wake event. The RTC_STS bit is set any time the RTC generates an alarm.
11-13	Reserved	Reserved. These bits always return a value of zero.
14	PCIEXP_WAKE_DIS	This bit is required for chipsets that implement PCI Express. This bit disables the inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the system. Modification of this bit has no impact on the value of the PCIEXP_WAKE_STS bit.
15	Reserved	Reserved. These bits always return a value of zero.

4.7.3.2 PM1 Control Grouping
The PM1 Control Grouping has a set of bits that can be distributed between two different registers. This allows these registers to be partitioned between two chips, or all placed in a single chip. Although the bits can be split between the two register blocks (each register block has a unique pointer within the FADT), the bit positions specified here are maintained. The register block with unimplemented bits (that is, those implemented in the other register block) returns zeros, and writes have no side effects.

4.7.3.2.1   PM1 Control Registers

Register Location:    <PM1a_CNT_BLK / PM1b_CNT_BLK>       System I/O or Memory Space
Default Value:    00h
Attribute:        Read/Write
Size:             PM1_CNT_LEN
The PM1 control registers contain the fixed hardware feature control bits. These bits can be split between two registers: PM1a_CNT or PM1b_CNT. Each register grouping can be at a different 32-bit aligned address and is pointed to by the PM1a_CNT_BLK or PM1b_CNT_BLK. The values for these pointers to the register space are found in the FADT. Accesses to PM1 control registers are accessed through byte and word accesses.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates that the feature is not supported as a fixed hardware feature, then software treats these bits as ignored.
Table 4-13   PM1 Control Registers Fixed Hardware Feature Control Bits

Bit	Name	Description
0	SCI_EN	Selects the power management event to be either an SCI or SMI interrupt for the following events. When this bit is set, then power management events will generate an SCI interrupt. When this bit is reset power management events will generate an SMI interrupt. It is the responsibility of the hardware to set or reset this bit. OSPM always preserves this bit position.
1	BM_RLD	When set, this bit allows the generation of a bus master request to cause any processor in the C3 state to transition to the C0 state. When this bit is reset, the generation of a bus master request does not affect any processor in the C3 state.
2	GBL_RLS	This write-only bit is used by the ACPI software to raise an event to the BIOS software, that is, generates an SMI to pass execution control to the BIOS for IA-PC platforms. BIOS software has a corresponding enable and status bit to control its ability to receive ACPI events (for example, BIOS_EN and BIOS_STS). The GBL_RLS bit is set by OSPM to indicate a release of the Global Lock and the setting of the pending bit in the FACS memory structure.
3-8	Reserved	Reserved. These bits are reserved by OSPM.
9	Ignore	Software ignores this bit field.
10-12	SLP_TYPx	Defines the type of sleeping state the system enters when the SLP_EN bit is set to one. This 3-bit field defines the type of hardware sleep state the system enters when the SLP_EN bit is set. The \_Sx object contains 3-bit binary values associated with the respective sleeping state (as described by the object). OSPM takes the two values from the \_Sx object and programs each value into the respective SLP_TYPx field.
13	SLP_EN	This is a write-only bit and reads to it always return a zero. Setting this bit causes the system to sequence into the sleeping state associated with the SLP_TYPx fields programmed with the values from the \_Sx object.
14-15	Reserved	Reserved. This field always returns zero.

4.7.3.3   Power Management Timer (PM_TMR)

Register Location:    <PM_TMR_BLK> System I/O or Memory Space
Default Value:    00h
Attribute:        Read-Only
Size:             32 bits
This read-only register returns the current value of the power management timer (PM timer). The FADT has a flag called TMR_VAL_EXT that an OEM sets to indicate a 32-bit PM timer or reset to indicate a 24-bit PM timer. When the last bit of the timer toggles the TMR_STS bit is set. This register is accessed as 32 bits.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates that the feature is not supported as a fixed hardware feature, then software treats these bits as ignored.
Table 4-14   PM Timer Bits

Bit	Name	Description
0-23	TMR_VAL	This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off a 3.579545-MHz clock and counts while in the S0 working system state. The starting value of the timer is undefined, thus allowing the timer to be reset (or not) by any transition to the S0 state from any other state. The timer is reset (to any initial value), and then continues counting until the system's 14.31818 MHz clock is stopped upon entering its Sx state. If the clock is restarted without a reset, then the counter will continue counting from where it stopped.
24-31	E_TMR_VAL	This read-only field returns the upper eight bits of a 32-bit power management timer. If the hardware supports a 32-bit timer, then this field will return the upper eight bits; if the hardware supports a 24-bit timer then this field returns all zeros.

4.7.3.4   PM2 Control (PM2_CNT)

Register Location:    <PM2_CNT_BLK> System I/O, System Memory, or
                                 Functional Fixed Hardware Space
Default Value:    00h
Attribute:        Read/Write
Size:             PM2_CNT_LEN
This register block is naturally aligned and accessed based on its length. For ACPI 1.0 this register is byte aligned and accessed as a byte.
This register contains optional features enabled or disabled within the FADT. If the FADT indicates that the feature is not supported as a fixed hardware feature, then software treats these bits as ignored.
Table 4-15   PM2 Control Register Bits

Bit

Name

Description

ARB_DIS

This bit is used to enable and disable the system arbiter. When this bit is CLEAR the system arbiter is enabled and the arbiter can grant the bus to other bus masters. When this bit is SET the system arbiter is disabled and the default CPU has ownership of the system.

OSPM clears this bit when using the C0, C1 and C2 power states.

Reserved

Reserved

4.7.3.5   Processor Register Block (P_BLK)
This optional register block is used to control each processor in the system. There is one unique processor register block per processor in the system. For more information about controlling processors and control methods that can be used to control processors, see section 8, "Processor Power and Performance State Configuration and Control." This register block is DWORD aligned and the context of this register block is not maintained across S3 or S4 sleeping states, or the S5 soft-off state.
4.7.3.5.1   Processor Control (P_CNT): 32

Register Location:    Either <P_BLK>:              System I/O Space
                  or specified by _PTC Object:    System I/O, System Memory, or
                                               Functional Fixed Hardware Space
Default Value:    00h
Attribute:        Read/Write
Size:             32 bits
This register is accessed as a DWORD. The CLK_VAL field is where the duty setting of the throttling hardware is programmed as described by the DUTY_WIDTH and DUTY_OFFSET values in the FADT. Software treats all other CLK_VAL bits as ignored (those not used by the duty setting value).
Table 4-16   Processor Control Register Bits

Bit	Name	Description
0-3	CLK_VAL	Possible locations for the clock throttling value.
4	THT_EN	This bit enables clock throttling of the clock as set in the CLK_VAL field. THT_EN bit must be reset LOW when changing the CLK_VAL field (changing the duty setting).
5-31	CLK_VAL	Possible locations for the clock throttling value.

4.7.3.5.2   Processor LVL2 Register (P_LVL2): 8

Register Location:    Either <P_BLK> + 4:          System I/O Space
                  or specified by _CST Object:    System I/O, System Memory, or
                                               Functional Fixed Hardware Space
Default Value:    00h
Attribute:        Read-Only
Size:             8 bits
This register is accessed as a byte.
Table 4-17   Processor LVL2 Register Bits

Bit	Name	Description
0-7	P_LVL2	Reads to this register return all zeros; writes to this register have no effect. Reads to this register also generate an "enter a C2 power state" to the clock control logic.

4.7.3.5.3   Processor LVL3 Register (P_LVL3): 8

Register Location:    Either <P_BLK> + 5:         System I/O Space
                  or specified by _CST Object:    System I/O, System Memory, or
                                               Functional Fixed Hardware Space
Default Value:    00h
Attribute:        Read-Only
Size:             8 bits
This register is accessed as a byte.
Table 4-18   Processor LVL3 Register Bits

Bit	Name	Description
0-7	P_LVL3	Reads to this register return all zeros; writes to this register have no effect. Reads to this register also generate an "enter a C3 power state" to the clock control logic.

4.7.3.6 Reset Register
The optional ACPI reset mechanism specifies a standard mechanism that provides a complete system reset. When implemented, this mechanism must reset the entire system. This includes processors, core logic, all buses, and all peripherals. From an OSPM perspective, asserting the reset mechanism is the logical equivalent to power cycling the machine. Upon gaining control after a reset, OSPM will perform actions in like manner to a cold boot.
The reset mechanism is implemented via an 8-bit register described by RESET_REG in the FADT (always accessed via the natural alignment and size described in RESET_REG). To reset the machine, software will write a value (indicated in RESET_VALUE in FADT) to the reset register. The RESET_REG field in the FADT indicates the location of the reset register.
The reset register may exist only in I/O space, Memory space, or in PCI Configuration space on a function in bus 0. Therefore, the Address_Space_ID value in RESET_REG must be set to I/O space, Memory space, or PCI Configuration space (with a bus number of 0). As the register is only 8 bits, Register_Bit_Wid^th must be 8 and Register_Bit_Offset must be 0.
The system must reset immediately following the write to this register. OSPM assumes that the processor will not execute beyond the write instruction. OSPM should execute spin loops on the CPUs in the system following a write to this register.
4.7.4 Generic Hardware Registers
ACPI provides a mechanism that allows a unique piece of "value added" hardware to be described to OSPM in the ACPI Namespace. There are a number of rules to be followed when designing ACPI-compatible hardware.
Programming bits can reside in any of the defined generic hardware address spaces (system I/O, system memory, PCI configuration, embedded controller, or SMBus), but the top-level event bits are contained in the general-purpose event registers. The general-purpose event registers are pointed to by the GPE0_BLK and GPE1_BLK register blocks, and the generic hardware registers can be in any of the defined ACPI address spaces. A device's generic hardware programming model is described through an associated object in the ACPI Namespace, which specifies the bit's function, location, address space, and address location.
The programming model for devices is normally broken into status and control functions. Status bits are used to generate an event that allows OSPM to call a control method associated with the pending status bit. The called control method can then control the hardware by manipulating the hardware control bits or by investigating child status bits and calling their respective control methods. ACPI requires that the top level "parent" event status and enable bits reside in either the GPE0_STS or GPE1_STS registers, and "child" event status bits can reside in generic address space.

The example below illustrates some of these concepts top diagram shows how the logic is partitioned into two chips: a chipset and an embedded controller.
·       The chipset contains the interrupt logic, performs the power button (which is part of the fixed register space, and is not discussed here), the lid switch (used in portables to indicate when the clam shell lid is open or closed), and the RI# function (which can be used to wake a sleeping system).
·       The embedded controller chip is used to perform the AC power detect and dock/undock event logic. Additionally, the embedded controller supports some system management functions using an OS-transparent interrupt in the embedded controller (represented by the EXTSMI# signal).

Figure 4-13   Example of General-Purpose vs. Generic Hardware Events
At the top level, the generic events in the GPEx_STS register are the:

·       Embedded controller interrupt, which contains two query events: one for AC detection and one for docking (the docking query event has a child interrupt status bit in the docking chip).
·       Ring indicate status (used for waking the system).
·       Lid status.
The embedded controller event status bit (EC_STS) is used to indicate that one of two query events is active.
·       A query event is generated when the AC# signal is asserted. The embedded controller returns a query value of 34 (any byte number can be used) upon a query command in response to this event; OSPM will then schedule for execution the control method associated with query value 34.
Another query event is for the docking chip that generates a docking event. In this case, the embedded controller will return a query value of 35 upon a query command from system software responding to an SCI from the embedded controller. OSPM will then schedule the control method associated with the query value of 35 to be executed, which services the docking event.
For each of the status bits in the GPEx_STS register, there is a corresponding enable bit in the GPEx_EN register. Notice that the child status bits do not necessarily need enable bits (see the DOCK_STS bit).
The lid logic contains a control bit to determine if its status bit is set when the LID is open (LID_POL is set and LID is set) or closed (LID_POL is clear and LID is clear). This control bit resides in generic I/O space (in this case, bit 2 of system I/O space 33h) and would be manipulated with a control method associated with the lid object.
As with fixed hardware events, OSPM will clear the status bits in the GPEx register blocks. However, AML code clears all sibling status bits in the generic hardware.
Generic hardware features are controlled by OEM supplied control methods, encoded in AML. ACPI provides both an event and control model for development of these features. The ACPI specification also provides specific control methods for notifying OSPM of certain power management and Plug and Play events. Section 5, "ACPI Software Programming Model," provides information on the types of hardware functionality that support the different types of subsystems. The following is a list of features supported by ACPI list is not intended to be complete or comprehensive.
·       Device insertion/ejection (for example, docking, device bay, A/C adapter)
·       Batteries[4]
·       Platform thermal subsystem
·       Turning on/off power resources
·       Mobile lid Interface
·       Embedded controller
·       System indicators
·       OEM-specific wake events
·       Plug and Play configuration
4.7.4.1   General-Purpose Event Register Blocks
ACPI supports up to two general-purpose register blocks as described in the FADT (see section 5, "ACPI Software Programming Model") and an arbitrary number of additional GPE blocks described as devices within the ACPI namespace. Each register block contains two registers: an enable and a status register. Each register block is 32-bit aligned. Each register in the block is accessed as a byte. It is up to the specific design to determine if these bits retain their context across sleeping or soft-off states. If they lose their context across a sleeping or soft-off state, then BIOS resets the respective enable bit prior to passing control to the OS upon waking.
4.7.4.1.1   General-Purpose Event 0 Register Block
This register block consists of two registers: The GPE0_STS and the GPE0_EN registers. Each register's length is defined to be half the length of the GPE0 register block, and is described in the ACPI FADT's GPE0_BLK and GPE0_BLK_LEN operators. OSPM owns the general-purpose event resources and these bits are only manipulated by OSPM; AML code cannot access the general-purpose event registers.
It is envisioned that chipsets will contain GPE event registers that provide GPE input pins for various events.
The platform designer would then wire the GPEs to the various value-added event hardware and the AML code would describe to OSPM how to utilize these events. As such, there will be the case where a platform has GPE events that are not wired to anything (they are present in the chip set), but are not utilized by the platform and have no associated AML code. In such, cases these event pins are to be tied inactive such that the corresponding SCI status bit in the GPE register is not set by a floating input pin.

4.7.4.1.1.1   General-Purpose Event 0 Status Register

Register Location:    <GPE0_STS> System I/O or System Memory Space
Default Value:    00h
Attribute:        Read/Write
Size:             GPE0_BLK_LEN/2
The general-purpose event 0 status register contains the general-purpose event status bits in bank zero of the general-purpose registers. Each available status bit in this register corresponds to the bit with the same bit position in the GPE0_EN register. Each available status bit in this register is set when the event is active, and can only be cleared by software writing a "1" to its respective bit position. For the general-purpose event registers, unimplemented bits are ignored by OSPM.
Each status bit can optionally wake the system if asserted when the system is in a sleeping state with its respective enable bit set. OSPM accesses GPE registers through byte accesses (regardless of their length).
4.7.4.1.1.2   General-Purpose Event 0 Enable Register

Register Location:    <GPE0_EN> System I/O or System Memory Space
Default Value:    00h
Attribute:        Read/Write
Size:             GPE0_BLK_LEN/2
The general-purpose event 0 enable register contains the general-purpose event enable bits. Each available enable bit in this register corresponds to the bit with the same bit position in the GPE0_STS register enable bits work similarly to how the enable bits in the fixed-event registers are defined: When the enable bit is set, then a set status bit in the corresponding status bit will generate an SCI bit. OSPM accesses GPE registers through byte accesses (regardless of their length).
4.7.4.1.2   General-Purpose Event 1 Register Block
This register block consists of two registers: The GPE1_STS and the GPE1_EN registers. Each register's length is defined to be half the length of the GPE1 register block, and is described in the ACPI FADT's GPE1_BLK and GPE1_BLK_LEN operators.
4.7.4.1.2.1   General-Purpose Event 1 Status Register

Register Location:    <GPE1_STS> System I/O or System Memory Space
Default Value:    00h
Attribute:        Read/Write
Size:             GPE1_BLK_LEN/2
The general -purpose event 1 status register contains the general-purpose event status bits. Each available status bit in this register corresponds to the bit with the same bit position in the GPE1_EN register. Each available status bit in this register is set when the event is active, and can only be cleared by software writing a "1" to its respective bit position the general-purpose event registers, unimplemented bits are ignored by the operating system.
Each status bit can optionally wake the system if asserted when the system is in a sleeping state with its respective enable bit set.
OSPM accesses GPE registers through byte accesses (regardless of their length).

4.7.4.1.2.2   General-Purpose Event 1 Enable Register

Register Location:    <GPE1_EN> System I/O or System Memory Space
Default Value:    00h
Attribute:        Read/Write
Size:             GPE1_BLK_LEN/2
The general-purpose event 1 enable register contains the general-purpose event enable. Each available enable bit in this register corresponds to the bit with the same bit position in the GPE1_STS register enable bits work similarly to how the enable bits in the fixed-event registers are defined: When the enable bit is set, a set status bit in the corresponding status bit will generate an SCI bit.
OSPM accesses GPE registers through byte accesses (regardless of their length).
4.7.4.2   Example Generic Devices
This section points out generic devices with specific ACPI driver support.
4.7.4.2.1   Lid Switch
The Lid switch is an optional feature present in most "clam shell" style mobile computers. It can be used by the OS as policy input for sleeping the system, or for waking the system from a sleeping state. If used, then the OEM needs to define the lid switch as a device with an _HID object value of "_PNP0C0D", which identifies this device as the lid switch to OSPM. The Lid device needs to contain a control method that returns its status Lid event handler AML code reconfigures the lid hardware (if it needs to) to generate an event in the other direction, clear the status, and then notify OSPM of the event.
Example hardware and ASL code is shown below for such a design.

Figure 4-14   Example Generic Address Space Lid Switch Logic
This logic will set the Lid status bit when the button is pressed or released (depending on the LID_POL bit).
The ASL code below defines the following:
·      An operational region where the lid polarity resides in address space System address space in registers 0x201.
·      A field operator to allow AML code to access this bit: Polarity control bit (LID_POL) is called LPOL and is accessed at 0x201.0.
·      A device named \_SB.LID with the following:
·       A Plug and Play identifier "PNP0C0D" that associates OSPM with this object.
·       Defines an object that specifies a change in the lid's status bit can wake the system from the S4 sleep state and from all higher sleep states (S1, S2, or S3).

·      The lid switch event handler that does the following:
·       Defines the lid status bit (LID_STS) as a child of the general-purpose event 0 register bit 1.
·       Defines the event handler for the lid (only event handler on this status bit) that does the following:
·       Flips the polarity of the LPOL bit (to cause the event to be generated on the opposite condition).
·       Generates a notify to the OS that does the following:
·       Passes the \_SB.LID object.
·       Indicates a device specific event (notify value 0x80).

// Define a Lid switch
OperationRegion(\PHO, SystemIO, 0x201, 0x1)
Field(\PHO, ByteAcc, NoLock, Preserve) {
    LPOL, 1                  // Lid polarity control bit
}

Device(\_SB.LID){
    Name(_HID, EISAID("PNP0C0D"))
    Method(_LID){Return(LPOL)}
    Name(_PRW, Package(2){
       1,                // bit 1 of GPE to enable Lid wakeup
       0x04}             // can wakeup from S4 state
    )
}
Scope(\_GPE){            // Root level event handlers
    Method(_L01){         // uses bit 1 of GP0_STS register
       Not(LPOL, LPOL)   // Flip the lid polarity bit
       Notify(LID, 0x80) // Notify OS of event
    }
}
4.7.4.2.2   Embedded Controller
ACPI provides a standard interface that enables AML code to define and access generic logic in "embedded controller space." This supports current computer models where much of the value added hardware is contained within the embedded controller while allowing the AML code to access this hardware in an abstracted fashion.
The embedded controller is defined as a device and must contain a set number of control methods:
·      _HID with a value of PNP0C09 to associate this device with the ACPI's embedded controller's driver.
·      _CRS to return the resources being consumed by the embedded controller.
·      _GPE that returns the general-purpose event bit that this embedded controller is wired to.
Additionally the embedded controller can support up to 255 generic events per embedded controller, referred to as query events. These query event handles are defined within the embedded controller's device as control methods. An example of defining an embedded controller device is shown below:

Device(EC0) {
    // PnP ID
    Name(_HID, EISAID("PNP0C09"))
    // Returns the "Current Resources" of EC
    Name(_CRS,
        ResourceTemplate(){
           IO(Decode16, 0x62, 0x62, 0, 1)
           IO(Decode16, 0x66, 0x66, 0, 1)
    })
    // Define that the EC SCI is bit 0 of the GP_STS register
    Name(_GPE, 0)     // embedded controller is wired to bit 0 of GPE

    OperationRegion(\EC0, EmbeddedControl, 0, 0xFF)
    Field(EC0, ByteAcc, Lock, Preserve) {
    // Field definitions
    }
    Method(Q00){..}
    Method(QFF){..}
}
For more information on the embedded controller, see section 12, "ACPI Embedded Controller Interface Specification."
4.7.4.2.3   Fan
ACPI has a device driver to control fans (active cooling devices) in platforms. A fan is defined as a device with the Plug and Play ID of "PNP0C0B." It should then contain a list power resources used to control the fan.
For more information, see section 9, "ACPI Devices and Device Specific Objects."

5   ACPI Software Programming Model
ACPI defines a hardware register interface that an ACPI-compatible OS uses to control core power management features of a machine, as described in section 4, "ACPI Hardware Specification." ACPI also provides an abstract interface for controlling the power management and configuration of an ACPI system. Finally, ACPI defines an interface between an ACPI-compatible OS and the system BIOS.
To give hardware vendors flexibility in choosing their implementation, ACPI uses tables to describe system information, features, and methods for controlling those features. These tables list devices on the system board or devices that cannot be detected or power managed using some other hardware standard, plus their capabilities as described in section 3, "Overview." They also list system capabilities such as the sleeping power states supported, a description of the power planes and clock sources available in the system, batteries, system indicator lights, and so on. This enables OSPM to control system devices without needing to know how the system controls are implemented.
Topics covered in this section are:
·       The ACPI system description table architecture is defined, and the role of OEM-provided definition blocks in that architecture is discussed.
·       The concept of the ACPI Namespace is discussed.
5.1   Overview of the System Description Table Architecture
The Root System Description Pointer (RSDP) structure is located in the system's memory address space and is setup by the platform firmware. This structure contains the address of the Extended System Description Table (XSDT), which references other description tables that provide data to OSPM, supplying it with knowledge of the base system's implementation and configuration (see Figure 5-1).

Figure 5-1   Root System Description Pointer and Table
All system description tables start with identical headers. The primary purpose of the system description tables is to define for OSPM various industry-standard implementation details. Such definitions enable various portions of these implementations to be flexible in hardware requirements and design, yet still provide OSPM with the knowledge it needs to control hardware directly.

The Extended System Description Table (XSDT) points to other tables in memory. Always the first table, it points to the Fixed ACPI Description table (FADT). The data within this table includes various fixed-length entries that describe the fixed ACPI features of the hardware FADT table always refers to the Differentiated System Description Table (DSDT), which contains information and descriptions for various system features. The relationship between these tables is shown in Figure 5-2.

Figure 5-2 Description Table Structures
· OSPM finds the RSDP structure as described in section 5.2.5.1 ("Finding the RSDP on IA-PC Systems") or section 5.2.5.2 ("Finding the RSDP on EFI Enabled Systems").
When OSPM locates the structure, it looks at the physical address for the Root System Description Table or the Extended System Description Table. The Root System Description Table starts with the signature "RSDT", while the Extended System Description Table starts with the signature "XSDT". These tables contain one or more physical pointers to other system description tables that provide various information about the system. As shown in Figure 5-1, there is always a physical address in the Root System Description Table for the Fixed ACPI Description table (FADT).
When OSPM follows a physical pointer to another table, it examines each table for a known signature. Based on the signature, OSPM can then interpret the implementation-specific data within the description table.
The purpose of the FADT is to define various static system information related to configuration and power management. The Fixed ACPI Description Table starts with the "FACP" signature. The FADT describes the implementation and configuration details of the ACPI hardware registers on the platform.

For a specification of the ACPI Hardware Register Blocks (PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK, PM2_CNT_BLK, PM_TMR_BLK, GP0_BLK, GP1_BLK, and one or more P_BLKs), see section 4.7, "ACPI Register Model." The PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK, PM2_CNT_BLK, and PM_TMR_BLK blocks are for controlling low-level ACPI system functions.
The GPE0_BLK and GPE1_BLK blocks provide the foundation for an interrupt-processing model for Control Methods. The P_BLK blocks are for controlling processor features.
Besides ACPI Hardware Register implementation information, the FADT also contains a physical pointer to the Differentiated System Description Table (DSDT). The DSDT contains a Definition Block named the Differentiated Definition Block for the DSDT that contains implementation and configuration information OSPM can use to perform power management, thermal management, or Plug and Play functionality that goes beyond the information described by the ACPI hardware registers.
A Definition Block contains information about hardware implementation details in the form of a hierarchical namespace, data, and control methods encoded in AML. OSPM "loads" or "unloads" an entire definition block as a logical unit. The Differentiated Definition Block is always loaded by OSPM at boot time and cannot be unloaded.
Definition Blocks can either define new system attributes or, in some cases, build on prior definitions. A Definition Block can be loaded from system memory address space. One use of a Definition Block is to describe and distribute platform version changes.
Definition blocks enable wide variations of hardware platform implementations to be described to the ACPI-compatible OS while confining the variations to reasonable boundaries. Definition blocks enable simple platform implementations to be expressed by using a few well-defined object names. In theory, it might be possible to define a PCI configuration space-like access method within a Definition Block, by building it from I/O space, but that is not the goal of the Definition Block specification. Such a space is usually defined as a "built in" operator.
Some operators perform simple functions and others encompass complex functions power of the Definition Block comes from its ability to allow these operations to be glued together in numerous ways, to provide functionality to OSPM operators present are intended to allow many useful hardware designs to be ACPI-expressed, not to allow all hardware designs to be expressed.
5.1.1 Address Space Translation
Some platforms may contain bridges that perform translations as I/O and/or Memory cycles pass through the bridges. This translation can take the form of the addition or subtraction of an offset it can take the form of a conversion from I/O cycles into Memory cycles and back again. When translation takes place, the addresses placed on the processor bus by the processor during a read or write cycle are not the same addresses that are placed on the I/O bus by the I/O bus bridge. The address the processor places on the processor bus will be known here as the processor-relative address. And the address that the bridge places on the I/O bus will be known as the bus-relative address. Unless otherwise noted, all addresses used within this section are processor-relative addresses.
For example, consider a platform with two root PCI buses. The platform designer has several choices. One solution would be to split the 16-bit I/O space into two parts, assigning one part to the first root PCI bus and one part to the second root PCI bus. Another solution would be to make both root PCI buses decode the entire 16-bit I/O space, mapping the second root PCI bus's I/O space into memory space. In this second scenario, when the processor needs to read from an I/O register of a device underneath the second root PCI bus, it would need to perform a memory read within the range that the root PCI bus bridge is using to map the I/O space.
Note: Industry standard PCs do not provide address space translations because of historical compatibility issues.

5.2   ACPI System Description Tables
This section specifies the structure of the system description tables:
·       Root System Description Pointer (RSDP)
·       System Description Table Header
·       Root System Description Table (RSDT)
·       Fixed ACPI Description Table (FADT)
·       Firmware ACPI Control Structure (FACS)
·       Differentiated System Description Table (DSDT)
·       Secondary System Description Table (SSDT)
·       Multiple APIC Description Table (MADT)
·       Smart Battery Table (SBST)
·       Extended System Description Table (XSDT)
·       Embedded Controller Boot Resources Table (ECDT)
·       System Locality Distance Information Table (SLIT)
·       System Resource Affinity Table (SRAT)
All numeric values in ACPI-defined tables, blocks, and structures are always encoded in little endian format. Signature values are stored as fixed-length strings.
5.2.1   Reserved Bits and Fields
For future expansion, all data items marked as reserved in this specification have strict meanings. This section lists software requirements for reserved fields. Notice that the list contains terms such as ACPI tables and AML code defined later in this section of the specification.
5.2.1.1   Reserved Bits and Software Components
·      OEM implementations of software and AML code return the bit value of 0 for all reserved bits in ACPI tables or in other software values, such as resource descriptors.
·      For all reserved bits in ACPI tables and registers, OSPM implementations must:
·      Ignore all reserved bits that are read.
·      Preserve reserved bit values of read/write data items (for example, OSPM writes back reserved bit values it reads).
·      Write zeros to reserved bits in write-only data items.
5.2.1.2   Reserved Values and Software Components
·      OEM implementations of software and AML code return only defined values and do not return reserved values.
·      OSPM implementations write only defined values and do not write reserved values.
5.2.1.3   Reserved Hardware Bits and Software Components
·      Software ignores all reserved bits read from hardware enable or status registers.
·      Software writes zero to all reserved bits in hardware enable registers.
·      Software ignores all reserved bits read from hardware control and status registers.
·      Software preserves the value of all reserved bits in hardware control registers by writing back read values.
5.2.1.4   Ignored Hardware Bits and Software Components
·      Software handles ignored bits in ACPI hardware registers the same way it handles reserved bits in these same types of registers.

5.2.2   Compatibility
All versions of the ACPI tables must maintain backward compatibility. To accomplish this, modifications of the tables consist of redefinition of previously reserved fields and values plus appending data to the 1.0 tables. Modifications of the ACPI tables require that the version numbers of the modified tables be incremented. The length field in the tables includes all additions and the checksum is maintained for the entire length of the table.
5.2.3   Address Format
Addresses used in the ACPI 1.0 system description tables were expressed as either system memory or I/O space. This was targeted at the IA-32 environment. Newer architectures require addressing mechanisms beyond that defined in ACPI 1.0. To support these architectures ACPI must support 64-bit addressing and it must allow the placement of control registers in address spaces other than System I/O.
5.2.3.1   Generic Address Structure
The Generic Address Structure (GAS) provides the platform with a robust means to describe register locations. This structure, described below (Table 5-1), is used to express register addresses within tables defined by ACPI .
Table 5-1   Generic Address Structure (GAS)

Field	Byte Length	Byte Offset	Description
Address_Space_ID	1	0	The address space where the data structure or register exists. Defined values are: 0 System Memory 1 System I/O 2 PCI Configuration Space 3 Embedded Controller 4 SMBus 5 to 0x7E – Reserved 0x7F Functional Fixed Hardware 0x80 to 0xBF – Reserved 0xC0 to 0xFF – OEM Defined
Register_Bit_Wid^th	1	1	The size in bits of the given register. When addressing a data structure, this field must be zero.
Register_Bit_Offset	1	2	The bit offset of the given register at the given address. When addressing a data structure, this field must be zero.
Access_Size	1	3	Specifies access size. 0 Undefined (legacy reasons) 1 Byte access 2 Word access 3 Dword access 4 Qword access
Address	8	4	The 64-bit address of the data structure or register in the given address space (relative to the processor). (See below for specific formats.)

Table 5-2 Address Space Format

Address Space	Format
0–System Memory	The 64-bit physical memory address (relative to the processor) of the register. 32-bit platforms must have the high DWORD set to 0.
1–System I/O	The 64-bit I/O address (relative to the processor) of the register. 32-bit platforms must have the high DWORD set to 0.
2–PCI Configuration Space	PCI Configuration space addresses must be confined to devices on PCI Segment Group 0, bus 0. This restriction exists to accommodate access to fixed hardware prior to PCI bus enumeration. The format of addresses are defined as follows:
	WORD Location	Description
	Highest WORD	Reserved (must be 0)
	�	PCI Device number on bus 0
	�	PCI Function number
	Lowest WORD	Offset in the configuration space header
	For example: Offset 23h of Function 2 on device 7 on bus 0 segment 0 would be represented as: 0x0000000700020023.
0x7F–Functional Fixed Hardware	Use of GAS fields other than Address_Space_ID is specified by the CPU manufacturer. The use of functional fixed hardware carries with it a reliance on OS specific software that must be considered. OEMs should consult OS vendors to ensure that specific functional fixed hardware interfaces are supported by specific operating systems.

5.2.4   Universal Uniform Identifiers (UUID)
UUIDs (Universally Unique IDentifiers), also known as GUIDs (Globally Unique IDentifiers) are 128 bit long values that extremely likely to be different from all other UUIDs generated until 3400 A.D. UUIDs are used to distinguish between callers of ASL methods, such as _DSM and _OSC.
The format of both the binary and string representations of UUIDs along with an algorithm to generate them is specified in ISO/IEC 11578:1996 and can be found as part of the Distributed Computing Environment 1.1: Remote Procedure Call specification, which can be downloaded from here: http://www.opengroup.org/publications/catalog/c706.htm >.
5.2.5   Root System Description Pointer (RSDP)
During OS initialization, OSPM must obtain the Root System Description Pointer (RSDP) structure from the platform. When OSPM locates the Root System Description Pointer (RSDP) structure, it then locates the Root System Description Table (RSDT) or the Extended Root System Description Table (XSDT) using the physical system address supplied in the RSDP.
5.2.5.1   Finding the RSDP on IA-PC Systems
OSPM finds the Root System Description Pointer (RSDP) structure by searching physical memory ranges on 16-byte boundaries for a valid Root System Description Pointer structure signature and checksum match as follows:
·      The first 1 KB of the Extended BIOS Data Area (EBDA). For EISA or MCA systems, the EBDA can be found in the two-byte location 40:0Eh on the BIOS data area.
·      The BIOS read-only memory space between 0E0000h and 0FFFFFh.
5.2.5.2   Finding the RSDP on EFI Enabled Systems
In Extensible Firmware Interface (EFI) enabled systems (for example, Itanium^TM-based platforms) a pointer to the RSDP structure exists within the EFI System Table. The OS loader's EFI image is provided a pointer to the EFI System Table at invocation. The OS loader must retrieve the pointer to the RSDP structure from the EFI System table and convey the pointer to OSPM, using an OS dependent data structure, as part of the hand off of control from the OS loader to the OS.
The OS loader locates the pointer to the RSDP structure by examining the EFI configuration table within the EFI system table configuration table entries consist of Globally Unique Identifier (GUID)/table pointer pairs. The EFI 1.0 specification defines a GUID for ACPI. An EFI configuration table entry that matches this GUID points to an ACPI 1.0-compatible RSDP structure (ACPI 1.0 GUID).
The EFI GUID for a pointer to the current revision RSDP structure is: 8868E871-E4F1-11d3-BC22-0080C73C8881.
The OS loader for an ACPI-compatible OS will search for an RSDP structure pointer using the current revision GUID first and if it finds one, will use the corresponding RSDP structure pointer. If the GUID is not found then the OS loader will search for the RSDP structure pointer using the ACPI 1.0 version GUID.
The OS loader must retrieve the pointer to the RSDP structure from the EFI System Table before assuming platform control via the EFI ExitBootServices interface the EFI specification for more information.
5.2.5.3   RSDP Structure
The revision number contained within the structure indicates the size of the table structure.
Table 5-3   Root System Description Pointer Structure

Field	Byte Length	Byte Offset	Description
Signature	8	0	"RSD PTR " (Notice that this signature must contain a trailing blank character.)
Checksum	1	8	This is the checksum of the fields defined in the ACPI 1.0 specification. This includes only the first 20 bytes of this table, bytes 0 to 19, including the checksum field. These bytes must sum to zero.
OEMID	6	9	An OEM-supplied string that identifies the OEM.
Revision	1	15	The revision of this structure. Larger revision numbers are backward compatible to lower revision numbers. The ACPI version 1.0 revision number of this table is zero. The current value for this field is 2.
RsdtAddress	4	16	32 bit physical address of the RSDT.
Length	4	20	The length of the table, in bytes, including the header, starting from offset 0. This field is used to record the size of the entire table.
XsdtAddress	8	24	64 bit physical address of the XSDT.
Extended Checksum	1	32	This is a checksum of the entire table, including both checksum fields.
Reserved	3	33	Reserved field

5.2.6 System Description Table Header
All system description tables begin with the structure shown in Table 5-4. The Signature field determines the content of the system description table. System description table signatures defined by this specification are listed in Table 5-5.
Table 5-4 DESCRIPTION_HEADER Fields

Field	Byte Length	Byte Offset	Description
Signature	4	0	The ASCII string representation of the table identifier. Notice that if OSPM finds a signature in a table that is not listed in Table 5-5, OSPM ignores the entire table (it is not loaded into ACPI namespace); OSPM ignores the table even though the values in the Length and Checksum fields are correct.
Length	4	4	The length of the table, in bytes, including the header, starting from offset 0. This field is used to record the size of the entire table.
Revision	1	8	The revision of the structure corresponding to the signature field for this table. Larger revision numbers are backward compatible to lower revision numbers with the same signature.
Checksum	1	9	The entire table, including the checksum field, must add to zero to be considered valid.
OEMID	6	10	An OEM-supplied string that identifies the OEM.
OEM Table ID	8	16	An OEM-supplied string that the OEM uses to identify the particular data table. This field is particularly useful when defining a definition block to distinguish definition block functions. The OEM assigns each dissimilar table a new OEM Table ID.
OEM Revision	4	24	An OEM-supplied revision number. Larger numbers are assumed to be newer revisions.
Creator ID	4	28	Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler.

For OEMs, good design practices will ensure consistency when assigning OEMID and OEM Table ID fields in any table. The intent of these fields is to allow for a binary control system that support services can use. Because many support functions can be automated, it is useful when a tool can programmatically determine which table release is a compatible and more recent revision of a prior table on the same OEMID and OEM Table ID.
Tables 5-5 and 5-6 contain the system description table signatures defined by this specification. These system description tables may be defined by ACPI and documented within this specification (Table 5-5) or reserved by ACPI and defined by other industry specifications (Table 5-6). This allows OS and platform specific tables to be defined and pointed to by the RSDT/XSDT as needed. For tables defined by other industry specifications, the ACPI specification acts as gatekeeper to avoid collisions in table signatures. Table signatures will be reserved by the ACPI promoters and posted independently of this specification in ACPI errata and clarification documents on the ACPI Web site. Requests to reserve a 4-byte alphanumeric table signature should be sent to the email address info@acpi.info and should include the purpose of the table and reference url to a document that describes the table format. Tables defined outside of the ACPI specification may define data value encodings in either little endian or big endian format. For the purpose of clarity, external table definition documents should include the endian-ness of their data value encodings.
Table 5-5 DESCRIPTION_HEADER Signatures for tables defined by ACPI

Signature	Description	Reference
"APIC"	Multiple APIC Description Table	Section 5.2.11.4, "Multiple APIC Description Table"
"DSDT"	Differentiated System Description Table	Section 5.2.11.1, "Differentiated System Description Table"
"ECDT"	Embedded Controller Boot Resources Table	Section 5.2.14, "Embedded Controller Boot Resources Table"
"FACP"	Fixed ACPI Description Table (FADT)	Section 5.2.9, "Fixed ACPI Description Table"
"FACS"	Firmware ACPI Control Structure	Section 5.2.10, "Firmware ACPI Control Structure"
"OEMx"	OEM Specific Information Tables	OEM Specific tables. All table signatures starting with "OEM" are reserved for OEM use.
"PSDT"	Persistent System Description Table	Section 5.2.11.3, "Persistent System Description Table"
"RSDT"	Root System Description Table	Section 5.2.7, "Root System Description Table"
"SBST"	Smart Battery Specification Table	Section 5.2 13, "Smart Battery Table"
"SLIT"	System Locality Distance Information Table	Section 5.2.16, "System Locality Distance Information Table"
"SRAT"	System Resource Affinity Table	Section 5.2.15, "System Resource Affinity Table"
"SSDT"	Secondary System Description Table	Section 5.2.11.2, "Secondary System Description Table"
"XSDT"	Extended System Description Table	Section 5.2.8, "Extended System Description Table"

Table 5-6 DESCRIPTION_HEADER Signatures for tables reserved by ACPI

Signature	Description	Comments / Reference
"BERT"	Boot Error Record Table	http://www.microsoft.com/whdc
"BOOT"	Simple Boot Flag Table	Microsoft Simple Boot Flag Specification http://www.microsoft.com/whdc/resources/respec/specs/simp_boot.mspx
"CPEP"	Corrected Platform Error Polling Table	DIG64 Corrected Platform Error Polling Specification http://www.dig64.org/specifications
"DBGP"	Debug Port Table	Microsoft Debug Port Specification http://www.microsoft.com/HWDEV/PLATFORM/pcdesign/LR/debugspec.asp
"DMAR"	DMA Remapping Table	http://download.intel.com/technology/computing/vptech/Intel(r)_VT_for_Direct_IO.pdf
"ERST"	Error Record Serialization Table	http://www.microsoft.com/whdc
"ETDT"	Event Timer Description Table	IA-PC Multimedia Timers Specification. This signature has been superseded by "HPET" and is now obsolete.
"HEST"	Hardware Error Source Table	http://www.microsoft.com/whdc
"HPET"	IA-PC High Precision Event Timer Table	IA-PC High Precision Event Timer Specification. http://www.intel.com/hardwaredesign/hpetspec.htm
"IBFT"	iSCSI Boot Firmware Table	http://www.microsoft.com/whdc
"MCFG"	PCI Express memory mapped configuration space base address Description Table	PCI Firmware Specification, Revision 3.0 http://pcisig.com
"SPCR"	Serial Port Console Redirection Table	Microsoft Serial Port Console Redirection Table http://www.microsoft.com/HWDEV/PLATFORM/server/headless/SPCR.asp
"SPMI"	Server Platform Management Interface Table	ftp://download.intel.com/design/servers/ipmi/IPMIv2_0rev1_0.pdf
"TCPA"	Trusted Computing Platform Alliance Capabilities Table	TCPA PC Specific Implementation Specification https://www.trustedcomputinggroup.org/home
"UEFI"	UEFI ACPI Boot Optimization Table	UEFI Specification, http://www.uefi.org.
"WAET"	Windows ACPI Enlightenment Table	http://www.microsoft.com/whdc
"WDAT"	Watch Dog Action Table	Requirements for Hardware Watchdog Timers Supported by Windows – Design Specification http://www.microsoft.com/whdc/system/CEC/hw-wdt.mspx
"WDRT"	Watchdog Resource Table	Watchdog Timer Hardware Requirements for Windows Server 2003 http://www.microsoft.com/whdc/system/CEC/watchdog.mspx
"WSPT"	Windows Specific Properties Table	http://www.microsoft.com/whdc

5.2.7 Root System Description Table (RSDT)
OSPM locates that Root System Description Table by following the pointer in the RSDP structure. The RSDT, shown in Table 5-7, starts with the signature 'RSDT' followed by an array of physical pointers to other system description tables that provide various information on other standards defined on the current system. OSPM examines each table for a known signature. Based on the signature, OSPM can then interpret the implementation-specific data within the table.
Platforms provide the RSDT to enable compatibility with ACPI 1.0 operating systems. The XSDT, described in the next section, supersedes RSDT functionality.
Table 5-7 Root System Description Table Fields (RSDT)

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'RSDT' Signature for the Root System Description Table.
Length	4	4	Length, in bytes, of the entire RSDT. The length implies the number of Entry fields (n) at the end of the table.
Revision	1	8	1
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	For the RSDT, the table ID is the manufacture model ID. This field must match the OEM Table ID in the FADT.
OEM Revision	4	24	OEM revision of RSDT table for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler.
Entry	4*n	36	An array of 32-bit physical addresses that point to other DESCRIPTION_HEADERs. OSPM assumes at least the DESCRIPTION_HEADER is addressable, and then can further address the table based upon its Length field.

5.2.8 Extended System Description Table (XSDT)
The XSDT provides identical functionality to the RSDT but accommodates physical addresses of DESCRIPTION HEADERs that are larger than 32-bits. Notice that both the XSDT and the RSDT can be pointed to by the RSDP structure. An ACPI-compatible OS must use the XSDT if present.
Table 5-8 Extended System Description Table Fields (XSDT)

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'XSDT'. Signature for the Extended System Description Table.
Length	4	4	Length, in bytes, of the entire table. The length implies the number of Entry fields (n) at the end of the table.
Revision	1	8	1
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	For the XSDT, the table ID is the manufacture model ID. This field must match the OEM Table ID in the FADT.
OEM Revision	4	24	OEM revision of XSDT table for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler.
Entry	8*n	36	An array of 64-bit physical addresses that point to other DESCRIPTION_HEADERs. OSPM assumes at least the DESCRIPTION_HEADER is addressable, and then can further address the table based upon its Length field.

5.2.9 Fixed ACPI Description Table (FADT)
The Fixed ACPI Description Table (FADT) defines various fixed hardware ACPI information vital to an ACPI-compatible OS, such as the base address for the following hardware registers blocks: PM1a_EVT_BLK, PM1b_EVT_BLK, PM1a_CNT_BLK, PM1b_CNT_BLK, PM2_CNT_BLK, PM_TMR_BLK, GPE0_BLK, and GPE1_BLK.
The FADT also has a pointer to the DSDT that contains the Differentiated Definition Block, which in turn provides variable information to an ACPI-compatible OS concerning the base system design.
All fields in the FADT that provide hardware addresses provide processor-relative physical addresses.
Table 5-9 Fixed ACPI Description Table (FADT) Format

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'FACP'. Signature for the Fixed ACPI Description Table.
Length	4	4	Length, in bytes, of the entire FADT.
Revision	1	8	4
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	For the FADT, the table ID is the manufacture model ID. This field must match the OEM Table ID in the RSDT.
OEM Revision	4	24	OEM revision of FADT for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler.
FIRMWARE_CTRL	4	36	Physical memory address (0-4 GB) of the FACS, where OSPM and Firmware exchange control information. See section 5.2.6, "Root System Description Table," for a description of the FACS.
DSDT	4	40	Physical memory address (0-4 GB) of the DSDT.
Reserved	1	44	ACPI 1.0 defined this offset as a field named INT_MODEL, which was eliminated in ACPI 2.0. Platforms should set this field to zero but field values of one are also allowed to maintain compatibility with ACPI 1.0.
Preferred_PM_Profile	1	45	This field is set by the OEM to convey the preferred power management profile to OSPM. OSPM can use this field to set default power management policy parameters during OS installation. Field Values: 0 Unspecified 1 Desktop 2 Mobile 3 Workstation 4 Enterprise Server 5 SOHO Server 6 Appliance PC 7 Performance Server >7 Reserved
SCI_INT	2	46	System vector the SCI interrupt is wired to in 8259 mode systems that do not contain the 8259, this field contains the Global System interrupt number of the SCI interrupt. OSPM is required to treat the ACPI SCI interrupt as a sharable, level, active low interrupt.
SMI_CMD	4	48	System port address of the SMI Command Port. During ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers. OSPM issues commands to the SMI_CMD port synchronously from the boot processor. This field is reserved and must be zero on system that does not support System Management mode.
ACPI_ENABLE	1	52	The value to write to SMI_CMD to disable SMI ownership of the ACPI hardware registers. The last action SMI does to relinquish ownership is to set the SCI_EN bit. During the OS initialization process, OSPM will synchronously wait for the transfer of SMI ownership to complete, so the ACPI system releases SMI ownership as quickly as possible. This field is reserved and must be zero on systems that do not support Legacy Mode.
ACPI_DISABLE	1	53	The value to write to SMI_CMD to re-enable SMI ownership of the ACPI hardware registers. This can only be done when ownership was originally acquired from SMI by OSPM using ACPI_ENABLE. An OS can hand ownership back to SMI by relinquishing use to the ACPI hardware registers, masking off all SCI interrupts, clearing the SCI_EN bit and then writing ACPI_DISABLE to the SMI_CMD port from the boot processor. This field is reserved and must be zero on systems that do not support Legacy Mode.
S4BIOS_REQ	1	54	The value to write to SMI_CMD to enter the S4BIOS state S4BIOS state provides an alternate way to enter the S4 state where the firmware saves and restores the memory context. A value of zero in S4BIOS_F indicates S4BIOS_REQ is not supported. (See Table 5-12.)
PSTATE_CNT	1	55	If non-zero, this field contains the value OSPM writes to the SMI_CMD register to assume processor performance state control responsibility.
PM1a_EVT_BLK	4	56	System port address of the PM1a Event Register Block section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This is a required field. This field is superseded by the X_PM1a_EVT_BLK field.
PM1b_EVT_BLK	4	60	System port address of the PM1b Event Register Block section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. This field is superseded by the X_PM1b_EVT_BLK field.
PM1a_CNT_BLK	4	64	System port address of the PM1a Control Register Block section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This is a required field. This field is superseded by the X_PM1a_CNT_BLK field.
PM1b_CNT_BLK	4	68	System port address of the PM1b Control Register Block section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. This field is superseded by the X_PM1b_CNT_BLK field.
PM2_CNT_BLK	4	72	System port address of the PM2 Control Register Block section 4.7.3.4, "PM2 Control (PM2_CNT)," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. This field is superseded by the X_PM2_CNT_BLK field.
PM_TMR_BLK	4	76	System port address of the Power Management Timer Control Register Block. See section 4.7.3.3, "Power Management Timer (PM_TMR)," for a hardware description layout of this register block. This is a required field. This field is superseded by the X_PM_TMR_BLK field.
GPE0_BLK	4	80	System port address of General-Purpose Event 0 Register Block. See section 4.7.4.1, "General-Purpose Event Register Blocks," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero. This field is superseded by the X_GPE0_BLK field.
GPE1_BLK	4	84	System port address of General-Purpose Event 1 Register Block. See section 4.7.4.1, "General-Purpose Event Register Blocks," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero. This field is superseded by the X_GPE1_BLK field.
PM1_EVT_LEN	1	88	Number of bytes decoded by PM1a_EVT_BLK and, if supported, PM1b_ EVT_BLK. This value is � 4.
PM1_CNT_LEN	1	89	Number of bytes decoded by PM1a_CNT_BLK and, if supported, PM1b_CNT_BLK. This value is � 2.
PM2_CNT_LEN	1	90	Number of bytes decoded by PM2_CNT_BLK. Support for the PM2 register block is optional. If supported, this value is � 1. If not supported, this field contains zero.
PM_TMR_LEN	1	91	Number of bytes decoded by PM_TMR_BLK. This field's value must be 4.
GPE0_BLK_LEN	1	92	Number of bytes decoded by GPE0_BLK. The value is a non-negative multiple of 2.
GPE1_BLK_LEN	1	93	Number of bytes decoded by GPE1_BLK. The value is a non-negative multiple of 2.
GPE1_BASE	1	94	Offset within the ACPI general-purpose event model where GPE1 based events start.
CST_CNT	1	95	If non-zero, this field contains the value OSPM writes to the SMI_CMD register to indicate OS support for the _CST object and C States Changed notification.
P_LVL2_LAT	2	96	The worst-case hardware latency, in microseconds, to enter and exit a C2 state. A value > 100 indicates the system does not support a C2 state.
P_LVL3_LAT	2	98	The worst-case hardware latency, in microseconds, to enter and exit a C3 state. A value > 1000 indicates the system does not support a C3 state.
FLUSH_SIZE	2	100	If WBINVD=0, the value of this field is the number of flush strides that need to be read (using cacheable addresses) to completely flush dirty lines from any processor's memory caches. Notice that the value in FLUSH_STRIDE is typically the smallest cache line width on any of the processor's caches (for more information, see the FLUSH_STRIDE field definition). If the system does not support a method for flushing the processor's caches, then FLUSH_SIZE and WBINVD are set to zero. Notice that this method of flushing the processor caches has limitations, and WBINVD=1 is the preferred way to flush the processors caches. This value is typically at least 2 times the cache size. The maximum allowed value for FLUSH_SIZE multiplied by FLUSH_STRIDE is 2 MB for a typical maximum supported cache size of 1 MB. Larger cache sizes are supported using WBINVD=1. This value is ignored if WBINVD=1. This field is maintained for ACPI 1.0 processor compatibility on existing systems. Processors in new ACPI-compatible systems are required to support the WBINVD function and indicate this to OSPM by setting the WBINVD field = 1.
FLUSH_STRIDE	2	102	If WBINVD=0, the value of this field is the cache line width, in bytes, of the processor's memory caches. This value is typically the smallest cache line width on any of the processor's caches. For more information, see the description of the FLUSH_SIZE field. This value is ignored if WBINVD=1. This field is maintained for ACPI 1.0 processor compatibility on existing systems. Processors in new ACPI-compatible systems are required to support the WBINVD function and indicate this to OSPM by setting the WBINVD field = 1.
DUTY_OFFSET	1	104	The zero-based index of where the processor's duty cycle setting is within the processor's P_CNT register.
DUTY_WIDTH	1	105	The bit width of the processor's duty cycle setting value in the P_CNT register. Each processor's duty cycle setting allows the software to select a nominal processor frequency below its absolute frequency as defined by: THTL_EN = 1 BF * DC/(2^DUTY_WIDTH) Where: BF–Base frequency DC–Duty cycle setting When THTL_EN is 0, the processor runs at its absolute BF. A DUTY_WIDTH value of 0 indicates that processor duty cycle is not supported and the processor continuously runs at its base frequency.
DAY_ALRM	1	106	The RTC CMOS RAM index to the day-of-month alarm value this field contains a zero, then the RTC day of the month alarm feature is not supported. If this field has a non-zero value, then this field contains an index into RTC RAM space that OSPM can use to program the day of the month alarm. See section 4.7.2.4, "Real Time Clock Alarm," for a description of how the hardware works.
MON_ALRM	1	107	The RTC CMOS RAM index to the month of year alarm value this field contains a zero, then the RTC month of the year alarm feature is not supported. If this field has a non-zero value, then this field contains an index into RTC RAM space that OSPM can use to program the month of the year alarm. If this feature is supported, then the DAY_ALRM feature must be supported also.
CENTURY	1	108	The RTC CMOS RAM index to the century of data value (hundred and thousand year decimals). If this field contains a zero, then the RTC centenary feature is not supported. If this field has a non-zero value, then this field contains an index into RTC RAM space that OSPM can use to program the centenary field.
IAPC_BOOT_ARCH	2	109	IA-PC Boot Architecture Flags. See Table 5-11 for a description of this field.
Reserved	1	111	Must be 0.
Flags	4	112	Fixed feature flags. See Table 5-10 for a description of this field.
RESET_REG	12	116	The address of the reset register represented in Generic Address Structure format (See section 4.7.3.6, "Reset Register," for a description of the reset mechanism.) Note: Only System I/O space, System Memory space and PCI Configuration space (bus #0) are valid for values for Address_Space_ID. Also, Register_Bit_Wid^th must be 8 and Register_Bit_Offset must be 0.
RESET_VALUE	1	128	Indicates the value to write to the RESET_REG port to reset the system. (See section 4.7.3.6, "Reset Register," for a description of the reset mechanism.)
Reserved	3	129	Must be 0.
X_FIRMWARE_CTRL	8	132	64bit physical address of the FACS.
X_DSDT	8	140	64bit physical address of the DSDT.
X_PM1a_EVT_BLK	12	148	Extended address of the PM1a Event Register Block, represented in Generic Address Structure format. See section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This is a required field.
X_PM1b_EVT_BLK	12	160	Extended address of the PM1b Event Register Block, represented in Generic Address Structure format. See section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero.
X_PM1a_CNT_BLK	12	172	Extended address of the PM1a Control Register Block, represented in Generic Address Structure format. See section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This is a required field.
X_PM1b_CNT_BLK	12	184	Extended address of the PM1b Control Register Block, represented in Generic Address Structure format. See section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero.
X_PM2_CNT_BLK	12	196	Extended address of the Power Management 2 Control Register Block, represented in Generic Address Structure format. See section 4.7.3.4, "PM2 Control (PM2_CNT)," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero.
X_PM_TMR_BLK	12	208	Extended address of the Power Management Timer Control Register Block, represented in Generic Address Structure format. See section 4.7.3.3, "Power Management Timer (PM_TMR)," for a hardware description layout of this register block. This is a required field.
X_GPE0_BLK	12	220	Extended address of the General-Purpose Event 0 Register Block, represented in Generic Address Structure format. See section 5.2.8, "Fixed ACPI Description Table," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero.
X_GPE1_BLK	12	232	Extended address of the General-Purpose Event 1 Register Block, represented in Generic Address Structure format. See section 5.2.8, "Fixed ACPI Description Table," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero.

Table 5-10 Fixed ACPI Description Table Fixed Feature Flags

FACP - Flag	Bit Length	Bit Offset	Description
WBINVD	1	0	Processor properly implements a functional equivalent to the WBINVD IA-32 instruction. If set, signifies that the WBINVD instruction correctly flushes the processor caches, maintains memory coherency, and upon completion of the instruction, all caches for the current processor contain no cached data other than what OSPM references and allows to be cached. If this flag is not set, the ACPI OS is responsible for disabling all ACPI features that need this function. This field is maintained for ACPI 1.0 processor compatibility on existing systems. Processors in new ACPI-compatible systems are required to support this function and indicate this to OSPM by setting this field.
WBINVD_FLUSH	1	1	If set, indicates that the hardware flushes all caches on the WBINVD instruction and maintains memory coherency, but does not guarantee the caches are invalidated. This provides the complete semantics of the WBINVD instruction, and provides enough to support the system sleeping states neither of the WBINVD flags is set, the system will require FLUSH_SIZE and FLUSH_STRIDE to support sleeping states. If the FLUSH parameters are also not supported, the machine cannot support sleeping states S1, S2, or S3.
PROC_C1	1	2	A one indicates that the C1 power state is supported on all processors.
P_LVL2_UP	1	3	A zero indicates that the C2 power state is configured to only work on a uniprocessor (UP) system. A one indicates that the C2 power state is configured to work on a UP or multiprocessor (MP) system.
PWR_BUTTON	1	4	A zero indicates the power button is handled as a fixed feature programming model; a one indicates the power button is handled as a control method device. If the system does not have a power button, this value would be "1" and no sleep button device would be present. Independent of the value of this field, the presence of a power button device in the namespace indicates to OSPM that the power button is handled as a control method device.
SLP_BUTTON	1	5	A zero indicates the sleep button is handled as a fixed feature programming model; a one indicates the sleep button is handled as a control method device. If the system does not have a sleep button, this value would be "1" and no sleep button device would be present. Independent of the value of this field, the presence of a sleep button device in the namespace indicates to OSPM that the sleep button is handled as a control method device.
FIX_RTC	1	6	A zero indicates the RTC wake status is supported in fixed register space; a one indicates the RTC wake status is not supported in fixed register space.
RTC_S4	1	7	Indicates whether the RTC alarm function can wake the system from the S4 state. The RTC must be able to wake the system from an S1, S2, or S3 sleep state. The RTC alarm can optionally support waking the system from the S4 state, as indicated by this value.
TMR_VAL_EXT	1	8	A zero indicates TMR_VAL is implemented as a 24-bit value. A one indicates TMR_VAL is implemented as a 32-bit value. The TMR_STS bit is set when the most significant bit of the TMR_VAL toggles.
DCK_CAP	1	9	A zero indicates that the system cannot support docking. A one indicates that the system can support docking. Notice that this flag does not indicate whether or not a docking station is currently present; it only indicates that the system is capable of docking.
RESET_REG_SUP	1	10	If set, indicates the system supports system reset via the FADT RESET_REG as described in section 4.7. 3.6, "Reset Register."
SEALED_CASE	1	11	System Type Attribute. If set indicates that the system has no internal expansion capabilities and the case is sealed.
HEADLESS	1	12	System Type Attribute. If set indicates the system cannot detect the monitor or keyboard / mouse devices.
CPU_SW_SLP	1	13	If set, indicates to OSPM that a processor native instruction must be executed after writing the SLP_TYPx register.
PCI_EXP_WAK	1	14	If set, indicates the platform supports the PCIEXP_WAKE_STS bit in the PM1 Status register and the PCIEXP_WAKE_EN bit in the PM1 Enable register.
USE_PLATFORM_CLOCK	1	15	A value of one indicates that OSPM should use a platform provided timer to drive any monotonically non-decreasing counters, such as OSPM performance counter services. Which particular platform timer will be used is OSPM specific, however, it is recommended that the timer used is based on the following algorithm: If the HPET is exposed to OSPM, OSPM should use the HPET. Otherwise, OSPM will use the ACPI power management timer. A value of one indicates that the platform is known to have a correctly implemented ACPI power management timer. A platform may choose to set this flag if a internal processor clock (or clocks in a multi-processor configuration) cannot provide consistent monotonically non-decreasing counters. Note: If a value of zero is present, OSPM may arbitrarily choose to use an internal processor clock or a platform timer clock for these operations. That is, a zero does not imply that OSPM will necessarily use the internal processor clock to generate a monotonically non-decreasing counter to the system.
S4_RTC_STS_VALID	1	16	A one indicates that the contents of the RTC_STS flag is valid when waking the system from S4. See Table 4-11 – PM1 Status Registers Fixed Hardware Feature Status Bits for more information. Some existing systems do not reliably set this input today, and this bit allows OSPM to differentiate correctly functioning platforms from platforms with this errata.
REMOTE_POWER_ON_CAPABLE	1	17	A one indicates that the platform is compatible with remote power on. That is, the platform supports OSPM leaving GPE wake events armed prior to an S5 transition. Some existing platforms do not reliably transition to S5 with wake events enabled (for example, the platform may immediately generate a spurious wake event after completing the S5 transition). This flag allows OSPM to differentiate correctly functioning platforms from platforms with this type of errata.
FORCE_ APIC_CLUSTER_MODEL	1	18	A one indicates that all local APICs must be configured for the cluster destination model when delivering interrupts in logical mode. If this bit is set, then logical mode interrupt delivery operation may be undefined until OSPM has moved all local APICs to the cluster model. Note that the cluster destination model doesn't apply to Itanium processor local SAPICs. This bit is intended for xAPIC based machines that require the cluster destination model even when 8 or fewer local APICs are present in the machine.
FORCE_APIC_PHYSICAL_DESTINATION_MODE	1	19	A one indicates that all local xAPICs must be configured for physical destination mode. If this bit is set, interrupt delivery operation in logical destination mode is undefined. On machines that contain fewer than 8 local xAPICs or that do not use the xAPIC architecture, this bit is ignored.
Reserved	12	20

5.2.9.1   Preferred PM Profile System Types
The following descriptions of preferred power management profile system types are to be used as a guide for setting the Preferred_PM_Profile field in the FADT. OSPM can use this field to set default power management policy parameters during OS installation.
Desktop. A single user, full featured, stationary computing device that resides on or near an individual's work area. Most often contains one processor. Must be connected to AC power to function. This device is used to perform work that is considered mainstream corporate or home computing (for example, word processing, Internet browsing, spreadsheets, and so on).
Mobile. A single-user, full-featured, portable computing device that is capable of running on batteries or other power storage devices to perform its normal functions. Most often contains one processor. This device performs the same task set as a desktop. However it may have limitations dues to its size, thermal requirements, and/or power source life.
Workstation. A single-user, full-featured, stationary computing device that resides on or near an individual's work area. Often contains more than one processor. Must be connected to AC power to function. This device is used to perform large quantities of computations in support of such work as CAD/CAM and other graphics-intensive applications.
Enterprise Server. A multi-user, stationary computing device that frequently resides in a separate, often specially designed, room. Will almost always contain more than one processor. Must be connected to AC power to function. This device is used to support large-scale networking, database, communications, or financial operations within a corporation or government.
SOHO Server. A multi-user, stationary computing device that frequently resides in a separate area or room in a small or home office. May contain more than one processor. Must be connected to AC power to function. This device is generally used to support all of the networking, database, communications, and financial operations of a small office or home office.
Appliance PC. A device specifically designed to operate in a low-noise, high-availability environment such as a consumer's living rooms or family room. Most often contains one processor. This category also includes home Internet gateways, Web pads, set top boxes and other devices that support ACPI. Must be connected to AC power to function. Normally they are sealed case style and may only perform a subset of the tasks normally associated with today's personal computers.
Performance Server. A multi-user stationary computing device that frequently resides in a separate, often specially designed room. Will often contain more than one processor. Must be connected to AC power to function. This device is used in an environment where power savings features are willing to be sacrificed for better performance and quicker responsiveness.
5.2.9.2   System Type Attributes
This set of flags is used by the OS to assist in determining assumptions about power and device management. These flags are read at boot time and are used to make decisions about power management and device settings. For example, a system that has the SEALED_CASE bit set may take a very aggressive low noise policy toward thermal management. In another example an OS might not load video, keyboard or mouse drivers on a HEADLESS system.
5.2.9.3   IA-PC Boot Architecture Flags
This set of flags is used by an OS to guide the assumptions it can make in initializing hardware on IA-PC platforms. These flags are used by an OS at boot time (before the OS is capable of providing an operating environment suitable for parsing the ACPI namespace) to determine the code paths to take during boot. In IA-PC platforms with reduced legacy hardware, the OS can skip code paths for legacy devices if none are present. For example, if there are no ISA devices, an OS could skip code that assumes the presence of these devices and their associated resources. These flags are used independently of the ACPI namespace. The presence of other devices must be described in the ACPI namespace as specified in section 6, "Configuration." These flags pertain only to IA-PC platforms. On other system architectures, the entire field should be set to 0.
Table 5-11   Fixed ACPI Description Table Boot Architecture Flags

BOOT_ARCH	Bit length	Bit offset	Description
LEGACY_DEVICES	1	0	If set, indicates that the motherboard supports user-visible devices on the LPC or ISA bus. User-visible devices are devices that have end-user accessible connectors (for example, LPT port), or devices for which the OS must load a device driver so that an end-user application can use a device. If clear, the OS may assume there are no such devices and that all devices in the system can be detected exclusively via industry standard device enumeration mechanisms (including the ACPI namespace).
8042	1	1	If set, indicates that the motherboard contains support for a port 60 and 64 based keyboard controller, usually implemented as an 8042 or equivalent micro-controller.
VGA Not Present	1	2	If set, indicates to OSPM that it must not blindly probe the VGA hardware (that responds to MMIO addresses A0000h-BFFFFh and IO ports 3B0h-3BBh and 3C0h-3DFh) that may cause machine check on this system. If clear, indicates to OSPM that it is safe to probe the VGA hardware..
MSI Not Supported	1	3	If set, indicates to OSPM that it must not enable Message Signaled Interrupts (MSI) on this platform.
PCIe ASPM Controls	1	4	If set, indicates to OSPM that it must not enable OSPM ASPM control on this platform.
Reserved	11	5	Must be 0.

5.2.10 Firmware ACPI Control Structure (FACS)
The Firmware ACPI Control Structure (FACS) is a structure in read/write memory that the BIOS reserves for ACPI usage. This structure is passed to an ACPI-compatible OS using the FADT. For more information about the FADT FIRMWARE_CTRL field, see section 5.2.9, "Fixed ACPI Description Table (FADT)."
The BIOS aligns the FACS on a 64-byte boundary anywhere within the system's memory address space. The memory where the FACS structure resides must not be reported as system AddressRangeMemory in the system address map. For example, the E820 address map reporting interface would report the region as AddressRangeReserved. For more information about system address map reporting interfaces, see section 14, "System Address Map Interfaces."
Table 5-12 Firmware ACPI Control Structure (FACS)

Field	Byte Length	Byte Offset	Description
Signature	4	0	'FACS'
Length	4	4	Length, in bytes, of the entire Firmware ACPI Control Structure. This value is 64 bytes or larger.
Hardware Signature	4	8	The value of the system's "hardware signature" at last boot. This value is calculated by the BIOS on a best effort basis to indicate the base hardware configuration of the system such that different base hardware configurations can have different hardware signature values. OSPM uses this information in waking from an S4 state, by comparing the current hardware signature to the signature values saved in the non-volatile sleep image the values are not the same, OSPM assumes that the saved non-volatile image is from a different hardware configuration and cannot be restored.
Firmware_Waking_ Vector	4	12	This field is superseded by the X_Firmware_Waking_Vector field. The 32-bit address field where OSPM puts its waking vector. Before transitioning the system into a global sleeping state, OSPM fills in this field with the physical memory address of an OS-specific wake function. During POST, the platform firmware first checks if the value of the X_Firmware_Waking_Vector field is non-zero and if so transfers control to OSPM as outlined in the X_Firmware_Waking_vector field description below the X_Firmware_Waking_Vector field is zero then the platform firmware checks the value of this field and if it is non-zero, transfers control to the specified address. On PCs, the wake function address is in memory below 1 MB and the control is transferred while in real mode. OSPM's wake function restores the processors' context. For IA-PC platforms, the following example shows the relationship between the physical address in the Firmware Waking Vector and the real mode address the BIOS jumps to. If, for example, the physical address is 0x12345, then the BIOS must jump to real mode address 0x1234:0x0005. In general this relationship is Real-mode address = Physical address>>4 : Physical address and 0x000F Notice that on IA-PC platforms, A20 must be enabled when the BIOS jumps to the real mode address derived from the physical address stored in the Firmware Waking Vector.

Table 5-12 Firmware ACPI Control Structure (FACS) (continued)

Field	Byte Length	Byte Offset	Description
Global_Lock	4	16	This field contains the Global Lock used to synchronize access to shared hardware resources between the OSPM environment and an external controller environment (for example, the SMI environment). This lock is owned exclusively by either OSPM or the firmware at any one time. When ownership of the lock is attempted, it might be busy, in which case the requesting environment exits and waits for the signal that the lock has been released. For example, the Global Lock can be used to protect an embedded controller interface such that only OSPM or the firmware will access the embedded controller interface at any one time. See section 5.2.10.1, "Global Lock," for more information on acquiring and releasing the Global Lock.
Flags	4	20	Firmware control structure flags. See Table 5-13 for a description of this field.
X_Firmware_Waking_Vector	8	24	64-bit physical address of OSPM's Waking Vector. Before transitioning the system into a global sleeping state, OSPM fills in this field with the physical memory address of an OS-specific wake function. During POST, the platform firmware checks if the value of this field is non-zero and if so transfers control to OSPM by jumping to this address. Prior to transferring control, the execution environment must be configured as follows: Memory address translation / paging and interrupts must be disabled. For IA 32-bit platforms, a 4GB flat address space for all segment registers and EFLAGS.IF set to 0. For 64-bit Itanium^TM-based platforms, the processor must have psr.i, psr.it, psr.dt, and psr.rt set to 0. See the Intel� Itanium^TM Architecture Software Developer's Manual for more information. If this field is zero, the platform firmware checks the Firmware_Waking_Vector field as outlined above.
Version	1	32	1–Version of this table
Reserved	31	33	This value is zero.

Table 5-13 Firmware Control Structure Feature Flags

FACS – Flag	Bit Length	Bit Offset	Description
S4BIOS_F	1	0	Indicates whether the platform supports S4BIOS_REQ S4BIOS_REQ is not supported, OSPM must be able to save and restore the memory state in order to use the S4 state.
Reserved	31	1	The value is zero.

5.2.10.1 Global Lock
The purpose of the ACPI Global Lock is to provide mutual exclusion between the host OS and the ROM BIOS. The Global Lock is a 32-bit (DWORD) value in read/write memory located within the FACS and is accessed and updated by both the OS environment and the SMI environment in a defined manner to provide an exclusive lock. Note: this is not a pointer to the Global Lock, it is the actual style='font-style:normal'> memory location of the lock. The FACS and Global Lock may be located anywhere in physical memory.
By convention, this lock is used to ensure that while one environment is accessing some hardware, the other environment is not. By this convention, when ownership of the lock fails because the other environment owns it, the requesting environment sets a "pending" state within the lock, exits its attempt to acquire the lock, and waits for the owning environment to signal that the lock has been released before attempting to acquire the lock again. When releasing the lock, if the pending bit in the lock is set after the lock is released, a signal is sent via an interrupt mechanism to the other environment to inform it that the lock has been released. During interrupt handling for the "lock released" event within the corresponding environment, if the lock ownership were still desired an attempt to acquire the lock would be made. If ownership is not acquired, then the environment must again set "pending" and wait for another "lock release" signal.
The table below shows the encoding of the Global Lock DWORD in memory.
Table 5-14 Global Lock Structure within the FACS

Field	Bit Length	Bit Offset	Description
Pending	1	0	Non-zero indicates that a request for ownership of the Global Lock is pending.
Owned	1	1	Non-zero indicates that the Global Lock is Owned.
Reserved	30	2	Reserved for future use.

The following code sequence is used by both OSPM and the firmware to acquire ownership of the Global Lock. If non-zero is returned by the function, the caller has been granted ownership of the Global Lock and can proceed. If zero is returned by the function, the caller has not been granted ownership of the Global Lock, the "pending" bit has been set, and the caller must wait until it is signaled by an interrupt event that the lock is available before attempting to acquire access again.
Note: In the examples that follow, the "GlobalLock" variable is a pointer that has been previously initialized to point to the 32-bit Global Lock location within the FACS.

AcquireGlobalLock:
           mov    ecx, GlobalLock          ; ecx = Address of Global Lock in FACS
acq10:     mov    eax, [ecx]               ;Get current value of Global Lock

           mov    edx, eax
           and    edx, not 1               ;Clear pending bit
           bts    edx, 1                   ;Check and set owner bit
           adc    edx, 0                   ;If owned, set pending bit

           lock cmpxchg dword ptr[ecx], edx    ; Attempt to set new value
           jnz short acq10                 ;If not set, try again

           cmp    dl, 3                    ;Was it acquired or marked pending?
           sbb    eax, eax                 ;acquired = -1, pending = 0

           ret

The following code sequence is used by OSPM and the firmware to release ownership of the Global Lock. If non-zero is returned, the caller must raise the appropriate event to the other environment to signal that the Global Lock is now free. Depending on the environment, this signaling is done by setting the either the GBL_RLS or BIOS_RLS within their respective hardware register spaces. This signal only occurs when the other environment attempted to acquire ownership while the lock was owned.

ReleaseGlobalLock:
           mov    ecx, GlobalLock          ; ecx = Address of Global Lock in FACS
rel10:     mov    eax, [ecx]           ; Get current value of Global Lock

           mov    edx, eax
           and    edx, not 03h             ; Clear owner and pending field

           lock cmpxchg dword ptr[ecx], edx    ; Attempt to set it
           jnz short rel10                     ;If not set, try again

           and    eax, 1                   ;Was pending set?

; If one is returned (we were pending) the caller must signal that the
; lock has been released using either GBL_RLS or BIOS_RLS as appropriate

           ret

Although using the Global Lock allows various hardware resources to be shared, it is important to notice that its usage when there is ownership contention could entail a significant amount of system overhead as well as waits of an indeterminate amount of time to acquire ownership of the Global Lock. For this reason, implementations should try to design the hardware to keep the required usage of the Global Lock to a minimum.
The Global Lock is required whenever a logical register in the hardware is shared. For example, if bit 0 is used by ACPI (OSPM) and bit 1 of the same register is used by SMI, then access to that register needs to be protected under the Global Lock, ensuring that the register's contents do not change from underneath one environment while the other is making changes to it. Similarly if the entire register is shared, as the case might be for the embedded controller interface, access to the register needs to be protected under the Global Lock.
5.2.11   Definition Blocks
A Definition Block consists of data in AML format (see section 5.4 "Definition Block Encoding") and contains information about hardware implementation details in the form of AML objects that contain data, AML code, or other AML objects. The top-level organization of this information after a definition block is loaded is name-tagged in a hierarchical namespace.
OSPM "loads" or "unloads" an entire definition block as a logical unit. OSPM will load a definition block either as a result of executing the AML Load() or LoadTable() operator or encountering a table definition during initialization. During initialization, OSPM loads the Differentiated System Description Table (DSDT), which contains the Differentiated Definition Block, using the DSDT pointer retrieved from the FADT. OSPM will load other definition blocks during initialization as a result of encountering Secondary System Description Table (SSDT) definitions in the RSDT/XSDT. The DSDT and SSDT are described in the following sections.
As mentioned, the AML Load() and LoadTable() operators make it possible for a Definition Block to load other Definition Blocks, either statically or dynamically, where they in turn can either define new system attributes or, in some cases, build on prior definitions. Although this gives the hardware the ability to vary widely in implementation, it also confines it to reasonable boundaries. In some cases, the Definition Block format can describe only specific and well-understood variances. In other cases, it permits implementations to be expressible only by means of a specified set of "built in" operators. For example, the Definition Block has built in operators for I/O space.
In theory, it might be possible to define something like PCI configuration space in a Definition Block by building it from I/O space, but that is not the goal of the definition block. Such a space is usually defined as a "built in" operator.
Some AML operators perform simple functions, and others encompass complex functions. The power of the Definition block comes from its ability to allow these operations to be glued together in numerous ways, to provide functionality to OSPM.
The AML operators defined in this specification are intended to allow many useful hardware designs to be easily expressed, not to allow all hardware designs to be expressed.
Note: To accommodate addressing beyond 32 bits, the integer type was expanded to 64 bits in ACPI 2.0, see section 17.2.5, "ASL Data Types". Existing ACPI definition block implementations may contain an inherent assumption of a 32-bit integer width. Therefore, to maintain backwards compatibility, OSPM uses the Revision field, in the header portion of system description tables containing Definition Blocks, to determine whether integers declared within the Definition Block are to be evaluated as 32-bit or 64-bit values. A Revision field value greater than or equal to 2 signifies that integers declared within the Definition Block are to be evaluated as 64-bit values. The ASL writer specifies the value for the Definition Block table header's Revision field via the ASL DefinitionBlock's ComplianceRevision field. See section 17.5.26, "DefinitionBlock (Declare Definition Block)", for more information. It is the responsibility of the ASL writer to ensure the Definition Block's compatibility with the corresponding integer width when setting the ComplianceRevision field.

5.2.11.1 Differentiated System Description Table (DSDT)
The Differentiated System Description Table (DSDT) is part of the system fixed description. The DSDT is comprised of a system description table header followed by data in Definition Block format. This Definition Block is like all other Definition Blocks, with the exception that it cannot be unloaded. See section 5.2.11, "Definition Blocks," for a description of Definition Blocks. During initialization, OSPM finds the pointer to the DSDT in the Fixed ACPI Description Table (using the FADT's DSDT or X_DSDT fields) and then loads the DSDT to create the ACPI Namespace.
Table 5-15 Differentiated System Description Table Fields (DSDT)

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'DSDT' Signature for the Differentiated System Description Table.
Length	4	4	Length, in bytes, of the entire DSDT (including the header).
Revision	1	8	2
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	The manufacture model ID.
OEM Revision	4	24	OEM revision of DSDT for supplied OEM Table ID.
Creator ID	4	28	Vendor ID for the ASL Compiler.
Creator Revision	4	32	Revision number of the ASL Compiler.
Definition Block	n	36	n bytes of AML code (see section 5.4, "Definition Block Encoding")

5.2.11.2 Secondary System Description Table (SSDT)
Secondary System Description Tables (SSDT) are a continuation of the DSDT. The SSDT is comprised of a system description table header followed by data in Definition Block format. There can be multiple SSDTs present. After OSPM loads the DSDT to create the ACPI Namespace, each secondary system description table listed in the RSDT/XSDT with a unique OEM Table ID is loaded. Note: Additional tables can only add data; they cannot overwrite data from previous tables.
This allows the OEM to provide the base support in one table and add smaller system options in other tables. For example, the OEM might put dynamic object definitions into a secondary table such that the firmware can construct the dynamic information at boot without needing to edit the static DSDT. A SSDT can only rely on the DSDT being loaded prior to it.
Table 5-16 Secondary System Description Table Fields (SSDT)

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'SSDT' Signature for the Secondary System Description Table.
Length	4	4	Length, in bytes, of the entire SSDT (including the header).
Revision	1	8	2
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	The manufacture model ID.
OEM Revision	4	24	OEM revision of DSDT for supplied OEM Table ID.
Creator ID	4	28	Vendor ID for the ASL Compiler.
Creator Revision	4	32	Revision number of the ASL Compiler.
Definition Block	n	36	n bytes of AML code (see section 5.4 , "Definition Block Encoding")

5.2.11.3   Persistent System Description Table (PSDT)
The table signature, "PSDT" refers to the Persistent System Description Table (PSDT) defined in the ACPI 1.0 specification. The PSDT was judged to provide no specific benefit and as such has been deleted from this version of the ACPI specification. OSPM will evaluate a table with the "PSDT" signature in like manner to the evaluation of an SSDT as described in section 5.2.11.2, "Secondary System Description Table."
5.2.11.4   Multiple APIC Description Table (MADT)
The ACPI interrupt model describes all interrupts for the entire system in a uniform interrupt model implementation. Supported interrupt models include the PC-AT–compatible dual 8259 interrupt controller and, for Intel processor-based systems, the Intel Advanced Programmable Interrupt Controller (APIC) and Intel Streamlined Advanced Programmable Interrupt Controller (SAPIC). The choice of the interrupt model(s) to support is up to the platform designer. The interrupt model cannot be dynamically changed by the system firmware; OSPM will choose which model to use and install support for that model at the time of installation. If a platform supports both models, an OS will install support for one model or the other; it will not mix models. Multi-boot capability is a feature in many modern operating systems. This means that a system may have multiple operating systems or multiple instances of an OS installed at any one time. Platform designers must allow for this.
This section describes the format of the Multiple APIC Description Table (MADT), which provides OSPM with information necessary for operation on systems with APIC or SAPIC implementations.
ACPI represents all interrupts as "flat" values known as global system interrupts. Therefore to support APICs or SAPICs on an ACPI-enabled system, each used APIC or SAPIC interrupt input must be mapped to the global system interrupt value used by ACPI. See Section 5.2.12. Global System Interrupts," for a description of Global System Interrupts.
Additional support is required to handle various multi-processor functions that APIC or SAPIC implementations might support (for example, identifying each processor's local APIC ID).
All addresses in the MADT are processor-relative physical addresses.
Table 5-17   Multiple APIC Description Table (MADT) Format

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'APIC' Signature for the Multiple APIC Description Table.
Length	4	4	Length, in bytes, of the entire MADT.
Revision	1	8	2
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	For the MADT, the table ID is the manufacturer model ID.
OEM Revision	4	24	OEM revision of MADT for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler.
Local APIC Address	4	36	The 32-bit physical address at which each processor can access its local APIC.
Flags	4	40	Multiple APIC flags. See Table 5-18 for a description of this field.
APIC Structure[n]	—	44	A list of APIC structures for this implementation. This list will contain all of the I/O APIC, I/O SAPIC, Local APIC, Local SAPIC, Interrupt Source Override, Non-maskable Interrupt Source, Local APIC NMI Source, Local APIC Address Override, and Platform Interrupt Sources structures needed to support this platform. These structures are described in the following sections.

Table 5-18 Multiple APIC Flags

Multiple APIC Flags	Bit Length	Bit Offset	Description
PCAT_COMPAT	1	0	A one indicates that the system also has a PC-AT-compatible dual-8259 setup. The 8259 vectors must be disabled (that is, masked) when enabling the ACPI APIC operation.
Reserved	31	1	This value is zero.

Immediately after the Flags value in the MADT is a list of APIC structures that declare the APIC features of the machine. The first byte of each structure declares the type of that structure and the second byte declares the length of that structure.
Table 5-19 APIC Structure Types

Value	Description
0	Processor Local APIC
1	I/O APIC
2	Interrupt Source Override
3	Non-maskable Interrupt Source (NMI)
4	Local APIC NMI Structure
5	Local APIC Address Override Structure
6	I/O SAPIC
7	Local SAPIC
8	Platform Interrupt Sources
9-127	Reserved. OSPM skips structures of the reserved type.
128-255	Reserved for OEM use

5.2.11.4.1 MADT Processor Local APIC / SAPIC Structure Entry Order
OSPM implementations may limit the number of supported processors on multi-processor platforms. OSPM executes on the boot processor to initialize the platform including other processors. To ensure that the boot processor is supported post initialization, two guidelines should be followed. The first is that OSPM should initialize processors in the order that they appear in the MADT. The second is that platform firmware should list the boot processor as the first processor entry in the MADT.
The advent of multi-threaded processors yielded multiple logical processors executing on common processor hardware. ACPI defines logical processors in an identical manner as physical processors. To ensure that non multi-threading aware OSPM implementations realize optimal performance on platforms containing multi-threaded processors, two guidelines should be followed. The first is the same as above , that is, OSPM should initialize processors in the order that they appear in the MADT. The second is that platform firmware should list the first logical processor of each of the indvdiual multi-threaded processors in the MADT before listing any of the second logical processors. This approach should be used for all successive logical processors.
Failure of OSPM implementations and platform firmware to abide by these guidelines can result in both unpredictable and non optimal platform operation.
5.2.11.5 Processor Local APIC
When using the APIC interrupt model, each processor in the system is required to have a Processor Local APIC record and an ACPI Processor object. OSPM does not expect the information provided in this table to be updated if the processor information changes during the lifespan of an OS boot. While in the sleeping state, processors are not allowed to be added, removed, nor can their APIC ID or Flags change. When a processor is not present, the Processor Local APIC information is either not reported or flagged as disabled.
Table 5-20 Processor Local APIC Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	0 Processor Local APIC structure
Length	1	1	8
ACPI Processor ID	1	2	The ProcessorId for which this processor is listed in the ACPI Processor declaration operator. For a definition of the Processor operator, see section 17.5.93, "Processor (Declare Processor)."
APIC ID	1	3	The processor's local APIC ID.
Flags	4	4	Local APIC flags. See Table 5-21 for a description of this field.

Table 5-21 Local APIC Flags

LocalAPIC Flags	Bit Length	Bit Offset	Description
Enabled	1	0	If zero, this processor is unusable, and the operating system support will not attempt to use it.
Reserved	31	1	Must be zero.

5.2.11.6 I/O APIC
In an APIC implementation, there are one or more I/O APICs. Each I/O APIC has a series of interrupt inputs, referred to as INTIn, where the value of n style='font-style:normal'> is from 0 to the number of the last interrupt input on the I/O APIC. The I/O APIC structure declares which global system interrupts are uniquely associated with the I/O APIC interrupt inputs. There is one I/O APIC structure for each I/O APIC in the system. For more information on global system interrupts see Section 5.2.12, "Global System Interrupts."
Table 5-22 I/O APIC Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	1 I/O APIC structure
Length	1	1	12
I/O APIC ID	1	2	The I/O APIC's ID.
Reserved	1	3	0
I/O APIC Address	4	4	The 32-bit physical address to access this I/O APIC. Each I/O APIC resides at a unique address.
Global System Interrupt Base	4	8	The global system interrupt number where this I/O APIC's interrupt inputs start. The number of interrupt inputs is determined by the I/O APIC's Max Redir Entry register.

5.2.11.7   Platforms with APIC and Dual 8259 Support
Systems that support both APIC and dual 8259 interrupt models must map global system interrupts 0-15 to the 8259 IRQs 0-15, except where Interrupt Source Overrides are provided (see section 5.2.10.8, "Interrupt Source Overrides"). This means that I/O APIC interrupt inputs 0-15 must be mapped to global system interrupts 0-15 and have identical sources as the 8259 IRQs 0-15 unless overrides are used. This allows a platform to support OSPM implementations that use the APIC model as well as OSPM implementations that use the 8259 model (OSPM will only use one model; it will not mix models).
When OSPM supports the 8259 model, it will assume that all interrupt descriptors reporting global system interrupts 0-15 correspond to 8259 IRQs. In the 8259 model all global system interrupts greater than 15 are ignored. If OSPM implements APIC support, it will enable the APIC as described by the APIC specification and will use all reported global system interrupts that fall within the limits of the interrupt inputs defined by the I/O APIC structures. For more information on hardware resource configuration see section 6, "Configuration."
5.2.11.8   Interrupt Source Overrides
Interrupt Source Overrides are necessary to describe variances between the IA-PC standard dual 8259 interrupt definition and the platform's implementation.
It is assumed that the ISA interrupts will be identity-mapped into the first I/O APIC sources. Most existing APIC designs, however, will contain at least one exception to this assumption. The Interrupt Source Override Structure is provided in order to describe these exceptions is not necessary to provide an Interrupt Source Override for every ISA interrupt. Only those that are not identity-mapped onto the APIC interrupt inputs need be described.
Note: This specification only supports overriding ISA interrupt sources.
For example, if your machine has the ISA Programmable Interrupt Timer (PIT) connected to ISA IRQ 0, but in APIC mode, it is connected to I/O APIC interrupt input 2, then you would need an Interrupt Source Override where the source entry is '0' and the Global System Interrupt is '2.'
Table 5-23   Interrupt Source Override Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	2 Interrupt Source Override
Length	1	1	10
Bus	1	2	0 Constant, meaning ISA
Source	1	3	Bus-relative interrupt source (IRQ)
Global System Interrupt	4	4	The Global System Interrupt that this bus-relative interrupt source will signal.
Flags	2	8	MPS INTI flags. See Table 5-24 for a description of this field.

The MPS INTI flags listed in Table 5-24 are identical to the flags used in Table 4-10 of the MPS version 1.4 specifications Polarity flags are the PO bits and the Trigger Mode flags are the EL bits.
Table 5-24 MPS INTI Flags

Local APIC - Flags	Bit Length	Bit Offset	Description
Polarity	2	0	Polarity of the APIC I/O input signals: 00 Conforms to the specifications of the bus (For example, EISA is active-low for level-triggered interrupts) 01 Active high 10 Reserved 11 Active low
Trigger Mode	2	2	Trigger mode of the APIC I/O Input signals: 00 Conforms to specifications of the bus (For example, ISA is edge-triggered) 01 Edge-triggered 10 Reserved 11 Level-triggered
Reserved	12	4	Must be zero.

Interrupt Source Overrides are also necessary when an identity mapped interrupt input has a non-standard polarity.
Note: You must have an interrupt source override entry for the IRQ mapped to the SCI interrupt if this IRQ is not identity mapped. This entry will override the value in SCI_INT in FADT. For example, if SCI is connected to IRQ 9 in PIC mode and IRQ 9 is connected to INTIN11 in APIC mode, you should have 9 in SCI_INT in the FADT and an interrupt source override entry mapping IRQ 9 to INTIN11.
5.2.11.9 Non-Maskable Interrupt Sources (NMIs)

This structure allows a platform designer to specify which I/O (S)APIC interrupt inputs should be enabled as non-maskable. Any source that is non-maskable will not be available for use by devices.
Table 5-25 Non-maskable Source Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	3 NMI
Length	1	1	8
Flags	2	2	Same as MPS INTI flags
Global System Interrupt	4	4	The Global System Interrupt that this NMI will signal.

5.2.11.10 Local APIC NMI
This structure describes the Local APIC interrupt input (LINTn) that NMI is connected to for each of the processors in the system where such a connection exists. This information is needed by OSPM to enable the appropriate local APIC entry.
Each Local APIC NMI connection requires a separate Local APIC NMI structure. For example, if the platform has 4 processors with ID 0-3 and NMI is connected LINT1 for processor 3 and 2, two Local APIC NMI entries would be needed in the MADT.
Table 5-26 Local APIC NMI Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	4 Local APIC NMI Structure
Length	1	1	6
ACPI Processor ID	1	2	Processor ID corresponding to the ID listed in the processor object. A value of 0xFF signifies that this applies to all processors in the machine.
Flags	2	3	MPS INTI flags. See Table 5-24 for a description of this field.
Local APIC LINT#	1	5	Local APIC interrupt input LINTn to which NMI is connected.

5.2.11.11 Local APIC Address Override Structure
This optional structure supports 64-bit systems by providing an override of the physical address of the local APIC in the MADT'stable header, which is defined as a 32-bit field.
If defined, OSPM must use the address specified in this structure for all local APICs (and local SAPICs), rather than the address contained in the MADT's table header. Only one Local APIC Address Override Structure may be defined.
Table 5-27 Local APIC Address Override Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	5 Local APIC Address Override Structure
Length	1	1	12
Reserved	2	2	Reserved (must be set to zero)
Local APIC Address	8	4	Physical address of Local APIC. For Itanium^TM-based systems, this field contains the starting address of the Processor Interrupt Block. See the Intel� Itanium^TM Architecture Software Developer's Manual for more information.

5.2.11.12 I/O SAPIC Structure
The I/O SAPIC structure is very similar to the I/O APIC structure. If both I/O APIC and I/O SAPIC structures exist for a specific APIC ID, the information in the I/O SAPIC structure must be used.
The I/O SAPIC structure uses the I/O_APIC_ID field as defined in the I/O APIC table. The Vector_Base field remains unchanged but has been moved. The I/O APIC address has been deleted. A new address and reserved field have been added.
Table 5-28 I/O SAPIC Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	6 I/O SAPIC Structure
Length	1	1	16
I/O APIC ID	1	2	I/O SAPIC ID
Reserved	1	3	Reserved (must be zero)
Global System Interrupt Base	4	4	The global system interrupt number where this I/O SAPIC's interrupt inputs start. The number of interrupt inputs is determined by the I/O SAPIC's Max Redir Entry register.
I/O SAPIC Address	8	8	The 64-bit physical address to access this I/O SAPIC. Each I/O SAPIC resides at a unique address.

If defined, OSPM must use the information contained in the I/O SAPIC structure instead of the information from the I/O APIC structure.
If both I/O APIC and an I/O SAPIC structures exist in an MADT, the OEM/BIOS writer must prevent "mixing" I/O APIC and I/O SAPIC addresses. This is done by ensuring that there are at least as many I/O SAPIC structures as I/O APIC structures and that every I/O APIC structure has a corresponding I/O SAPIC structure (same APIC ID).
5.2.11.13 Local SAPIC Structure
The Processor local SAPIC structure is very similar to the processor local APIC structure. When using the SAPIC interrupt model, each processor in the system is required to have a Processor Local SAPIC record and an ACPI Processor object. OSPM does not expect the information provided in this table to be updated if the processor information changes during the lifespan of an OS boot. While in the sleeping state, processors are not allowed to be added, removed, nor can their SAPIC ID or Flags change. When a processor is not present, the Processor Local SAPIC information is either not reported or flagged as disabled.
Table 5-29 Processor Local SAPIC Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	7 Processor Local SAPIC structure
Length	1	1	Length of the Local SAPIC Structure in bytes.
ACPI Processor ID	1	2	OSPM associates the Local SAPIC Structure with a processor object declared in the namespace using the Processor statement by matching the processor object's ProcessorID value with this field. For a definition of the Processor object, see section 17.5.93, "Processor (Declare Processor)."
Local SAPIC ID	1	3	The processor's local SAPIC ID
Local SAPIC EID	1	4	The processor's local SAPIC EID
Reserved	3	5	Reserved (must be set to zero)
Flags	4	8	Local SAPIC flags. See Table 5-21 for a description of this field.
ACPI Processor UID Value	4	12	OSPM associates the Local SAPIC Structure with a processor object declared in the namespace using the Device statement, when the _UID child object of the processor device evaluates to a numeric value, by matching the numeric value with this field.
ACPI Processor UID String	>=1	16	OSPM associates the Local SAPIC Structure with a processor object declared in the namespace using the Device statement, when the _UID child object of the processor device evaluates to a string, by matching the string with this field. This value is stored as a null-terminated ASCII string.

5.2.11.14 Platform Interrupt Source Structure
The Platform Interrupt Source structure is used to communicate which I/O SAPIC interrupt inputs are connected to the platform interrupt sources.
Platform Management Interrupts (PMIs) are used to invoke platform firmware to handle various events (similar to SMI in IA-32) Intel� Itanium^TM architecture permits the I/O SAPIC to send a vector value in the interrupt message of the PMI type. This value is specified in the I/O SAPIC Vector field of the Platform Interrupt Sources Structure.
INIT messages cause processors to soft reset.

If a platform can generate an interrupt after correcting platform errors (e.g., single bit error correction), the interrupt input line used to signal such corrected errors is specified by the Global System Interrupt field in the following table. Some systems may restrict the retrieval of corrected platform error information to a specific processor. In such cases, the firmware indicates the processor that can retrieve the corrected platform error information through the Processor ID and EID fields in the structure below. OSPM is required to program the I/O SAPIC redirection table entries with the Processor ID, EID values specified by the ACPI system firmware platforms where the retrieval of corrected platform error information can be performed on any processor, the firmware indicates this capability by setting the CPEI Processor Override flag in the Platform Interrupt Source Flags field of the structure below. If the CPEI Processor Override Flag is set, OSPM uses the processor specified by Processor ID, and EID fields of the structure below only as a target processor hint and the error retrieval can be performed on any processor in the system. However, firmware is required to specify valid values in Processor ID, EID fields to ensure backward compatibility.
If the CPEI Processor Override flag is clear, OSPM may reject a ejection request for the processor that is targeted for the corrected platform error interrupt. If the CPEI Processor Override flag is set, OSPM can retarget the corrected platform error interrupt to a different processor when the target processor is ejected.
Note that the _MAT object can return a buffer containing Platform Interrupt Source Structure entries. It is allowed for such an entry to refer to a Global System Interrupt that is already specified by a Platform Interrupt Source Structure provided through the static MADT table, provided the value of platform interrupt source flags are identical.
Refer to the Itanium^TM Processor Family System Abstraction Layer (SAL) Specification for details on handling the Corrected Platform Error Interrupt.
Table 5-30 Platform Interrupt Sources Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	8 Platform Interrupt Source structure
Length	1	1	16
Flags	2	2	MPS INTI flags. See Table 5-24 for a description of this field.
Interrupt Type	1	4	1 PMI 2 INIT 3 Corrected Platform Error Interrupt All other values are reserved.
Processor ID	1	5	Processor ID of destination.
Processor EID	1	6	Processor EID of destination.
I/O SAPIC Vector	1	7	Value that OSPM must use to program the vector field of the I/O SAPIC redirection table entry for entries with the PMI interrupt type.
Global System Interrupt	4	8	The Global System Interrupt that this platform interrupt will signal.
Platform Interrupt Source Flags	4	12	Platform Interrupt Source Flags. See Table 5-31 for a description of this field

Table 5-31 Platform Interrupt Source Flags

Platform Interrupt Source Flags	Bit Length	Bit Offset	Description
CPEI Processor Override	1	0	When set, indicates that retrieval of error information is allowed from any processor and OSPM is to use the information provided by the processor ID, EID fields of the Platform Interrupt Source Structure (Table 5-30) as a target processor hint.
Reserved	31	1	Must be zero.

Figure 5-3 APIC–Global System Interrupts
5.2.12 Global System Interrupts
Global System Interrupts can be thought of as ACPI Plug and Play IRQ numbers. They are used to virtualize interrupts in tables and in ASL methods that perform resource allocation of interrupts. Do not confuse global system interrupts with ISA IRQs although in the case of the IA-PC 8259 interrupts they correspond in a one-to-one fashion.
There are two interrupt models used in ACPI-enabled systems.
The first model is the APIC model. In the APIC model, the number of interrupt inputs supported by each I/O APIC can vary. OSPM determines the mapping of the Global System Interrupts by determining how many interrupt inputs each I/O APIC supports and by determining the global system interrupt base for each I/O APIC as specified by the I/O APIC Structure. OSPM determines the number of interrupt inputs by reading the Max Redirection register from the I/O APIC. The global system interrupts mapped to that I/O APIC begin at the global system interrupt base and extending through the number of interrupts specified in the Max Redirection register. This mapping is depicted in Figure 5-3.
There is exactly one I/O APIC structure per I/O APIC in the system.

Figure 5-4 8259–Global System Interrupts

The other interrupt model is the standard AT style mentioned above which uses ISA IRQs attached to a master slave pair of 8259 PICs. The system vectors correspond to the ISA IRQs. The ISA IRQs and their mappings to the 8259 pair are part of the AT standard and are well defined. This mapping is depicted in Figure 5-4.

5.2.13 Smart Battery Table (SBST)
If the platform supports batteries as defined by the Smart Battery Specification 1.0 or 1.1, then an Smart Battery Table (SBST) is present. This table indicates the energy level trip points that the platform requires for placing the system into the specified sleeping state and the suggested energy levels for warning the user to transition the platform into a sleeping state. Notice that while Smart Batteries can report either in current (mA/mAh) or in energy (mW/mWh), OSPM must set them to operate in energy (mW/mWh) mode so that the energy levels specified in the SBST can be used. OSPM uses these tables with the capabilities of the batteries to determine the different trip points. For more precise definitions of these levels, see section 3.9.3, "Battery Gas Gauge."

Table 5-32 Smart Battery Description Table (SBST) Format

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'SBST' Signature for the Smart Battery Description Table.
Length	4	4	Length, in bytes, of the entire SBST
Revision	1	8	1
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	For the SBST, the table ID is the manufacturer model ID.
OEM Revision	4	24	OEM revision of SBST for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler.
Warning Energy Level	4	36	OEM suggested energy level in milliWatt-hours (mWh) at which OSPM warns the user.
Low Energy Level	4	40	OEM suggested platform energy level in mWh at which OSPM will transition the system to a sleeping state.
Critical Energy Level	4	44	OEM suggested platform energy level in mWh at which OSPM performs an emergency shutdown.

5.2.14 Embedded Controller Boot Resources Table (ECDT)
This optional table provides the processor-relative, translated resources of an Embedded Controller. The presence of this table allows OSPM to provide Embedded Controller operation region space access before the namespace has been evaluated. If this table is not provided, the Embedded Controller region space will not be available until the Embedded Controller device in the AML namespace has been discovered and enumerated availability of the region space can be detected by providing a _REG method object underneath the Embedded Controller device.

Table 5-33 Embedded Controller Boot Resources Table Format

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'ECDT' Signature for the Embedded Controller Table.
Length	4	4	Length, in bytes, of the entire Embedded Controller Table
Revision	1	8	1
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID
OEM Table ID	8	16	For the Embedded Controller Table, the table ID is the manufacturer model ID.
OEM Revision	4	24	OEM revision of Embedded Controller Table for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler.
EC_CONTROL	12	36	Contains the processor relative address, represented in Generic Address Structure format, of the Embedded Controller Command/Status register. Note: Only System I/O space and System Memory space are valid for values for Address_Space_ID.
EC_DATA	12	48	Contains the processor-relative address, represented in Generic Address Structure format, of the Embedded Controller Data register. Note: Only System I/O space and System Memory space are valid for values for Address_Space_ID.
UID	4	60	Unique ID–Same as the value returned by the _UID under the device in the namespace that represents this embedded controller.
GPE_BIT	1	64	The bit assignment of the SCI interrupt within the GPEx_STS register of a GPE block described in the FADT that the embedded controller triggers.
EC_ID	Variable	65	ASCII, null terminated, string that contains a fully qualified reference to the name space object that is this embedded controller device (for example, "\\_SB.PCI0.ISA.EC"). Quotes are omitted in the data field.

ACPI OSPM implementations supporting Embedded Controller devices must also support the ECDT. ACPI 1.0 OSPM implementation will not recognize or make use of the ECDT. The following example code shows how to detect whether the Embedded Controller operation regions are available in a manner that is backward compatible with prior versions of ACPI/OSPM.

Device(EC0) {
    Name(REGC,Ones)
    Method(_REG,2) {
       If(Lequal(Arg0, 3)) {
           Store(Arg1, REGC)
       }
    }
}
Method(ECAV,0) {
    If(Lequal(REGC,Ones)) {
       If(LgreaterEqual(_REV,2)) {
           Return(One)
       }
       Else {
           Return(Zero)
        }
        Return(REGC)
    }
}
To detect the availability of the region, call the ECAV method. For example:

If (\_SB.PCI0.EC0.ECAV()) {
    ...regions are available...
}
else {
    ...regions are not available...
}
5.2.15   System Resource Affinity Table (SRAT)
This optional table provides information that allows OSPM to associate processors and memory ranges, including ranges of memory provided by hot-added memory devices, with system localities / proximity domains NUMA platforms, SRAT information enables OSPM to optimally configure the operating system during a point in OS initialization when evaluation of objects in the ACPI Namespace is not yet possible. OSPM evaluates the SRAT only during OS initialization.
Table 5-34   Static Resource Affinity Table Format

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'SRAT'. Signature for the System Resource Affinity Table.
Length	4	4	Length, in bytes, of the entire SRAT. The length implies the number of Entry fields at the end of the table
Revision	1	8	2
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID.
OEM Table ID	8	16	For the System Resource Affinity Table, the table ID is the manufacturer model ID.
OEM Revision	4	24	OEM revision of System Resource Affinity Table for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table.
Creator Revision	4	32	Revision of utility that created the table.
Reserved	4	36	Reserved to be 1 for backward compatibility
Reserved	8	40	Reserved
Static Resource Allocation Structure[n]	---	48	A list of static resource allocation structures for the platform. See section 5.2.15.1,"Processor Local APIC/SAPIC Affinity Structure" and section 5.2.15.2 Memory Affinity Structure".

5.2.15.1 Processor Local APIC/SAPIC Affinity Structure
The Processor Local APIC/SAPIC Affinity structure provides the association between the APIC ID or SAPIC ID/EID of a processor and the proximity domain to which the processor belongs. Table 5-35 provides the details of the Processor Local APIC/SAPIC Affinity structure.
Table 5-35 Processor Local APIC/SAPIC Affinity Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	0 Processor Local APIC/SAPIC Affinity Structure
Length	1	1	16
Proximity Domain [7:0]	1	2	Bit[7:0] of the proximity domain to which the processor belongs.
APIC ID	1	3	The processor local APIC ID.
Flags	4	4	Flags – Processor Local APIC/SAPIC Affinity Structure. See Table 5-36 for a description of this field.
Local SAPIC EID	1	8	The processor local SAPIC EID.
Proximity Domain [31:8]	3	9	Bit[31:8] of the proximity domain to which the processor belongs.
Reserved	4	12	Reserved

Table 5-36 Flags – Processor Local APIC/SAPIC Affinity Structure

Field	Bit Length	Bit Offset	Description
Enabled	1	0	If clear, the OSPM ignores the contents of the Processor Local APIC/SAPIC Affinity Structure. This allows system firmware to populate the SRAT with a static number of structures but only enable them as necessary.
Reserved	31	1	Must be zero.

5.2.15.2 Memory Affinity Structure
The Memory Affinity structure provides the following topology information statically to the operating system:
· The association between a range of memory and the proximity domain to which it belongs
· Information about whether the range of memory can be hot-plugged.
Table 5-37 provides the details of the Memory Affinity structure.
Table 5-37 Memory Affinity Structure

Field	Byte Length	Byte Offset	Description
Type	1	0	1 Memory Affinity Structure
Length	1	1	40
Proximity Domain	4	2	Integer that represents the proximity domain to which the processor belongs
Reserved	2	6	Reserved
Base Address Low	4	8	Low 32 Bits of the Base Address of the memory range
Base Address High	4	12	High 32 Bits of the Base Address of the memory range
Length Low	4	16	Low 32 Bits of the length of the memory range.
Length High	4	20	High 32 Bits of the length of the memory range.
Reserved	4	24	Reserved.
Flags	4	28	Flags – Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged. Details in See Table 5-38.
Reserved	8	32	Reserved.

Table 5-38 Flags – Memory Affinity Structure

Field	Bit Length	Bit Offset	Description
Enabled	1	0	If clear, the OSPM ignores the contents of the Memory Affinity Structure. This allows system firmware to populate the SRAT with a static number of structures but only enable then as necessary.
Hot Pluggable[5]	1	1	The information conveyed by this bit depends on the value of the Enabled bit. If the Enabled bit is set and the Hot Pluggable bit is also set. The system hardware supports hot-add and hot-remove of this memory region If the Enabled bit is set and the Hot Pluggable bit is clear, the system hardware does not support hot-add or hot-remove of this memory region. If the Enabled bit is clear, the OSPM will ignore the contents of the Memory Affinity Structure
NonVolatile	1	2	If set, the memory region represents Non-Volatile memory
Reserved	29	3	Must be zero.

5.2.16 System Locality Distance Information Table (SLIT)
This optional table provides a matrix that describes the relative distance (memory latency) between all System Localities, which are also referred to as Proximity Domains. Systems employing a Non Uniform Memory Access (NUMA) architecture contain collections of hardware resources including for example, processors, memory, and I/O buses, that comprise what is known as a "NUMA node". Processor accesses to memory or I/O resources within the local NUMA node is generally faster than processor accesses to memory or I/O resources outside of the local NUMA node.
The value of each Entry[i,j] in the SLIT table, where i represents a row of a matrix and j represents a column of a matrix, indicates the relative distances from System Locality / Proximity Domain i to every other System Locality j in the system (including itself).
The i,j row and column values correlate to the value returned by the _PXM object in the ACPI namespace. See section 6.2.12, "_PXM (Proximity)" for more information.
The entry value is a one-byte unsigned integer. The relative distance from System Locality i to System Locality j is the i*N + j entry in the matrix, where N is the number of System Localities. Except for the relative distance from a System Locality to itself, each relative distance is stored twice in the matrix. This provides the capability to describe the scenario where the relative distances for the two directions between System Localities is different.
The diagonal elements of the matrix, the relative distances from a System Locality to itself are normalized to a value of 10. The relative distances for the non-diagonal elements are scaled to be relative to 10 example, if the relative distance from System Locality i to System Locality j style='font-style:normal'> is 2.4, a value of 24 is stored in table entry i*N+ j and in j*N+ i, where N is the number of System Localities.

If one locality is unreachable from another, a value of 255 (0xFF) is stored in that table entry. Distance values of 0-9 are reserved and have no meaning.
Table 5-39 SLIT Format

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'SLIT'. Signature for the System Locality Distance Information Table.
Length	4	4	Length, in bytes, of the entire System Locality Distance Information Table.
Revision	1	8	1
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID.
OEM Table ID	8	16	For the System Locality Information Table, the table ID is the manufacturer model ID.
OEM Revision	4	24	OEM revision of System Locality Information Table for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the revision for the ASL Compiler.
Number of System Localities	8	36	Indicates the number of System Localities in the system.
Entry[0][0]	1	44	Matrix entry (0,0), contains a value of 10.
�
Entry[0][Number of System Localities-1]	1		Matrix entry (0, Number of System Localities-1)
Entry[1][0]	1		Matrix entry (1,0)
��			��
Entry[Number of System Localities-1][Number of System Localities-1]	1		Matrix entry (Number of System Localities-1, Number of System Localities-1), contains a value of 10

5.3   ACPI Namespace
For all Definition Blocks, the system maintains a single hierarchical namespace that it uses to refer to objects. All Definition Blocks load into the same namespace. Although this allows one Definition Block to reference objects and data from another (thus enabling interaction), it also means that OEMs must take care to avoid any naming collisions[6]. Only an unload operation of a Definition Block can remove names from the namespace, so a name collision in an attempt to load a Definition Block is considered fatal. The contents of the namespace changes only on a load or unload operation.
The namespace is hierarchical in nature, with each name allowing a collection of names "below" it. The following naming conventions apply to all names:
·       All names are a fixed 32 bits.
·       The first byte of a name is inclusive of: 'A'–'Z', '_', (0x41–0x5A, 0x5F).
·       The remaining three bytes of a name are inclusive of: 'A'–'Z', '0'–'9', '_', (0x41–0x5A, 0x30–0x39, 0x5F).
·       By convention, when an ASL compiler pads a name shorter than 4 characters, it is done so with trailing underscores ('_'). See the language definition for AML NameSeg in Section 16, "ACPI Source Language Reference."
·       Names beginning with '_' are reserved by this specification. Definition Blocks can only use names beginning with '_' as defined by this specification.
·       A name proceeded with '\' causes the name to refer to the root of the namespace ('\' is not part of the 32-bit fixed-length name).
·       A name proceeded with '^' causes the name to refer to the parent of the current namespace ('^' is not part of the 32-bit fixed-length name).

Except for names preceded with a '\', the current namespace determines where in the namespace hierarchy a name being created goes and where a name being referenced is found. A name is located by finding the matching name in the current namespace, and then in the parent namespace the parent namespace does not contain the name, the search continues recursively upwards until either the name is found or the namespace does not have a parent (the root of the namespace). This indicates that the name is not found[7].

An attempt to access names in the parent of the root will result in the name not being found.
There are two types of namespace paths: an absolute namespace path (that is, one that starts with a '\' prefix), and a relative namespace path (that is, one that is relative to the current namespace). The namespace search rules discussed above, only apply to single NameSeg paths, which is a relative namespace path. For those relative name paths that contain multiple NameSegs or Parent Prefixes, '^', the search rules do not apply. If the search rules do not apply to a relative namespace path, the namespace object is looked up relative to the current namespace example:
ABCD                           //search rules apply
^ABCD                        //search rules do not apply
XYZ.ABCD                 //search rules do not apply
\XYZ.ABCD               //search rules do not apply
All name references use a 32-bit fixed-length name or use a Name Extension prefix to concatenate multiple 32-bit fixed-length name components together. This is useful for referring to the name of an object, such as a control method, that is not in the scope of the current namespace.

The figure below shows a sample of the ACPI namespace after a Differentiated Definition Block has been loaded.

Figure 5-5 Example ACPI NameSpace
Care must be taken when accessing namespace objects using a relative single segment name because of the namespace search rules. An attempt to access a relative object recurses toward the root until the object is found or the root is encountered. This can cause unintentional results. For example, using the namespace described in Figure 5.5, attempting to access a _CRS named object from within the \_SB_.PCI0.IDE0 will have different results depending on if an absolute or relative path name is used. If an absolute pathname is specified (\_SB_.PCI0.IDE0._CRS) an error will result since the object does not exist. Access using a single segment name (_CRS) will actually access the \_SB_.PCI0._CRS object. Notice that the access will occur successfully with no errors.

5.3.1 Predefined Root Namespaces
The following namespaces are defined under the namespace root.
Table 5-40 Namespaces Defined Under the Namespace Root

Name	Description
\_GPE	General events in GPE register block.
\_PR	ACPI 1.0 Processor Namespace. ACPI 1.0 requires all Processor objects to be defined under this namespace. ACPI allows Processor object definitions under the \_SB namespace. Platforms may maintain the \_PR namespace for compatibility with ACPI 1.0 operating systems ACPI-compatible namespace may define Processor objects in either the \_SB or \_PR scope but not both. For more information about defining Processor objects, see section 8, "Processor Power and Performance State Configuration and Control."
\_SB	All Device/Bus Objects are defined under this namespace.
\_SI	System indicator objects are defined under this namespace more information about defining system indicators, see section 9.1, \_S1 System Indicators."
\_TZ	ACPI 1.0 Thermal Zone namespace. ACPI 1.0 requires all Thermal Zone objects to be defined under this namespace. Thermal Zone object definitions may now be defined under the \_SB namespace. ACPI-compatible systems may maintain the \_TZ namespace for compatibility with ACPI 1.0 operating systems. An ACPI-compatible namespace may define Thermal Zone objects in either the \_SB or \_TZ scope but not both. For more information about defining Thermal Zone objects, see section 11, "Thermal Management."

5.3.2 Objects
All objects, except locals, have a global scope. Local data objects have a per-invocation scope and lifetime and are used to process the current invocation from beginning to end.
The contents of objects vary greatly. Nevertheless, most objects refer to data variables of any supported data type, a control method, or system software-provided functions.
5.4 Definition Block Encoding
This section specifies the encoding used in a Definition Block to define names (load time only), objects, and packages. The Definition Block is encoded as a stream from beginning to end. The lead byte in the stream comes from the AML encoding tables shown in section 17, "ACPI Source Language (ASL) Reference," and signifies how to interpret some number of following bytes, where each following byte can in turn signify how to interpret some number of following bytes. For a full specification of the AML encoding, see section 17, "ACPI Source Language (ASL) Reference."
Within the stream there are two levels of data being defined. One is the packaging and object declarations (load time), and the other is an object reference (package contents/run-time).

All encodings are such that the lead byte of an encoding signifies the type of declaration or reference being made. The type either has an implicit or explicit length in the stream. All explicit length declarations take the form shown below, where PkgLength is the length of the inclusive length of the data for the operation.

Figure 5-6   AML Encoding
Encodings of implicit length objects either have fixed length encodings or allow for nested encodings that, at some point, either result in an explicit or implicit fixed length.
The PkgLength is encoded as a series of 1 to 4 bytes in the stream with the most significant two bits of byte zero, indicating how many following bytes are in the PkgLength encoding. The next two bits are only used in one-byte encodings, which allows for one-byte encodings on a length up to 0x3F. Longer encodings, which do not use these two bits, have a maximum length of the following: two-byte encodings of 0x0FFF, three-byte encodings of 0x0FFFFF, and four-byte length encodings of 0x0FFFFFFFFF.
It is fatal for a package length to not fall on a logical boundary. For example, if a package is contained in another package, then by definition its length must be contained within the outer package, and similarly for a datum of implicit length.
At some point, the system software decides to "load" a Definition Block. Loading is accomplished when the system makes a pass over the data and populates the ACPI namespace and initializes objects accordingly namespace for which population occurs is either from the current namespace location, as defined by all nested packages or from the root if the name is preceded with '\'.
The first object present in a Definition Block must be a named control method. This is the Definition Block's initialization control.
Packages are objects that contain an ordered reference to one or more objects. A package can also be considered a vertex of an array, and any object contained within a package can be another package. This permits multidimensional arrays of fixed or dynamic depths and vertices.
Unnamed objects are used to populate the contents of named objects. Unnamed objects cannot be created in the "root." Unnamed objects can be used as arguments in control methods.

Control method execution may generate errors when creating objects. This can occur if a Method that creates named objects blocks and is reentered while blocked. This will happen because all named objects have an absolute path. This is true even if the object name specified is relative. For example, the following ASL code segments are functionally identical.

(1)
    Method (DEAD,) {
       Scope (\_SB_.FOO) {
           Name (BAR,)        // Run time definition
       }
    }
(2)
    Scope (\_SB_) {
       Name (\_SB_. FOO.BAR,) // Load time definition
    }
Notice that in the above example the execution of the DEAD method will always fail because the object \_SB_.FOO.BAR is created at load time.

5.5   Using the ACPI Control Method Source Language
OEMs and BIOS vendors write definition blocks using the ACPI Control Method Source language (ASL) and use a translator to produce the byte stream encoding described in section 5.4, "Definition Block Encoding" example, the ASL statements that produce the example byte stream shown in that earlier section are shown in the following ASL example. For a full specification of the ASL statements, see section 17, "ACPI Source Language (ASL) Reference."

// ASL Example
DefinitionBlock (
    "forbook.aml",    // Output Filename
    "DSDT",               // Signature
    0x02,             // DSDT Compliance Revision
    "OEM",            // OEMID
    "forbook",        // TABLE ID
    0x1000            // OEM Revision
)
{   // start of definition block
    OperationRegion(\GIO, SystemIO, 0x125, 0x1)
    Field(\GIO, ByteAcc, NoLock, Preserve) {
       CT01, 1,
    }

    Scope(\_SB)   {   // start of scope
       Device(PCI0) {     // start of device
           PowerResource(FET0, 0, 0) {     // start of pwr
              Method (_ON) {
                  Store (Ones, CT01)           // assert power
                  Sleep (30)               // wait 30ms
              }
              Method (_OFF) {
                  Store (Zero, CT01)           // assert reset#
              }
              Method (_STA) {
                  Return (CT01)
              }
           } // end of power
       } // end of device
    } // end of scope
} // end of definition block
5.5.1   ASL Statements
ASL is principally a declarative language. ASL statements declare objects. Each object has three parts, two of which can be null:

    Object := ObjectType FixedList VariableList
FixedList refers to a list of known length that supplies data that all instances of a given ObjectType must have. It is written as (a, b, c,), where the number of arguments depends on the specific ObjectType, and some elements can be nested objects, that is (a, b, (q, r, s, t), d). Arguments to a FixedList can have default values, in which case they can be skipped. Some ObjectTypes can have a null FixedList.

VariableList refers to a list, not of predetermined length, of child objects that help define the parent. It is written as {x, y, z, aa, bb, cc}, where any argument can be a nested object. ObjectType determines what terms are legal elements of the VariableList. Some ObjectTypes can have a null variable list.

For a detailed specification of the ASL language, see section 17, "ACPI Source Language (ASL) Reference." For a detailed specification of the ACPI Control Method Machine Language (AML), upon which the output of the ASL translator is based, see section 18, "ACPI Machine Language (AML) Specification."

5.5.2 Control Method Execution
The operating software will initiate well-defined control methods as necessary to either interrogate or adjust system-level hardware state. This is called an invocation.
A control method can use other internal, or well defined, control methods to accomplish the task at hand, which can include defined control methods provided by the operating software. Interpretation of a Control Method is not preemptive, but it can block. When a control method does block, the operating software can initiate or continue the execution of a different control method. A control method can only assume that access to global objects is exclusive for any period the control method does not block.
Global objects are those NameSpace objects created at table load time.
5.5.2.1 Access to Objects and Operation Regions
Control Methods can reference any objects anywhere in the Namespace as well as address spaces defined in operation regions. Control methods must have exclusive access to the any address accessed via OpRegions. Control methods do not directly access any other hardware registers, including the ACPI-defined register blocks. Some of the ACPI registers, in the defined ACPI registers blocks, are maintained on behalf of control method execution. For example, the GPEx_BLK is not directly accessed by a control method but is used to provide an extensible interrupt handling model for control method invocation.
Note: Accessing an OpRegion may block, even if the OpRegion is not protected by a mutex example, because of the slow nature of the embedded controller, an embedded controller OpRegion field access may block.

5.5.2.2   Arguments
Up to seven arguments can be passed to a control method. Each argument is an object which in turn could be a "package" style object that refers to other objects. Access to the argument objects is provided via the ASL ArgTerm (ArgX) language elements. The number of arguments passed to any control method is fixed and is defined when the control method package is created.
Method arguments can take one of the following forms:
1)     An ACPI name or namepath that refers to a named object. This includes the LocalX and ArgX names. In this case, the object associated with the name is passed as the argument.
2)     An ACPI name or namepath that refers to another control method. In this case, the method is invoked and the return value of the method is passed as the argument. A fatal error occurs if no object is returned from the method. If the object is not used after the method invocation it is automatically deleted.
3)     A valid ASL expression. In the case, the expression is evaluated and the object that results from this evaluation is passed as the argument. If this object is not used after the method invocation it is automatically deleted.
5.5.2.3   Method Calling Convention
The calling convention for control methods can best be described as call-by-reference-constant. In this convention, objects passed as arguments are passed by "reference", meaning that they are not copied to new objects as they are passed to the called control method (A calling convention that copies objects or object wrappers during a call is known as call-by-value style='font-style:normal'> or call-by-copy).
This call-by-reference-constant convention allows internal objects to be shared across each method invocation, therefore reducing the number of object copies that must be performed as well as the number of buffers that must be copied. This calling convention is appropriate to the low-level nature of the ACPI subsystem within the kernel of the host operating system where non-paged dynamic memory is typically at a premium. The ASL programmer must be aware of the calling convention and the related side effects.
However, unlike a pure call-by-reference convention, the ability of the called control method to modify arguments is extremely limited. This reduces aliasing issues such as when a called method unexpectedly modifies a object or variable that has been passed as an argument by the caller. In effect, the arguments that are passed to control methods are passed as constants that cannot be modified except under specific controlled circumstances.
Generally, the objects passed to a control method via the ArgX terms cannot be directly written or modified by the called method other words, when an ArgX term is used as a target operand in an ASL statement, the existing ArgX object is not modified. Instead, the new object replaces the existing object and the ArgX term effectively becomes a LocalX term.
The only exception to the read-only argument rule is if an ArgX term contains an Object Reference created via the RefOf ASL operator. In this case, the use of the ArgX term as a target operand will cause any existing object stored at the ACPI name referred to by the RefOf operation to be overwritten.
In some limited cases, a new, writable object may be created that will allow a control method to change the value of an ArgX object. These cases are limited to Buffer and Package objects where the "value" of the object is represented indirectly. For Buffers, a writable Index or Field can be created that refers to the original buffer data and will allow the called method to read or modify the data. For Packages, a writable Index can be created to allow the called method to modify the contents of individual elements of the Package.
5.5.2.4   Local Variables and Locally Created Data Objects
Control methods can access up to eight local data objects. Access to the local data objects have shorthand encodings. On initial control method execution, the local data objects are NULL. Access to local objects is via the ASL LocalTerm language elements.
Upon control method execution completion, one object can be returned that can be used as the result of the execution of the method "caller" must either use the result or save it to a different object if it wants to preserve it. See the description of the Return ASL operator for additional details
NameSpace objects created within the scope of a method are dynamic. They exist only for the duration of the method execution. They are created when specified by the code and are destroyed on exit. A method may create dynamic objects outside of the current scope in the NameSpace using the scope operator or using full path names. These objects will still be destroyed on method exit. Objects created at load time outside of the scope of the method are static. For example:

Scope (\XYZ) {
    Name (BAR, 5)           // Creates \XYZ.BAR
    Method (FOO, 1) {
       Store (BAR, CREG) // same effect as Store (\XYZ.BAR, CREG)
       Name (BAR, 7) // Creates \XYZ.FOO.BAR
       Store (BAR, DREG) // same effect as Store (\XYZ.FOO.BAR, DREG
       Name (\XYZ.FOOB, 3) // Creates \XYZ.FOOB
    } // end method
} // end scope

The object \XYZ.BAR is a static object created when the table that contains the above ASL is loaded. The object \XYZ.FOO.BAR is a dynamic object that is created when the Name (BAR, 7) statement in the FOO method is executed. The object \XYZ.FOOB is a dynamic object created by the \XYZ.FOO method when the Name (\XYZ.FOOB, 3) statement is executed. Notice that the \XYZ.FOOB object is destroyed after the \XYZ.FOO method exits.
5.6   ACPI Event Programming Model
The ACPI event programming model is based on the SCI interrupt and General-Purpose Event (GPE) register. ACPI provides an extensible method to raise and handle the SCI interrupt, as described in this section.

5.6.1 ACPI Event Programming Model Components
The components of the ACPI event programming model are the following:
· OSPM

· FADT

·       PM1a_STS, PM1b_STS and PM1a_EN, PM1b_EN fixed register blocks
·       GPE0_BLK and GPE1_BLK register blocks
·       GPE register blocks defined in GPE block devices
·       SCI interrupt
·       ACPI AML code general-purpose event model
·       ACPI device-specific model events
·       ACPI Embedded Controller event model
The role of each component in the ACPI event programming model is described in the following table.
Table 5-41   ACPI Event Programming Model Components

Component	Description
OSPM	Receives all SCI interrupts raised (receives all SCI events). Either handles the event or masks the event off and later invokes an OEM-provided control method to handle the event. Events handled directly by OSPM are fixed ACPI events; interrupts handled by control methods are general-purpose events.
FADT	Specifies the base address for the following fixed register blocks on an ACPI-compatible platform: PM1x_STS and PM1x_EN fixed registers and the GPEx_STS and GPEx_EN fixed registers.
PM1x_STS and PM1x_EN fixed registers	PM1x_STS bits raise fixed ACPI events. While a PM1x_STS bit is set, if the matching PM1x_EN bit is set, the ACPI SCI event is raised.
GPEx_STS and GPEx_EN fixed registers	GPEx_STS bits that raise general-purpose events. For every event bit implemented in GPEx_STS, there must be a comparable bit in GPEx_EN. Up to 256 GPEx_STS bits and matching GPEx_EN bits can be implemented. While a GPEx_STS bit is set, if the matching GPEx_EN bit is set, then the general-purpose SCI event is raised.
SCI interrupt	A level-sensitive, shareable interrupt mapped to a declared interrupt vector. The SCI interrupt vector can be shared with other low-priority interrupts that have a low frequency of occurrence.
ACPI AML code general-purpose event model	A model that allows OEM AML code to use GPEx_STS events. This includes using GPEx_STS events as "wake" sources as well as other general service events defined by the OEM ("button pressed," "thermal event," "device present/not present changed," and so on).
ACPI device-specific model events	Devices in the ACPI namespace that have ACPI-specific device IDs can provide additional event model functionality. In particular, the ACPI embedded controller device provides a generic event model.
ACPI Embedded Controller event model	A model that allows OEM AML code to use the response from the Embedded Controller Query command to provide general-service event defined by the OEM.

5.6.2   Types of ACPI Events
At the direct ACPI hardware level, two types of events can be signaled by an SCI interrupt:
·      Fixed ACPI events
·      General-purpose events
In turn, the general-purpose events can be used to provide further levels of events to the system. And, as in the case of the embedded controller, a well-defined second-level event dispatching is defined to make a third type of typical ACPI event. For the flexibility common in today's designs, two first-level general-purpose event blocks are defined, and the embedded controller construct allows a large number of embedded controller second-level event-dispatching tables to be supported. Then if needed, the OEM can also build additional levels of event dispatching by using AML code on a general-purpose event to sub-dispatch in an OEM defined manner.
5.6.2.1   Fixed ACPI Event Handling
When OSPM receives a fixed ACPI event, it directly reads and handles the event registers itself. The following table lists the fixed ACPI events. For a detailed specification of each event, see section 4, "ACPI Hardware Specification."
Table 5-42   Fixed ACPI Events

Event	Comment
Power management timer carry bit set.	For more information, see the description of the TMR_STS and TMR_EN bits of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping," as well as the TMR_VAL register in the PM_TMR_BLK in section 4.7.3.3, "Power Management Timer."
Power button signal	A power button can be supplied in two ways. One way is to simply use the fixed status bit, and the other uses the declaration of an ACPI power device and AML code to determine the event. For more information about the alternate-device based power button, see section 4.7.2.2.1.2, Control Method Power Button." Notice that during the S0 state, both the power and sleep buttons merely notify OSPM that they were pressed. If the system does not have a sleep button, it is recommended that OSPM use the power button to initiate sleep operations as requested by the user.
Sleep button signal	A sleep button can be supplied in one of two ways. One way is to simply use the fixed status button. The other way requires the declaration of an ACPI sleep button device and AML code to determine the event.
RTC alarm	ACPI-defines an RTC wake alarm function with a minimum of one-month granularity. The ACPI status bit for the device is optional. If the ACPI status bit is not present, the RTC status can be used to determine when an alarm has occurred. For more information, see the description of the RTC_STS and RTC_EN bits of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping."
Wake status	The wake status bit is used to determine when the sleeping state has been completed. For more information, see the description of the WAK_STS and WAK_EN bits of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping."

Table 5-42 Fixed ACPI Events (continued)

Event	Comment
System bus master request	The bus-master status bit provides feedback from the hardware as to when a bus master cycle has occurred. This is necessary for supporting the processor C3 power savings state. For more information, see the description of the BM_STS bit of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping."
Global release status	This status is raised as a result of the Global Lock protocol, and is handled by OSPM as part of Global Lock synchronization. For more information, see the description of the GBL_STS bit of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping." For more information on Global Lock, see section 5.2.10.1, "Global Lock."

5.6.2.2   General-Purpose Event Handling
When OSPM receives a general-purpose event, it either passes control to an ACPI-aware driver, or uses an OEM-supplied control method to handle the event. An OEM can implement up to 128 general-purpose event inputs in hardware per GPE block, each as either a level or edge event. It is also possible to implement a single 256-pin block as long as it's the only block defined in the system.
An example of a general-purpose event is specified in section 4, "ACPI Hardware Specification," where EC_STS and EC_EN bits are defined to enable OSPM to communicate with an ACPI-aware embedded controller device driver. The EC_STS bit is set when either an interface in the embedded controller space has generated an interrupt or the embedded controller interface needs servicing. Notice that if a platform uses an embedded controller in the ACPI environment, then the embedded controller's SCI output must be directly and exclusively tied to a single GPE input bit.
Hardware can cascade other general-purpose events from a bit in the GPEx_BLK through status and enable bits in Operational Regions (I/O space, memory space, PCI configuration space, or embedded controller space). For more information, see the specification of the General-Purpose Event Blocks (GPEx_BLK) in section 4.7.4.1, "General-Purpose Event Register Blocks."
OSPM manages the bits in the GPEx blocks directly, although the source to those events is not directly known and is connected into the system by control methods. When OSPM receives a general-purpose event (the event is from a GPEx_BLK STS bit), OSPM does the following:
1.    Disables the interrupt source (GPEx_BLK EN bit).
2.    If an edge event, clears the status bit.
3.    Performs one of the following:
·       Dispatches to an ACPI-aware device driver.
·       Queues the matching control method for execution.
·       Manages a wake event using device _PRW objects.
4.    If a level event, clears the status bit.
5.    Enables the interrupt source.
The OEM AML code can perform OEM-specific functions custom to each event the particular platform might generate by executing a control method that matches the event. For GPE events, OSPM will execute the control method of the name \_GPE._TXX where XX is the hex value format of the event that needs to be handled and T indicates the event handling type (T must be either 'E' for an edge event or 'L' for a level event). The event values for status bits in GPE0_BLK start at zero (_T00) and end at the (GPE0_BLK_LEN / 2) - 1. The event values for status bits in GPE1_BLK start at GPE1_BASE and end at GPE1_BASE + (GPE1_BLK_LEN / 2) - 1. GPE0_BLK_LEN, GPE1_BASE, and GPE1_BLK_LEN are all defined in the FADT.
For OSPM to manage the bits in the GPEx_BLK blocks directly:
·       Enable bits must be read/write.
·       Status bits must be latching.
·       Status bits must be read/clear, and cleared by writing a "1" to the status bit.

5.6.2.2.1 Wake Events
An important use of the general-purpose events is to implement device wake events. The components of the ACPI event programming model interact in the following way:
· When a device asserts its wake signal, the general-purpose status event bit used to track that device is set.
· While the corresponding general-purpose enable bit is enabled, the SCI interrupt is asserted.
· If the system is sleeping, this will cause the hardware, if possible, to transition the system into the S0 state.
· Once the system is running, OSPM will dispatch the corresponding GPE handler.
· The handler needs to determine which device object has signaled wake and performs a wake Notify command on the corresponding device object(s) that have asserted wake.
· In turn OSPM will notify OSPM native driver(s) for each device that will wake its device to service it.
Events that wake may not be intermixed with non-wake (runtime) events on the same GPE input. The only exception to this rule is made for the special devices below. Only the following devices are allowed to utilize a single GPE for both wake and runtime events:
1) Button Devices
· PNP0C0C — Power Button Device

· PNP0C0D — Lid Device

· PNP0C0E — Sleep Button Device

2) PCI Bus Wakeup Event Reporting (PME)
· PNP0A03 — PCI Host Bridge

All wake events that are not exclusively tied to a GPE input (for example, one input is shared for multiple wake events) must have individual enable and status bits in order to properly handle the semantics used by the system.
5.6.2.2.2   Dispatching to an ACPI-Aware Device Driver
Certain device support, such as an embedded controller, requires a dedicated GPE to service the device. Such GPEs are dispatched to native OS code to be handled and not to the corresponding GPE-specific control method.
In the case of the embedded controller, an OS-native, ACPI-aware driver is given the GPE event for its device. This driver services the embedded controller device and determines when events are to be reported by the embedded controller by using the Query command. When an embedded controller event occurs, the ACPI-aware driver dispatches the requests to other ACPI-aware drivers that have registered to handle the embedded controller queries or queues control methods to handle each event. If there is no device driver to handle specific queries, OEM AML code can perform OEM-specific functions that are customized to each event on the particular platform by including specific control methods in the namespace to handle these events. For an embedded controller event, OSPM will queue the control method of the name _QXX, where XX is the hex format of the query code. Notice that each embedded controller device can have query event control methods.
Similarly, for an SMBus driver, if no driver registers for SMBus alarms, the SMBus driver will queue control methods to handle these. Methods must be placed under the SMBus device with the name _QXX where XX is the hex format of the SMBus address of the device sending the alarm.
5.6.2.2.3   Queuing the Matching Control Method for Execution
When a general-purpose event is raised, OSPM uses a naming convention to determine which control method to queue for execution and how the GPE EOI is to be handled. The GPEx_STS bits in the GPEx_BLK are indexed with a number from 0 through FF. The name of the control method to queue for an event raised from an enable status bit is always of the form \_GPE._Txx where xx is the event value and T indicates the event EOI protocol to use (either edge or level). The event values for status bits in GPE0_BLK start at zero (_T00), end at the (GPE0_BLK_LEN / 2) - 1, and correspond to each status bit index within GPE0_BLK. The event values for status bits in GPE1_BLK are offset by GPE_BASE and therefore start at GPE1_BASE and end at GPE1_BASE + (GPE1_BLK_LEN / 2) - 1.
For example, suppose an OEM supplies a wake event for a communications port and uses bit 4 of the GPE0_STS bits to raise the wake event status. In an OEM-provided Definition Block, there must be a Method declaration that uses the name \_GPE._L04 or \GPE._E04 to handle the event. An example of a control method declaration using such a name is the following:

Method (\_GPE._L04) {        // GPE 4 level wake handler
    Notify (\_SB.PCIO.COM0, 2)
}
The control method performs whatever action is appropriate for the event it handles. For example, if the event means that a device has appeared in a slot, the control method might acknowledge the event to some other hardware register and signal a change notify request of the appropriate device object. Or, the cause of the general-purpose event can result from more then one source, in which case the control method for that event determines the source and takes the appropriate action.
When a general-purpose event is raised from the GPE bit tied to an embedded controller, the embedded controller driver uses another naming convention defined by ACPI for the embedded controller driver to determine which control method to queue for execution. The queries that the embedded controller driver exchanges with the embedded controller are numbered from 0 through FF, yielding event codes 01 through FF. (A query response of 0 from the embedded controller is reserved for "no outstanding events.") The name of the control method to queue is always of the form _Qxx where xx is the number of the query acknowledged by the embedded controller. An example declaration for a control method that handles an embedded controller query is the following:

Method(_Q34) {        // embedded controller event for thermal
    Notify (\_SB.TZ0.THM1, 0x80)
}
When an SMBus alarm is handled by the SMBus driver, the SMBus driver uses a similar naming convention defined by ACPI for the driver to determine the control method to queue for execution. When an alarm is received by the SMBus host controller, it generally receives the SMBus address of the device issuing the alarm and one word of data. On implementations that use SMBALERT# for notifications, only the device address will be received. The name of the control method to queue is always of the form _Qxx where xx is the SMBus address of the device that issued the alarm. The SMBus address is 7 bits long corresponding to hex values 0 through 7F, although some addresses are reserved and will not be used. The control method will always be queued with one argument that contains the word of data received with the alarm exception is the case of an SMBus using SMBALERT# for notifications, in this case the argument will be 0. An example declaration for a control method that handles a SMBus alarm follows:

Method(_Q18, 1) {     // Thermal sensor device at address 0011 000

    // Arg0 contains notification value (if any)
    // Arg0 = 0 if device supports only SMBALERT#

    Notify (\_SB.TZ0.THM1, 0x80)
}
5.6.2.2.4   Managing a Wake Event Using Device _PRW Objects
A device's _PRW object provides the zero-based bit index into the general-purpose status register block to indicate which general-purpose status bit from either GPE0_BLK or GPE1_BLK is used as the specific device's wake mask. Although the hardware must maintain individual device wake enable bits, the system can have multiple devices using the same general-purpose event bit by using OEM-specific hardware to provide second-level status and enable bits. In this case, the OEM AML code is responsible for the second-level enable and status bits.
OSPM enables or disables the device wake function by enabling or disabling its corresponding GPE and by executing its _PSW control method (which is used to take care of the second-level enables). When the GPE is asserted, OSPM still executes the corresponding GPE control method that determines which device wakes are asserted and notifies the corresponding device objects. The native OS driver is then notified that its device has asserted wake, for which the driver powers on its device to service it.
If the system is in a sleeping state when the enabled GPE bit is asserted the hardware will transition the system into the S0 state, if possible.
5.6.2.2.5 Determining the System Wake Source Using _Wxx Control Methods

After a transition to the S0 state, OSPM may evaluate the _SWS object in the \_GPE scope to determine the index of the GPE that was the source of the transition event. When a single GPEs is shared among multiple devices, the platform provides a _Wxx control method, where xx is GPE index as described in Section 5.6.2.2.3, that allows the source device of the transition to be determined . If implemented, the _Wxx control method must exist in the \_GPE scope or in the scope of a GPE block device.
If _Wxx is implemented, either hardware or firmware must detect and save the source device as described in Section 7.3.5, "_SWS (System Wake Source)". During invocation, the _Wxx control method determines the source device and issues a Notify(<device>,0x2) on the device that caused the system to transition to the S0 state. If the device uses a bus-specific method of arming for wakeup, then the Notify must be issued on the parent of the device that has a _PRW method. The _Wxx method must issue a Notify(<device>,0x2) only to devices that contain a _PRW method within their device scope. OSPM's evaluation of the _SWS and _Wxx objects is indeterminate. As such, the platform must not rely on _SWS or _Wxx evaluation to clear any hardware state, including GPEx_STS bits, or to perform any wakeup-related actions.
If the GPE index returned by the _SWS object is only referenced by a single _PRW object in the system, it is implied that the device containing that _PRW is the wake source. In this case, it is not necessary for the platform to provide a _Wxx method.
5.6.3   Device Object Notifications
During normal operation, the platform needs to notify OSPM of various device-related events. These notifications are accomplished using the Notify operator, which indicates a target device, thermal zone, or processor object and a notification value that signifies the purpose of the notification. Notification values from 0 through 0x7F are common across all device object types. Notification values of 0xC0 and above are reserved for definition by hardware vendors for hardware specific notifications. Notification values from 0x80 to 0xBF are device-specific and defined by each such device. For more information on the Notify operator, see section 17.5.85, "Notify (Notify)."
Table 5-43   Device Object Notification Values

Value	Description
0	Bus Check. This notification is performed on a device object to indicate to OSPM that it needs to perform the Plug and Play re-enumeration operation on the device tree starting from the point where it has been notified. OSPM will only perform this operation at boot, and when notified. It is the responsibility of the ACPI AML code to notify OSPM at any other times that this operation is required. The more accurately and closer to the actual device tree change the notification can be done, the more efficient the operating system's response will be; however, it can also be an issue when a device change cannot be confirmed. For example, if the hardware cannot notice a device change for a particular location during a system sleeping state, it issues a Bus Check notification on wake to inform OSPM that it needs to check the configuration for a device change.
1	Device Check. Used to notify OSPM that the device either appeared or disappeared. If the device has appeared, OSPM will re-enumerate from the parent. If the device has disappeared, OSPM will invalidate the state of the device. OSPM may optimize out re-enumeration. If _DCK is present, then Notify(object,1) is assumed to indicate an undock request.
2	Device Wake. Used to notify OSPM that the device has signaled its wake event, and that OSPM needs to notify OSPM native device driver for the device. This is only used for devices that support _PRW.
3	Eject Request. Used to notify OSPM that the device should be ejected, and that OSPM needs to perform the Plug and Play ejection operation. OSPM will run the _EJx method.
4	Device Check Light. Used to notify OSPM that the device either appeared or disappeared. If the device has appeared, OSPM will re-enumerate from the device itself, not the parent. If the device has disappeared, OSPM will invalidate the state of the device.
5	Frequency Mismatch. Used to notify OSPM that a device inserted into a slot cannot be attached to the bus because the device cannot be operated at the current frequency of the bus. For example, this would be used if a user tried to hot-plug a 33 MHz PCI device into a slot that was on a bus running at greater than 33 MHz.
6	Bus Mode Mismatch. Used to notify OSPM that a device has been inserted into a slot or bay that cannot support the device in its current mode of operation. For example, this would be used if a user tried to hot-plug a PCI device into a slot that was on a bus running in PCI-X mode.
7	Power Fault. Used to notify OSPM that a device cannot be moved out of the D3 state because of a power fault.
8	Capabilities Check. This notification is performed on a device object to indicate to OSPM that it needs to re-evaluate the _OSC control method associated with the device.
9	Device _PLD Check. Used to notify OSPM to reevaluate the _PLD object, as the Device's connection point has changed.
0xA	*Reserved*.
0xB	System Locality Information Update. Dynamic reconfiguration of the system may cause existing relative distance information to change. The platform sends the System Locality Information Update notification to a point on a device tree to indicate to OSPM that it needs to invoke the _SLI objects associated with the System Localities on the device tree starting from the point notified.
0xC-0x7F	*Reserved*.

Below are the notification values defined for specific ACPI devices. For more information concerning the object-specific notification, see the section on the corresponding device/object.
Table 5-44 Control Method Battery Device Notification Values

Hex value	Description
0x80	Battery Status Changed. Used to notify OSPM that the Control Method Battery device status has changed.
0x81	Battery Information Changed. Used to notify OSPM that the Control Method Battery device information has changed. This only occurs when a battery is replaced.
0x82	Battery Maintenance Data Status Flags Check. Used to notify OSPM that the Control Method Battery device battery maintenance data status flags should be checked.
0x83-0xBF	*Reserved*.

Table 5-45 Power Source Object Notification Values

Hex value	Description
0x80	Power Source Status Changed. Used to notify OSPM that the power source status has changed.
0x81-0xBF	*Reserved*.

Table 5-46 Thermal Zone Object Notification Values

Hex value	Description
0x80	Thermal Zone Status Changed. Used to notify OSPM that the thermal zone temperature has changed.
0x81	Thermal Zone Trip points Changed. Used to notify OSPM that the thermal zone trip points have changed.
0x82	Device Lists Changed. Used to notify OSPM that the thermal zone device lists (_ALx, _PSL, _TZD) have changed.
0x83	Thermal Relationship Table Changed. Used to notify OSPM that values in the thermal relationship table have changed.
0x84-0xBF	*Reserved*.

Table 5-47 Control Method Power Button Notification Values

Hex value	Description
0x80	S0 Power Button Pressed. Used to notify OSPM that the power button has been pressed while the system is in the S0 state. Notice that when the button is pressed while the system is in the S1-S4 state, a Device Wake notification must be issued instead.
0x81-0xBF	Reserved.

Table 5-48 Control Method Sleep Button Notification Values

Hex value	Description
0x80	S0 Sleep Button Pressed. Used to notify OSPM that the sleep button has been pressed while the system is in the S0 state. Notice that when the button is pressed while the system is in the S1-S4 state, a Device Wake notification must be issued instead.
0x81-0xBF	Reserved.

Table 5-49 Control Method Lid Notification Values

Hex value	Description
0x80	Lid Status Changed. Used to notify OSPM that the control method lid device status has changed.
0x81-0xBF	Reserved.

Table 5-50 Processor Device Notification Values

Hex value	Description
0x80	Performance Present Capabilities Changed. Used to notify OSPM that the number of supported processor performance states has changed. This notification causes OSPM to re-evaluate the _PPC object. See section 8, "Processor Power and Performance State Configuration and Control," for more information.
0x81	C States Changed. Used to notify OSPM that the number or type of supported processor C States has changed. This notification causes OSPM to re-evaluate the _CST object. See section 8, "Processor Power and Performance State Configuration and Control," for more information.
0x82	Throttling Present Capabilities Changed. Used to notify OSPM that the number of supported processor throttling states has changed. This notification causes OSPM to re-evaluate the _TPC object. See section 8, "Processor Power and Performance State Configuration and Control," for more information.
0x83-0xBF	Reserved.

Table 5-51 User Presence Device Notification Values

Hex value	Description
0x80	User Presence Changed. Used to notify OSPM that a meaningful change in user presence has occurred, causing OSPM to re-evaluate the _UPD object.
0x81-0xBF	Reserved.

Table 5-52 Ambient Light Sensor Device Notification Values

Hex value	Description
0x80	ALS Illuminance Changed. Used to notify OSPM that a meaningful change in ambient light illuminance has occurred, causing OSPM to re-evaluate the _ALI object.
0x81	ALS Color Temperature Changed. Used to notify OSPM that a meaningful change in ambient light color temperature or chromacity has occurred, causing OSPM to re-evaluate the _ALT and/or _ALC objects.
0x82	ALS Response Changed. Used to notify OSPM that the set of points used to convey the ambient light response has changed, causing OSPM to re-evaluate the _ALR object.
0x83-0xBF	Reserved.

5.6.4 Device Class-Specific Objects
Most device objects are controlled through generic objects and control methods and they have generic device IDs. These generic objects, control methods, and device IDs are specified in sections 6, 7, 8, 9, 10, and 11. Section 5.6.5, "Defined Generic Objects and Control Methods," lists all the generic objects and control methods defined in this specification.
However, certain integrated devices require support for some device-specific ACPI controls. This section lists these devices, along with the device-specific ACPI controls that can be provided.
Some of these controls are for ACPI-aware devices and as such have Plug and Play IDs that represent these devices. The following table lists the Plug and Play IDs defined by the ACPI specification.
Table 5-53 ACPI Device IDs

Plug and Play ID	Description
PNP0C08	ACPI. Not declared in ACPI as a device. This ID is used by OSPM for the hardware resources consumed by the ACPI fixed register spaces, and the operation regions used by AML code. It represents the core ACPI hardware itself.
PNP0A05	Generic Container Device. A device whose settings are totally controlled by its ACPI resource information, and otherwise needs no device or bus-specific driver support. This was originally known as Generic ISA Bus Device. This ID should only be used for containers that do not produce resources for consumption by child devices. Any system resources claimed by a PNP0A05 device's _CRS object must be consumed by the container itself.
PNP0A06	Generic Container Device. This device behaves exactly the same as the PNP0A05 device. This was originally known as Extended I/O Bus. This ID should only be used for containers that do not produce resources for consumption by child devices. Any system resources claimed by a PNP0A06 device's _CRS object must be consumed by the container itself.
PNP0C09	Embedded Controller Device. A host embedded controller controlled through an ACPI-aware driver.
PNP0C0A	Control Method Battery. A device that solely implements the ACPI Control Method Battery functions. A device that has some other primary function would use its normal device ID. This ID is used when the devices primary function is that of a battery.
PNP0C0B	Fan. A device that causes cooling when "on" (D0 device state).

Table 5-53 ACPI Device IDs (continued)

Plug and Play ID	Description
PNP0C0C	Power Button Device. A device controlled through an ACPI-aware driver that provides power button functionality. This device is only needed if the power button is not supported using the fixed register space.
PNP0C0D	Lid Device. A device controlled through an ACPI-aware driver that provides lid status functionality. This device is only needed if the lid state is not supported using the fixed register space.
PNP0C0E	Sleep Button Device. A device controlled through an ACPI-aware driver that provides power button functionality. This device is optional.
PNP0C0F	PCI Interrupt Link Device. A device that allocates an interrupt connected to a PCI interrupt pin. See section 6., "Configuration," for more details.
PNP0C80	Memory Device. This device is a memory subsystem.
ACPI0001	SMBus 1.0 Host Controller. An SMBus host controller (SMB-HC) compatible with the embedded controller-based SMB-HC interface (as specified in section 12.9, "SMBus Host Controller Interface via Embedded Controller") and implementing the SMBus 1.0 Specification.
ACPI0002	Smart Battery Subsystem. The Smart battery Subsystem specified in section 10, "Power Source Devices."
ACPI0003	AC Device. The AC adapter specified in section 10, "Power Source Devices."
ACPI0004	Module Device. This device is a container object that acts as a bus node in a namespace. A Module Device without any of the _CRS, _PRS and _SRS methods behaves the same way as the Generic Container Devices (PNP0A05 or PNP0A06). If the Module Device contains a _CRS method, only these resources described in the _CRS are available for consumption by its child devices. Also, the Module Device can support _PRS and _SRS methods if _CRS is supported.
ACPI0005	SMBus 2.0 Host Controller. An SMBus host controller (SMB-HC compatible with the embedded controller-based SMB-HC interface (as specified in section 12.9, "SMBus Host Controller Interface via Embedded Controller") and implementing the SMBus 2.0 Specification.
ACPI0006	GPE Block Device. This device allows a system designer to describe GPE blocks beyond the two that are described in the FADT.
ACPI0007	Processor Device. This device provides an alternative to declaring processors using the Processor ASL statement. See section 8.4, "Declaring Processors", for more details.
ACPI0008	Ambient Light Sensor Device. This device is an ambient light sensor. See section 9.2, "Control Method Ambient Light Sensor Device".
ACPI0009	I/OxAPIC Device. This device is an I/O unit that complies with both the APIC and SAPIC interrupt models.
ACPI000A	I/O APIC Device. This device is an I/O unit that complies with the APIC interrupt model.
ACPI000B	I/O SAPIC Device. This device is an I/O unit that complies with the SAPIC interrupt model.

5.6.5 Defined Generic Objects and Control Methods
The following table lists all of the ACPI namespace objects defined in this specification and provides a reference to the defining section of the specification. Object names reserved by ACPI but defined by other specifications are also listed along with their corresponding specification reference.

Table 5-54 Defined Generic Object and Control Methods
Object		Description	Reference
_ACx		Thermal Zone object that returns active cooling policy threshold values in tenths of degrees Kelvin.	11.3.1
_ADR		Device object that evaluates to a device's address on its parent bus. For the display output device, this object returns a unique ID. (B.5.1, "_ADR - Return the Unique ID for this Device.")	6.1.1
_ALC	Object evaluates to current Ambient Light Color Chromacity		9.2.4
_ALI		The current ambient light brightness in lux (lumen per square meter).	9.2.2
_ALN		Resource data type reserved field name	17.1.8
_ALP		Ambient light sensor polling frequency in tenths of seconds.	9.2.6
_ALR		Returns a set of ambient light brightness to display brightness mappings that can be used by an OS to calibrate its ambient light policy.	9.2.5
_ALT		The current ambient light color temperature in degrees Kelvin.	9.2.3
_ALx		Thermal zone object containing a list of cooling device objects.	11.3.2
_ASI		Resource data type reserved field name	17.1.8
_BAS		Resource data type reserved field name	17.1.8
_BBN		PCI bus number setup by the BIOS	6.5.5
_BCL		Returns a buffer of bytes indicating list of brightness control levels supported.	B.6.2
_BCM		Sets the brightness level of the built-in display output device.	B.6.3
_BDN		Correlates a docking station between ACPI and legacy interfaces.	6.5.3
_BFS		Control method executed immediately following a wake event.	7.3.1
_BIF		Control Method Battery information object	10.2.2.1
_BLT		Object that conveys user's battery level threshold preferences to platform.	9.1.3
_BM		Resource data type reserved field name	17.1.8
_BMC		Powers source object used to initiate battery calibration cycles or to control the charger and whether or not a battery is powering the system.	10.2.2.7
_BMD		Power source object that returns information about the battery's capabilities and current state in relation to battery calibration and charger control features.	10.2.2.6
_BQC		Object that returns current display brightness level.	B.6.4
_BST		Control Method Battery status object	10.2.2.3
_BTM		Returns estimated runtime at the present average rate of drain, or the runtime at a specified rate.	10.2.2.5
_BTP		Sets Control Method Battery trip point	10.2.2.4
_CBA		Provides the Configuration Base Address for a PCI Express host bridge	PCI Firmware Specification, Revision 3.0 http://pcisig.com
_CID		Device identification object that evaluates to a device's Plug and Play Compatible ID list.	6.1.2
_CRS		Device configuration object that specifies a device's current resource settings, or a control method that generates such an object.	6.2.1
_CRT		Thermal zone object that returns critical trip point in tenths of degrees Kelvin.	11.3.3
_CSD		Object that conveys C-State dependencies	8.4.2.2
_CST		Processor power state declaration object	8.4.2.1
_DCK		Indicates that the device is a docking station.	6.5.2
_DCS		Returns the status of the display output device.	B.6.6
_DDC		Returns the EDID for the display output device	B.6.5
_DDN		Object that associates a logical software name (for example, COM1) with a device.	6.1.3
_DEC		Resource data type reserved field name	17.1.8
_DGS		Control method used to query the state of the output device.	B.6.7
_DIS		Device configuration control method that disables a device.	6.2.2
_DMA		Object that specifies a device's current resources for DMA transactions.	6.2.3
_DOD		Control method used to enumerate devices attached to the display adapter.	B.4.2
_DOS		Control method used to enable/disable display output switching.	B.4.1
_DSM		Generic device control method object	9.15.1
_DSS		Control method used to set display device state.	B.6.8
_DSW		Set up a device for device-only wake	7.2.1
_Exx		Control method executed as a result of a general-purpose event.	5.6.2.2, 5.6.2.2.3
_EC		Control Method used to define the offset address and Query value of an SMB-HC defined within an embedded controller device.	12.12
_EDL		Device removal object that returns a packaged list of devices that are dependent on a device.	6.3.1
_EJx		Device insertion/removal control method that ejects a device.	6.3.3
_EJD		Device removal object that evaluates to the name of a device object upon which a device is dependent. Whenever the named device is ejected, the dependent device must receive an ejection notification.	6.3.2
_FDE		Object that indicates the presence or absence of floppy disks.	9.10.1
_FDI		Object that returns floppy drive information.	9.10.2
_FDM		Control method that changes the mode of floppy drives.	9.10.3
_FIX		Object used to provide correlation between the fixed hardware register blocks defined in the FADT and the devices that implement these fixed hardware registers.	6.2.4
_GL		OS-defined Global Lock mutex object	5.7.1
_GLK		Indicates the need to acquire the Global Lock, must be acquired when accessing the device.	6.5.7
_GPD		Control method that returns which VGA device will be posted at boot	B.4.4
_GPE		1. General-Purpose Events root name space 2. Object that returns the SCI interrupt within the GPx_STS register that is connected to the EC.	5.3.1 12.11
_GRA		Resource data type reserved field name.	17.1.8
_GTF		IDE device control method to get the Advanced Technology Attachment (ATA) task file needed to re-initialize the drive to boot up defaults.	9.9.1.1
_GTM		IDE device control method to get the IDE controller timing information.	9.9.2.1.1
_GSB		Object that provides the Global System Interrupt Base for a hot-plugged I/O APIC device.	6.2.5
_GTS		Control method executed just prior to setting the sleep enable (SLP_EN) bit.	7.3.3
_HE		Resource data type reserved field name	17.1.8
_HID		Device identification object that evaluates to a device's Plug and Play Hardware ID.	6.1.4
_HOT		Object returns critical temperature when OSPM enters S4	11.3.4
_HPP		An object that specifies the Cache-line size, Latency timer, SERR enable, and PERR enable values to be used when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot.	6.2.6
_HPX		Object that provides device parameters when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot. Supersedes _HPP.	6.2.7
_IFT		IPMI Interface Type	Intelligent Platform Management Interface Specification href="http://www.intel.com/design/servers/ipmi/index.htm">http://www.intel.com/design/servers/ipmi/index.htm
_INI		Device initialization method that performs device specific initialization.	6.5.1
_INT		Resource data type reserved field name	17.1.8
_IRC		Power management object that signifies the device has a significant inrush current draw.	7.2.12
_Lxx		Control method executed as a result of a general-purpose event.	5.6.2.2, 5.6.2.2.3
_LCK		Device insertion/removal control method that locks or unlocks a device.	6.3.4
_LEN		Resource data type reserved field name	17.1.8
_LID		Object that returns the status of the Lid on a mobile system.	9.4.1
_LL		Resource data type reserved field name	17.1.8
_MAF		Resource data type reserved field name	17.1.8
_MAT		Object evaluates to a buffer of MADT APIC Structure entries.	6.2.8
_MAX		Resource data type reserved field name	17.1.8
_MEM		Resource data type reserved field name	17.1.8
_MIF		Resource data type reserved field name	17.1.8
_MIN		Resource data type reserved field name	17.1.8
_MSG		System indicator control that indicates messages are waiting.	9.1.2
_MLS		Object that provides a human readable description of a device in multiple languages.	6.1.5
_OFF		Power resource object that sets the resource off.	7.1.2
_ON		Power resource object that sets the resource on.	7.1.3
_OS		Object that evaluates to a string that identifies the operating system.	5.7.2
_OSC		Convey specific software support / capabilities to the platform allowing the platform to configure itself appropriately.	6.2.9
_OST		OSPM Status Indication	6.3.5
_PCL		Power source object that contains a list of devices powered by a power source.	10.3.2
_PCT		Processor performance control object	8.4.4.1
_PDC		Processor Driver Capabilities	8.4.1
_PIC		Control method that conveys interrupt model in use to the system firmware.	5.8.1
_PLD		Object that provides physical location description information.	6.1.6
_PPC		Control method used to determine number of performance states currently supported by the platform.	8.4.4.3
_PPE		Object provides polling interval to retrieve Corrected Platform Error information	DIG64 Corrected Platform Error Polling Specification. http://www.dig64.org/specifications
_PR		ACPI 1.0 Processor Namespace	5.3.1
_PR0		Power management object that evaluates to the device's power requirements in the D0 device state (device fully on).	7.2.7
_PR1		Power management object that evaluates to the device's power requirements in the D1 device state. Only devices that can achieve the defined D1 device state according to its given device class would supply this level.	7.2.8
_PR2		Power management object that evaluates to the device's power requirements in the D2 device state. Only devices that can achieve the defined D2 device state according to its given device class would supply this level.	7.2.9
_PRS		Device configuration object that specifies a device's possible resource settings, or a control method that generates such an object.	6.2.10
_PRT		An object that specifies the PCI interrupt Routing Table.	6.2.11
_PRW		Power management object that evaluates to the device's power requirements in order to wake the system from a system sleeping state.	7.2.10
_PS0		Power management control method that puts the device in the D0 device state. (device fully on).	7.2.2
_PS1		Power management control method that puts the device in the D1 device state.	7.2.3
_PS2		Power management control method that puts the device in the D2 device state.	7.2.4
_PS3		Power management control method that puts the device in the D3 device state (device off).	7.2.5
_PSC		Power management object that evaluates to the device's current power state.	7.2.6
_PSD		Object that conveys P-State dependencies	8.4.4.5
_PSL		Thermal zone object that returns list of passive cooling device objects.	11.3.5
_PSR		Power source object that returns present power source device.	10.3.1
_PSS		Object indicates the number of supported processor performance states.	8.4.4.2
_PSV		Thermal zone object that returns Passive trip point in tenths of degrees Kelvin.	11.3.6
_PSW		Power management control method that enables or disables the device's wake function.	7.2.11
_PTC		Object used to define a processor throttling control register.	8.4.3.1
_PTS		Control method used to notify the platform of impending sleep transition.	7.3.2
_PXM		Object used to describe proximity domains within a machine.	6.2.12
_Qxx		Embedded Controller Query and SMBus Alarm control method	5.6.2.2.3
_RBO		Resource data type reserved field name	17.1.8
_RBW		Resource data type reserved field name	17.1.8
_REG		Notifies AML code of a change in the availability of an operation region.	6.5.4
_REV		Revision of the ACPI specification that OSPM implements.	5.7.4
_RMV		Device insertion/removal object that indicates that the given device is removable.	6.3.6
_RNG		Resource data type reserved field name	17.1.8
_ROM		Control method used to get a copy of the display devices' ROM data.	B.4.3
_RT		Resource Type field of the QWordSpace, DWordSpace or WordSpace address descriptors	17.1.8
_RTV		Object indicates whether temperature values are relative or absolute.	11.3.7
_RW		Resource data type reserved field name	17.1.8
_S0		Power management package that defines system \_S0 state mode.	7.3.4.1
_S1		Power management package that defines system \_S1 state mode.	7.3.4.2
_S2		Power management package that defines system \_S2 state mode.	7.3.4.3
_S3		Power management package that defines system \_S3 state mode.	7.3.4.4
_S4		Power management package that defines system \_S4 state mode.	7.3.4.5
_S5		Power management package that defines system \_S5 state mode.	7.3.4.6
_S1D		Highest D-state supported by the device in the S1 state.	7.2.13
_S2D		Highest D-state supported by the device in the S2 state.	7.2.14
_S3D		Highest D-state supported by the device in the S3 state.	7.2.15
_S4D		Highest D-state supported by the device in the S4 state.	7.2.16
_S0W		Lowest D-state supported by the device in the S0 state which can wake the device	7.2.17
_S1W		Lowest D-state supported by the device in the S1 state which can wake the system	7.2.18
_S2W		Lowest D-state supported by the device in the S2 state which can wake the system	7.2.19
_S3W		Lowest D-state supported by the device in the S3 state which can wake the system	7.2.20
_S4W		Lowest D-state supported by the device in the S4 state which can wake the system	7.2.21
_SB		System bus scope	5.3.1
_SBS		Smart Battery object that returns Smart Battery configuration.	10.1.2
_SCP		Thermal zone object that sets user cooling policy (Active or Passive).	11.3.8
_SDD		Control method that informs the platform of the type of device attached to a SATA port.	9.9.3.3.1
_SEG		Evaluates to the PCI Segment Group number.	6.5.6
_SHR		Resource data type reserved field name	17.1.8
_SI		System indicators scope	9.1
_SIZ		Resource data type reserved field name	17.1.8
_SLI		Object that provides updated distance information for a system locality.	6.2.13
_SPD		Control method used to update which video device will be posted at boot.	B.4.5
_SRS		Device configuration control method that sets a device's settings.	6.2.14
_SRV		IPMI Spec Revision	Intelligent Platform Management Interface Specification href="http://www.intel.com/design/servers/ipmi/index.htm">http://www.intel.com/design/servers/ipmi/index.htm
_SST		System indicator control method that indicates the system status.	9.1.1
_STA		1. Device insertion/removal control method that returns a device's status. 2. Power resource object that evaluates to the current on or off state of the Power Resource.	6.3.7 7.1.4
_STM		IDE device control method used to set the IDE controller transfer timings.	9.9.2.1.2
_STR		Object evaluates to a Unicode string to describe a device.	6.1.7
_SUN		Object that evaluates to the slot unique ID number for a slot.	6.1.8
_SWS		Object that returns the source event that caused the system to wake.	7.3.5
_T_x		Reserved for use by the ASL compiler.	17.2.1.1
_TC1		Thermal zone object that contains thermal constant for Passive cooling.	11.3.9
_TC2		Thermal zone object that contains thermal constant for Passive cooling.	11.3.10
_TMP		Thermal zone object that returns current temperature in tenths of degrees Kelvin.	11.3.11
_TPC		Object evaluates to the current number of supported throttling states.	8.4.3.3
_TPT		Control method invoked when a devices' embedded temperature sensor crosses a temperature trip point.	11.3.12
_TRA		Resource data type reserved field name	17.1.8
_TRS		Resource data type reserved field name	17.1.8
_TRT		Object provides thermal relationship information between platform devices.	11.3.13
_TSD		Object that conveys Throttling State dependencies	8.4.3.4
_TSF		Type-Specific Flags fields in a Word, DWord or QWord address space descriptor	17.1.8
_TSP		Thermal zone object that contains thermal sampling period for Passive cooling.	11.3.14
_TST		Object returns minimum temperature separation for device's programmable temperature trip points.	11.3.15
_TSS		Object evaluates to a table of support throttling states.	8.4.3.2
_TTP		Resource data type reserved field name	17.1.8
\_TTS		Control method used to prepare to sleep and run once awakened	7.3.6
_TYP		Resource data type reserved field name	17.1.8
_TZ		ACPI 1.0 thermal zone scope	5.3.1
_TZD		Object evaluates to a package of device names associated with a Thermal Zone.	11.3.16
_TZM		Object indicates the thermal zone of which a device is a member.	11.3.17
_TZP		Thermal zone polling frequency in tenths of seconds.	11.3.18
_UID		Device identification object that specifies a device's unique persistent ID, or a control method that generates it.	6.1.9
_UPC		Object provides USB port capabilities information..	9.14
_UPD		Object that returns user presence information.	9.17.1
_UPP		Object evaluates to user presence polling interval.	9.17.2
_VPO		Returns 32-bit integer indicating the video post options.	B.4.6
\_WAK		Power management control method run once system is awakened.	7.3.7

5.7 Predefined Objects
The AML interpreter of an ACPI compatible operating system supports the evaluation of a number of predefined objects. The objects are considered "built in" to the AML interpreter on the target operating system.
A list of predefined object names are shown in the following table.
Table 5-55 Predefined Object Names

Name	Description
\_GL	Global Lock
\_OS	Name of the operating system
\_OSI	Operating System Interface support
\_REV	Revision of the ACPI specification that OSPM implements.

5.7.1   \_GL (Global Lock Mutex)
This predefined object is a Mutex object that behaves like a Mutex as defined in section 17.5.79, "Mutex (Declare Synchronization/Mutex Object)," with the added behavior that acquiring this Mutex also acquires the shared environment Global Lock defined in section 5.2.10.1, "Global Lock." This allows Control Methods to explicitly synchronize with the Global Lock if necessary .
5.7.2   \_OSI (Operating System Interfaces)
This object provides the platform with the ability to query OSPM to determine the set of ACPI related interfaces, behaviors, or features that the operating system supports.
The _OSI method has one argument and one return value argument is an OS vendor defined string representing a set of OS interfaces and behaviors or an ACPI defined string representing an operating system and an ACPI feature group of the form, "OSVendorString-FeatureGroupString".
Syntax
_OSI (Interface)=> BooleanResult
Arguments
Interface: String | String "-" String
Specifies the OS interface / behavior compatibility string or the Feature Group String, as defined in Table 5-57, or the OS Vendor String Prefix-OS Vendor Specific String. OS Vendor String Prefixes are defined in Table 5-56.
Return Value
BooleanResult: DWordConst
A return value of 0x00000000 indicates that interface, behavior, feature, is not supported.
A return value of 0xFFFFFFFF indicates that interface, behavior, feature, is supported.

OSPM may indicate support for multiple OS interface / behavior strings if the operating system supports the behaviors. For example, a newer version of an operating system may indicate support for strings from all or some of the prior versions of that operating system.
_OSI provides the platform with the ability to support new operating system versions and their associated features when they become available. OSPM can choose to expose new functionality based on the _OSI argument string. That is, OSPM can use the strings passed into _OSI to ensure compatibility between older platforms and newer operating systems by maintaining known compatible behavior for a platform. As such, it is recommended that _OSI be evaluated by the \_SB.INI control method so that platform compatible behavior or features are available early in operating system initialization.
Since feature group functionality may be dependent on OSPM implementation, it may be required that OS vendor-defined strings be checked before feature group strings.
Platform developers should consult OS vendor specific information for OS vendor defined strings representing a set of OS interfaces and behaviors. ACPI defined strings representing an operating system and an ACPI feature group are listed in the following tables.

Table 5-56   Operating System Vendor Strings

Operating System Vendor String Prefix	Description
"FreeBSD"	Free BSD
"HP-UX"	HP Unix Operating Environment
"Linux"	GNU/Linux Operating system
"OpenVMS"	HP OpenVMS Operating Environment
"Windows"	Microsoft Windows

Table 5-57 Feature Group Strings

Feature Group String	Description
"Module Device"	OSPM supports the declaration of module device (ACPI0004) in the namespace and will enumerate objects under the module device scope.
"Processor Device"	OSPM supports the declaration of processors in the namespace using the ACPI0007 processor device HID.
"3.0 Thermal Model"	OSPM supports the extensions to the ACPI thermal model in Revision 3.0.
"Extended Address Space Descriptor"	OSPM supports the Extended Address Space Descriptor
"3.0 _SCP Extensions"	OSPM evaluates _SCP with the additional acoustic limit and power limit arguments defined in ACPI 3.0.

_OSI Example ASL using OS vendor defined string:

Scope (_SB)          //Scope
{
    Name (TOOS, 0)       // Global variable for type of OS.
    // This methods sets the "TOOS"variable depending on the type of OS
    // installed on the system.
    // TOOS = 1                     // Windows 98 & SE
    // TOOS = 2                     // Windows Me.
    // TOOS = 3                     // Windows 2000 OS or above version.
    // TOOS = 4                     // Windows XP OS or above version.
    Method (_INI)
    {
        If (CondRefOf (_OSI,Local0))
        {
           If (\_OSI ("Windows 2001"))
           {
               Store(4, TOOS)
           }
        }
        Else
        {
           Store (\_OS, local0)
           If (LEqual (local0, "Microsoft Windows NT"))
           {
               Store (3, TOOS)
           }
           ElseIf (LEqual (Local0, "Microsoft Windows"))
           {
              Store (1, TOOS)
           }
           ElseIf (LEqual (Local0, "Microsoft WindowsME:Millennium Edition"))
           {
              Store (2, TOOS)
           }
       }
    }
}

_OSI Example ASL using an ACPI defined string:
Scope (_SB) {
   Method (_INI) {
If (CondRefOf (_OSI,Local0)) {
If (\_OSI ("Module Device")) {
       //Expose PCI Root Bridge under Module Device
LoadTable("OEM1", "OEMID", "Table1",,,)}
Else {
// Expose PCI Root Bridge under \_SB – OS does not support Module Device
       LoadTable("OEM1", "OEMID", "Table2",,,)}
}
Else {
       // Default Behavior
    LoadTable("OEM1", "OEMID", "Table2",,,)}
   } //_INI Method
} //_SB scope

DefinitionBlock ("MD1SSDT.aml","OEM1",0x02,
    "OEMID", "Table1", 0) {
    Scope(\_SB) {
      Device (\_SB.NOD0) {
        Name (_HID, "ACPI0004") // Module device
        Name (_UID, 0)
        Name (_PRS, ResourceTemplate() {
        Method (_SRS, 1) { ... }
        Method (_CRS, 0) { ... }
        Device (PCI0) { // PCI Root Bridge
         Name (_HID, EISAID("PNP0A03"))
         Name (_UID, 0)
         Name (_BBN, 0x00)
         Name (_PRS, ResourceTemplate () {...})
       } // end of PCI Root Bridge
     } // end of Module device
   } // end of \_SB Scope
} // end of Definition Block

DefinitionBlock ("MD1SSDT.aml","OEM1",0x02,
    "OEMID", "Table2", 0) {
   Scope(\_SB) {
     Device (PCI0) { // PCI Root Bridge
        Name (_HID, EISAID("PNP0A03"))
        Name (_UID, 0)
        Name (_BBN, 0x00)
        Name (_PRS, ResourceTemplate () {...})
     } // end of PCI Root Bridge
   } // end of \_SB Scope
} // end of Definition Block
5.7.3   \_OS (OS Name Object)
This predefined object evaluates to a string that identifies the operating system. In robust OSPM implementations, \_OS evaluates differently for each OS release. This may allow AML code to accommodate differences in OSPM implementations. This value does not change with different revisions of the AML interpreter.
5.7.4   \_REV (Revision Data Object)
This predefined object evaluates to the revision of the ACPI Specification that the specified \_OS implements as a DWORD. Larger values are newer revisions of the ACPI specification.
5.8   System Configuration Objects
5.8.1   _PIC Method
The \_PIC optional method is to report to the BIOS the current interrupt model used by the OS. This control method returns nothing. The argument passed into the method signifies the interrupt model OSPM has chosen, PIC mode, APIC mode, or SAPIC mode. Notice that calling this method is optional for OSPM. If the method is never called, the BIOS must assume PIC mode. It is important that the BIOS save the value passed in by OSPM for later use during wake operations.
_PIC(x):
_PIC(0)             =>PIC Mode
_PIC(1)            =>APIC Mode
_PIC(2)                         =>SAPIC Mode
_PIC(3-n)           =>Reserved

6   Configuration
This section specifies the objects OSPM uses to configure devices. There are three types of configuration objects:
·      Device identification objects associate platform devices with Plug and Play IDs.
·      Device configuration objects declare and configure hardware resources and characteristics for devices enumerated via ACPI.
·      Device insertion and removal objects provide mechanisms for handling dynamic insertion and removal of devices.
This section also defines the ACPI device–resource descriptor formats. Device–resource descriptors are used as parameters by some of the device configuration objects.
6.1   Device Identification Objects
Device identification objects associate each platform device with a Plug and Play device ID for each device. All the device identification objects are listed Table 6-1:
Table 6-1   Device Identification Objects

Object	Description
_ADR	Object that evaluates to a device's address on its parent bus.
_CID	Object that evaluates to a device's Plug and Play-compatible ID list.
_DDN	Object that associates a logical software name (for example, COM1) with a device.
_HID	Object that evaluates to a device's Plug and Play hardware ID.
_MLS	Object that provides a human readable description of a device in multiple languages.
_PLD	Object that provides physical location description information.
_SUN	Object that evaluates to the slot-unique ID number for a slot.
_STR	Object that contains a Unicode identifier for a device.
_UID	Object that specifies a device's unique persistent ID, or a control method that generates it.

For any device that is not on an enumerable type of bus (for example, an ISA bus), OSPM enumerates the devices' Plug and Play ID(s) and the ACPI BIOS must supply an _HID object (plus an optional _CID object) for each device to enable OSPM to do that. For devices on an enumerable type of bus, such as a PCI bus, the ACPI system must identify which device on the enumerable bus is identified by a particular Plug and Play ID; the ACPI BIOS must supply an _ADR object for each device to enable this. A device object must contain either an _HID object or an _ADR object, but can contain both.
If any of these objects are implemented as control methods, these methods may depend on operation regions. Since the control methods may be evaluated before an operation region provider becomes available, the control method must be structured to execute in the absence of the operation region provider. (_REG methods notify the BIOS of the presence of operation region providers.) When a control method cannot determine the current state of the hardware due to a lack of operation region provider, it is recommended that the control method should return the condition that was true at the time that control passed from the BIOS to the OS. (The control method should return a default, boot value).
6.1.1 _ADR (Address)
This object is used to supply OSPM with the address of a device on its parent bus. An _ADR object must be used when specifying the address of any device on a bus that has a standard enumeration algorithm (see 3.7, "Configuration and Plug and Play", for the situations when these devices do appear in the ACPI name space).
An _ADR object can be used to provide capabilities to the specified address even if a device is not present. This allows the system to provide capabilities to a slot on the parent bus.
OSPM infers the parent bus from the location of the _ADR object's device package in the ACPI namespace. For more information about the positioning of device packages in the ACPI namespace, see section 17.5.28, "Device–Declare Bus/Device Package."
_ADR object information must be static and can be defined for the following bus types listed in Table 6-2.
Table 6-2 _ADR Object Address Encodings

BUS	Address encoding
EISA	EISA slot number 0–F
Floppy Bus	Drive select values used for programming the floppy controller to access the specified INT13 unit number. The _ADR Objects should be sorted based on drive select encoding from 0-3.
IDE Controller	0–Primary Channel, 1–Secondary Channel
IDE Channel	0–Master drive, 1–Slave drive
Intel� High Definition Audio	High word – SDI (Serial Data In) ID of the codec that contains the function group. Low word – Node ID of the function group.
PCI	High word–Device #, Low word–Function #. (for example, device 3, function 2 is 0x00030002). To refer to all the functions on a device #, use a function number of FFFF).
PCMCIA	Socket #; 0–First Socket
PC CARD	Socket #; 0–First Socket
Serial ATA	SATA Port: High word—Root port #, Low word—port number off of a SATA port multiplier, or 0xFFFF if no port multiplier attached. (For example, root port 2 would be 0x0002FFFF. If instead a port multiplier had been attached to root port 2, the ports connected to the multiplier would be encoded 0x00020000, 0x00020001, etc.) The value 0xFFFFFFFF is reserved.
SMBus	Lowest Slave Address
USB Root HUB	Only one child of the host controller. It must have an _ADR of 0. No other children or values of _ADR are allowed.
USB Ports	Port number (1-n)

6.1.2   _CID (Compatible ID)
This optional object is used to supply OSPM with a device's Plug and Play-Compatible Device ID. Use _CID objects when a device has no other defined hardware standard method to report its compatible IDs.
A _CID object evaluates to either:
· A single Compatible Device ID
· A package of Compatible Device IDs for the device — in the order of preference, highest preference first.
Each Compatible Device ID must be either:
· A valid HID value (a 32-bit compressed EISA type ID or a string such as "ACPI0004").
· A string that uses a bus-specific nomenclature. For example, _CID can be used to specify the PCI ID. The format of a PCI ID string is one of the following:

"PCI\CC_ccss"
"PCI\CC_ccsspp"
"PCI\VEN_vvvv&DEV_dddd&SUBSYS_ssssssss&REV_rr"
"PCI\VEN_vvvv&DEV_dddd&SUBSYS_ssssssss"
"PCI\VEN_vvvv&DEV_dddd&REV_rr"
"PCI\VEN_vvvv&DEV_dddd"

Where:
cc         –hexadecimal representation of the Class Code byte
ss         –hexadecimal representation of the Subclass Code byte
pp         –hexadecimal representation of the Programming Interface byte
vvvv     –hexadecimal representation of the Vendor ID
dddd     –hexadecimal representation of the Device ID
ssssssss –hexadecimal representation of the Subsystem ID
rr          –hexadecimal representation of the Revision byte
A compatible ID retrieved from a _CID object is only meaningful if it is a non-NULL value.
Example ASL:

    Device (XYZ) {
       Name (_HID, EISAID ("PNP0303"))         // PC Keyboard Controller
       Name (_CID, EISAID ("PNP030B"))
    }
6.1.3   _DDN (DOS Device Name)
This object is used to associate a logical name (for example, COM1) with a device. This name can be used by applications to connect to the device.
6.1.4   _HID (Hardware ID)
This object is used to supply OSPM with the device's Plug and Play hardware ID.[8] When describing a platform, use of any _HID objects is optional. However, a _HID object must be used to describe any device that will be enumerated by OSPM. OSPM only enumerates a device when no bus enumerator can detect the device ID. For example, devices on an ISA bus are enumerated by OSPM. Use the _ADR object to describe devices enumerated by bus enumerators other than OSPM.
A _HID object evaluates to either a numeric 32-bit compressed EISA type ID or a string. If a string, the format must be an alphanumeric PNP or ACPI ID with no asterisk or other leading characters.
A valid PNP ID must be of the form "AAA####" where A is an uppercase letter and # is a hex digit. A valid ACPI ID must be of the form "ACPI####" where # is a hex digit.
Example ASL:
    Name (_HID, EISAID ("PNP0C0C"))     // Control-Method Power Button
    Name (_HID, EISAID ("INT0800"))     // Firmware Hub
    Name (_HID, "ACPI0003")             // AC adapter device
6.1.5    _MLS (Multiple Language String)
The _MLS object provides OSPM a human readable description of a device in multiple languages. This information may be provided to the end user when the OSPM is unable to get any other information about this device. Although this functionality is also provided by the _STR object, _MLS expands that functionality and provides vendors with the capability to provide multiple strings in multiple languages. The _MLS object evaluates to a package of packages. Each sub-package consists of a Language identifier and corresponding unicode string for a given locale. Specifying a language identifier allows OSPM to easily determine if support for displaying the Unicode string is available. OSPM can use this information to determine whether or not to display the device string, or which string is appropriate for a user's preferred locale.
It is assumed that OSPM will always support the primary English locale to accommodate English embedded in a non-English string, such as a brand name.
If OSPM doesn't support the specific sub-language ID it may choose to use the primary language ID for displaying device text.
The package is of the following format:

Package() {         Package(){Language ID, Unicode device description string},
Package(){Language ID, Unicode device description string},
      �
}
Language ID := string := a string identifying the language. This string follows the format specified in RFC 3066. Additionally, the following strings are supported:
Unicode device description string := Unicode (UTF-16) string . The Unicode device description string contains the language-specific description of the device corresponding to the LanguageID.
Example ASL:

Device (XYZ) {
Name (_ADR, 0x00020001)
Name ( _MLS, Package(){ Package(2){"en", Unicode("ACME super DVD controller")}})
}
In addition to supporting the existing strings in RFC 3066, Table 6-3 lists aliases that are also supported.
Table 6-3   Additional Alias Strings

RFC String	Supported Alias String
zh-Hans	zh-chs
zh-Hant	zh-cht

6.1.6 _PLD (Physical Device Location)
This optional object is a method that conveys to OSPM a general description of the physical location of a device's external connection point. The _PLD may be child object for any ACPI Namespace object the system wants to describe. This information can be used by system software to describe to the user which specific connector or device input mechanism may be used for a given task or may need user intervention for correct operation. The _PLD should only be evaluated when its parent device is present as indicated by the device's presence mechanism (i.e. _STA or other)

An externally expose device connection point can reside on any surface of a system's housing. The _PLD method returns data to describe the general location of where the device's connection point resides. One physical device may have several connection points. A _PLD describes a single device connection point.

All data bits are interpreted as though the user is facing the front of the system. The data bits also assume that if the system is capable of opening up like a laptop that the device may exist on the base of the laptop system or on the lid. In the case of the latter, the "Lid" bit (described below) should be set indicating the device connection point is on the lid. If the device is on the lid, the description describes the device's connection point location when the system is opened with the lid up. If the device connection point is not on the lid, then the description describes the device's connection point location when the system with the lid closed.

The location of a device connection point may change as a result of the system connecting or disconnecting to a docking station or a port replicator. As such, Notify event of type 0x8 will cause OSPM to re-evaluate the _PLD object residing under the particular device notified. If a platform is unable to detect the change of connecting or disconnecting to a docking station or port replicator, a _PLD object should not be used to describe the device connection points that will change location after such an event.

This method returns a package containing, a single or multiple buffer entries. At least one buffer entry must be returned using the bit definitions below.

Arguments:
None

Buffer 0 Result Code:

Bit 6:0 – Revision. The current revision is 0x1; all other values are reserved.
Bit 7 – Ignore Color. If this bit is set, the Color field is ignored, as the color is unknown.
Bit 31:8 – Color – 24bit RGB value for the color of the device connection point.
Bit 47:32 – Wid^th: Describes, in millimeters, the width (widest point) of the device connection point.
Bit 63:48 – Height: Describes, in millimeters, the height of the device connection.

Bit 64 – User Visible: Set if the device connection point can be seen by the user.
Bit 65 – Dock: Set if the device connection point resides in a docking station or port replicator.
Bit 66 – Lid: Set if this device connection point resides on the lid of laptop system.

Bit 69:67 – Panel: Describes which panel surface of the system's housing the device connection point resides on.
      0 – Top
      1 – Bottom
      2 – Left
      3 – Right
      4 – Front
      5 – Back
      6 – Unknown (Vertical Position and Horizontal Position will be ignored)

Bit 71:70 – Vertical Position on the panel where the device connection point resides.
      0 – Upper
      1 – Center
      2 – Lower

Bit 73:72 – Horizontal Position on the panel where the device connection point resides.
      0 – Left
      1 – Center
      2 – Right

Bit 77:74 – Shape: Describes the shape of the device connection point.
0 – Round
1 – Oval
2 – Square
3 – Vertical Rectangle
4 – Horizontal Rectangle
5 – Vertical Trapezoid
6 – Horizontal Trapezoid
7 – Unknown

Bit 78 – Group Orientation: if Set, indicates vertical grouping, otherwise horizontal is assumed.
Bit 86:79 – Group Token: Unique numerical value identifying a group.
Bit 94:87 – Group Position: Identifies this device connection point's position in the group (i.e. 1^st, 2^nd)
Bit 95 – Bay: Set if describing a device in a bay or if device connection point is a bay.
Bit 96 – Ejectable: Set if the device is ejectable. Indicates ejectability in the absence of _EJx objects.
Bit 97 – OSPM Ejection required: Set if OSPM needs to be involved with ejection process. User-operated physical hardware ejection is not possible. Bit 105:98 – Cabinet Number. For single cabinet system, this field is always 0.
Bit 113:106 – Card cage Number. For single card cage system, this field is always 0.
Bit 127:114 – Reserved, must contain a value of 0.

All additional buffer entries returned, may contain OEM specific data, but must begin in a {GUID, data} pair. These additional data may provide complimentary physical location information specific to certain systems or class of machines.
Buffers 1 – N Result Code (Optional):

Buffer 1 Bit 127:0 – GUID 1
Buffer 2 Bit 127:0 – Data 1
Buffer 3 Bit 127:0 – GUID 2
Buffer 4 Bit 127:0 – Data 2
��
6.1.7 _STR (String)

The _STR object evaluates to a Unicode string that may be used by an OS to provide information to an end user describing the device. This information is particularly valuable when no other information is available.
Example ASL:

    Device (XYZ) {
       Name (_ADR, 0x00020001)
       Name (_STR, Unicode ("ACME super DVD controller"))
    }
Then, when all else fails, an OS can use the info included in the _STR object to describe the hardware to the user.
6.1.8   _SUN (Slot User Number)
_SUN is an object that evaluates to the slot-unique ID number for a slot. _SUN is used by OSPM UI to identify slots for the user example, this can be used for battery slots, PCI slots, PCMCIA slots, or swappable bay slots to inform the user of what devices are in each slot. _SUN evaluates to an integer that is the number to be used in the user interface. This number is required to be unique among the slots of the same type. It is also recommended that this number match the slot number printed on the physical slot whenever possible.
6.1.9   _UID (Unique ID)
This object provides OSPM with a logical device ID that does not change across reboots. This object is optional, but is required when the device has no other way to report a persistent unique device ID. The _UID must be unique across all devices with either a common _HID or _CID. This is because a device needs to be uniquely identified to the OSPM, which may match on either a _HID or a _CID to identify the device. The uniqueness match must be true regardless of whether the OSPM uses the _HID or the _CID. OSPM typically uses the unique device ID to ensure that the device-specific information, such as network protocol binding information, is remembered for the device even if its relative location changes. For most integrated devices, this object contains a unique identifier.
A _UID object evaluates to either a numeric value or a string.

6.2 Device Configuration Objects
This section describes objects that provide OSPM with device specific information and allow OSPM to configure device operation and resource utilization.
OSPM uses device configuration objects to configure hardware resources for devices enumerated via ACPI. Device configuration objects provide information about current and possible resource requirements, the relationship between shared resources, and methods for configuring hardware resources.
Note: these objects must only be provided for devices that cannot be configured by any other hardware standard such as PCI, PCMCIA, and so on.
When OSPM enumerates a device, it calls _PRS to determine the resource requirements of the device. It may also call _CRS to find the current resource settings for the device. Using this information, the Plug and Play system determines what resources the device should consume and sets those resources by calling the device's _SRS control method.
In ACPI, devices can consume resources (for example, legacy keyboards), provide resources (for example, a proprietary PCI bridge), or do both. Unless otherwise specified, resources for a device are assumed to be taken from the nearest matching resource above the device in the device hierarchy.
Some resources, however, may be shared amongst several devices. To describe this, devices that share a resource (resource consumers) must use the extended resource descriptors (0x7-0xA) described in section 6.4.3, "Large Resource Data Type." These descriptors point to a single device object (resource producer) that claims the shared resource in its _PRS. This allows OSPM to clearly understand the resource dependencies in the system and move all related devices together if it needs to change resources. Furthermore, it allows OSPM to allocate resources only to resource producers when devices that consume that resource appear.
The device configuration objects are listed in Table 6-4.
Table 6-4 Device Configuration Objects

Object	Description
_CRS	Object that specifies a device's current resource settings, or a control method that generates such an object.
_DIS	Control method that disables a device.
_DMA	Object that specifies a device's current resources for DMA transactions.
_FIX	Object used to provide correlation between the fixed-hardware register blocks defined in the FADT and the devices that implement these fixed-hardware registers.
_GSB	Object that provides the Global System Interrupt Base for a hot-plugged I/O APIC device.
_HPP	Object that specifies the cache-line size, latency timer, SERR enable, and PERR enable values to be used when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot.
_HPX	Object that provides device parameters when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot. Supersedes _HPP.
_MAT	Object that evaluates to a buffer of MADT APIC Structure entries.
_OSC	An object OSPM evaluates to convey specific software support / capabilities to the platform allowing the platform to configure itself appropriately.
_PRS	An object that specifies a device's possible resource settings, or a control method that generates such an object.
_PRT	Object that specifies the PCI interrupt routing table.
_PXM	Object that specifies a proximity domain for a device.
_SLI	Object that provides updated distance information for a system locality.
_SRS	Control method that sets a device's settings.

6.2.1   _CRS (Current Resource Settings)
This required object evaluates to a byte stream that describes the system resources currently allocated to a device. Additionally, a bus device must supply the resources that it decodes and can assign to its children devices. If a device is disabled, then _CRS returns a valid resource template for the device, but the actual resource assignments in the return byte stream are ignored. If the device is disabled when _CRS is called, it must remain disabled.
The format of the data contained in a _CRS object follows the formats defined in section 6.4, "Resource Data Types for ACPI," a compatible extension of the formats specified in the PNPBIOS specification.[9] The resource data is provided as a series of data structures, with each of the resource data structures having a unique tag or identifier. The resource descriptor data structures specify the standard PC system resources, such as memory address ranges, I/O ports, interrupts, and DMA channels.
Arguments:
None
Result Code:
Byte stream
6.2.2   _DIS (Disable)
This control method disables a device. When the device is disabled, it must not be decoding any hardware resources. Prior to running this control method, OSPM will have already put the device in the D3 state.
When a device is disabled via the _DIS, the _STA control method for this device must return with the Disabled bit set.
Arguments:
None
Result Code:
None
6.2.3   _DMA (Direct Memory Access)
This optional object returns a byte stream in the same format as a _CRS object. _DMA is only defined under devices that represent buses. It specifies the ranges the bus controller (bridge) decodes on the child-side of its interface. (This is analogous to the _CRS object, which describes the resources that the bus controller decodes on the parent-side of its interface.) Any ranges described in the resources of a _DMA object can be used by child devices for DMA or bus master transactions.
The _DMA object is only valid if a _CRS object is also defined. OSPM must re-evaluate the _DMA object after an _SRS object has been executed because the _DMA ranges resources may change depending on how the bridge has been configured.
If the _DMA object is not present for a bus device, the OS assumes that any address placed on a bus by a child device will be decoded either by a device on the bus or by the bus itself, (in other words, all address ranges can be used for DMA).
For example, if a platform implements a PCI bus that cannot access all of physical memory, it has a _DMA object under that PCI bus that describes the ranges of physical memory that can be accessed by devices on that bus.

A _DMA object is not meant to describe any "map register" hardware that is set up for each DMA transaction. It is meant only to describe the DMA properties of a bus that cannot be changed without reevaluating the _SRS method.
Arguments:
None
Result Code:
Byte stream
_DMA Example ASL:

Device(BUS0)
{

//
// The _DMA method returns a resource template describing the
// addresses that are decoded on the child side of this
// bridge. The contained resource descriptors thus indicate
// the address ranges that bus masters living below this
// bridge can use to send accesses through the bridge toward a
// destination elsewhere in the system (e.g. main memory).
//
// In our case, any bus master addresses need to fall between
// 0 and 0x80000000 and will have 0x200000000 added as they
// cross the bridge. Furthermore, any child-side accesses
// falling into the range claimed in our _CRS will be
// interpreted as a peer-to-peer traffic and will not be
// forwarded upstream by the bridge.
//
// Our upstream address decoder will only claim one range from
// 0x20000000 to 0x5fffffff in the _CRS. Therefore _DMA
// should return two QWORDMemory descriptors, one describing
// the range below and one describing the range above this
// "peer-to-peer" address range.
//

Method(_DMA, ResourceTemplate()
{
QWORDMemory(
ResourceConsumer,
PosDecode, // _DEC
MinFixed, // _MIF
MaxFixed, // _MAF
Prefetchable, // _MEM
ReadWrite, // _RW
0, // _GRA
0, // _MIN
0x1fffffff, // _MAX
0x200000000, // _TRA
0x20000000, // _LEN
,
,
,
)
QWORDMemory(
ResourceConsumer,
PosDecode, // _DEC
MinFixed, // _MIF
MaxFixed, // _MAF
Prefetchable, // _MEM
ReadWrite, // _RW
0, // _GRA
0x60000000, // _MIN
0x7fffffff, // _MAX
0x200000000, // _TRA
0x20000000, // _LEN
,
,
,
)
})
}

6.2.4 _FIX (Fixed Register Resource Provider)
This optional object is used to provide a correlation between the fixed-hardware register blocks defined in the FADT and the devices in the ACPI namespace that implement these fixed-hardware registers. This object evaluates to a package of Plug and Play-compatible IDs (32-bit compressed EISA type IDs) that correlate to the fixed-hardware register blocks defined in the FADT. The device under which _FIX appears plays a role in the implementation of the fixed-hardware (for example, implements the hardware or decodes the hardware's address). _FIX conveys to OSPM whether a given device can be disabled, powered off, or should be treated specially by conveying its role in the implementation of the ACPI fixed-hardware register interfaces. This object takes no arguments.
The _CRS object describes a device's resources. That _CRS object may contain a superset of the resources in the FADT, as the device may actually decode resources beyond what the FADT requires. Furthermore, in a machine that performs translation of resources within I/O bridges, the processor-relative resources in the FADT may not be the same as the bus-relative resources in the _CRS.
Each of fields in the FADT has its own corresponding Plug and Play ID, as shown below:
· PNP0C20 - SMI_CMD
· PNP0C21 - PM1a_EVT_BLK / X_ PM1a_EVT_BLK
· PNP0C22 - PM1b_EVT_BLK / X_PM1b_EVT_BLK
· PNP0C23 - PM1a_CNT_BLK / X_PM1a_CNT_BLK
· PNP0C24 - PM1b_CNT_BLK / X_ PM1b_CNT_BLK
· PNP0C25 - PM2_CNT_BLK / X_ PM2_CNT_BLK
· PNP0C26 - PM_TMR_BLK / X_ PM_TMR_BLK
· PNP0C27 - GPE0_BLK / X_GPE0_BLK
· PNP0C28 - GPE1_BLK / X_ GPE1_BLK
· PNP0B00 – FIXED_RTC
· PNP0B01 – FIXED_RTC
· PNP0B02 – FIXED_RTC

Example ASL for _FIX usage:

Scope(\_SB) {
    Device(PCI0) {         // Root PCI Bus
       Name(_HID, EISAID("PNP0A03"))       // Need _HID for root device
       Name(_ADR,0)                    // Device 0 on this bus
       Method (_CRS,0){                 // Need current resources for root device
           // Return current resources for root bridge 0
       }
       Name(_PRT, Package(){            // Need PCI IRQ routing for PCI bridge
           // Package with PCI IRQ routing table information
       })
       Name(_FIX, Package(1) {
           EISAID("PNP0C25")}               // PM2 control ID
       )

       Device (PX40) {                 // ISA
           Name(_ADR,0x00070000)
           Name(_FIX, Package(1) {
              EISAID("PNP0C20")}           // SMI command port
           )
           Device (NS17) {              // NS17 (Nat. Semi 317, an ACPI part)
              Name(_HID, EISAID("PNP0C02"))
              Name(_FIX, Package(3) {
                  EISAID("PNP0C22"),       // PM1b event ID
                  EISAID("PNP0C24"),       // PM1b control ID
                  EISAID("PNP0C28")}        // GPE1 ID
           }
       }   // end PX40

       Device (PX43) {                  // PM Control
           Name(_ADR,0x00070003)
           Name(_FIX, Package(4) {
              EISAID("PNP0C21"),           // PM1a event ID
              EISAID("PNP0C23"),           // PM1a control ID
              EISAID("PNP0C26"),           // PM Timer ID
              EISAID("PNP0C27")}           // GPE0 ID
           )

       }   // end PX43
    } // end PCI0
}   // end scope SB

6.2.5 _GSB (Global System Interrupt Base)
_GSB is an optional object that evaluates to an integer that corresponds to the Global System Interrupt Base for the corresponding I/O APIC device. The I/O APIC device may either be bus enumerated (e.g. as a PCI device) or enumerated in the name space as described in Section 9.18,"I/O APIC Device". Any I/O APIC device that either supports hot-plug or is not described in the MADT must contain a _GSB object.
If the I/O APIC device also contains a _MAT object, OSPM evaluates the _GSB object first before evaluating the _MAT object. By providing the Global System Interrupt Base of the I/O APIC, this object enables OSPM to process only the _MAT entries that correspond to the I/O APIC device. See section 6.2.8, "_MAT (Multiple APIC Table Entry)". Since _MAT is allowed to potentially return all the MADT entries for the entire platform, _GSB is needed in the I/O APIC device scope to enable OSPM to identify the entries that correspond to that device.
If an I/O APIC device is activated by a device-specific driver, the physical address used to access the I/O APIC will be exposed by the driver and cannot be determined from the _MAT object. In this case, OSPM cannot use the _MAT object to determine the Global System Interrupt Base corresponding to the I/O APIC device and hence requires the _GSB object.
Arguments:
None
Results:
64-bit value representing the Global System Interrupt Base for the corresponding I/OAPIC device as defined in Section 5.2.12, "Global System Interrupts".
Example ASL for _GSB usage for a non-PCI based I/O APIC Device:

Scope(\_SB) {
�
Device(APIC) {       // I/O APIC Device
Name(_HID, "ACPI0009")      // ACPI ID for I/O APIC
Name(_CRS, ResourceTemplate()
{ �})            // only one resource pointing to I/O APIC register base
Method(_GSB){
       Return (0x10) // Global System Interrupt Base for I/O APIC starts at 16
}
} // end APIC
}   // end scope SB
Example ASL for _GSB usage for a PCI-based I/O APIC Device:

Scope(\_SB) {
Device(PCI0)     // Host bridge
Name(_HID, EISAID("PNP0A03"))     // Need _HID for root device
Name(_ADR, 0)
Device(PCI1) {       // I/O APIC PCI Device
Name(_ADR,0x00070000)
Method(_GSB){
       Return (0x18) // Global System Interrupt Base for I/O APIC starts at 24
}

} // end PCI1
} // end PCI0
}   // end scope SB
6.2.6   _HPP (Hot Plug Parameters)
This optional object evaluates to the cache-line size, latency timer, SERR enable, and PERR enable values to be used when configuring a PCI device inserted into a hot-plug slot or for performing configuration of a PCI devices not configured by the BIOS at system boot. The object is placed under a PCI bus where this behavior is desired, such as a bus with hot-plug slots. _HPP provided settings apply to all child buses, until another _HPP object is encountered.
Arguments:
            None
Result Code:

    Method (_HPP, 0) {
       Return (Package(4){
           0x08,             // CacheLineSize in DWORDS
           0x40,             // LatencyTimer in PCI clocks
           0x01,             // Enable SERR (Boolean)
           0x00              // Enable PERR (Boolean)
       })
    }
Table 6-5   _HPP

Field	Format	Definition
Cache-line size	INTEGER	Cache-line size reported in number of DWORDs.
Latency timer	INTEGER	Latency timer value reported in number of PCI clock cycles.
Enable SERR	INTEGER	When set to 1, indicates that action must be performed to enable SERR in the command register.
Enable PERR	INTEGER	When set to 1, indicates that action must be performed to enable PERR in the command register.

6.2.6.1   Example:Using _HPP

Scope(\_SB) {
    Device(PCI0) {                      // Root PCI Bus
       Name(_HID, EISAID("PNP0A03"))       // _HID for root device
       Name(_ADR,0)                    // Device 0 on this bus
       Method (_CRS,0){                // Need current resources for root dev
                  // Return current resources for root bridge 0
       }
       Name(_PRT, Package(){ // Need PCI IRQ routing for PCI bridge
                  // Package with PCI IRQ routing table information
       })

       Device (P2P1) {                 // First PCI-to-PCI bridge (No Hot Plug slots)
           Name(_ADR,0x000C0000)        // Device#Ch, Func#0 on bus PCI0
           Name(_PRT, Package(){        // Need PCI IRQ routing for PCI bridge
                      // Package with PCI IRQ routing table information
           })
       } // end P2P1

       Device (P2P2) {       // Second PCI-to-PCI bridge (Bus contains Hot plug slots)
           Name(_ADR,0x000E0000)        // Device#Eh, Func#0 on bus PCI0
           Name(_PRT, Package(){        // Need PCI IRQ routing for PCI bridge
                      // Package with PCI IRQ routing table information
           })
           Name(_HPP, Package(){0x08,0x40, 0x01, 0x00})

           // Device definitions for Slot 1- HOT PLUG SLOT
           Device (S1F0) {              // Slot 1, Func#0 on bus P2P2
               Name(_ADR,0x00020000)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S1F1) {              // Slot 1, Func#1 on bus P2P2
               Name(_ADR,0x00020001)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S1F2) {              // Slot 1, Func#2 on bus P2P2
               Name(_ADR,0x000200    02)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S1F3) {              // Slot 1, Func#3 on bus P2P2
              Name(_ADR,0x00020003)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S1F4) {              // Slot 1, Func#4 on bus P2P2
               Name(_ADR,0x00020004)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S1F5) {              // Slot 1, Func#5 on bus P2P2
               Name(_ADR,0x00020005)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S1F6) {              // Slot 1, Func#6 on bus P2P2
              Name(_ADR,0x00020006)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S1F7) {              // Slot 1, Func#7 on bus P2P2
               Name(_ADR,0x00020007)
              Method(_EJ0, 1) {        // Remove all power to device}
           }

           // Device definitions for Slot 2- HOT PLUG SLOT
           Device (S2F0) {              // Slot 2, Func#0 on bus P2P2
              Name(_ADR,0x00030000)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S2F1) {              // Slot 2, Func#1 on bus P2P2
              Name(_ADR,0x00030001)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S2F2) {              // Slot 2, Func#2 on bus P2P2
               Name(_ADR,0x00030002)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S2F3) {              // Slot 2, Func#3 on bus P2P2
              Name(_ADR,0x00030003)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S2F4) {              // Slot 2, Func#4 on bus P2P2
               Name(_ADR,0x00030004)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S2F5) {              // Slot 2, Func#5 on bus P2P2
              Name(_ADR,0x00030005)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S2F6) {              // Slot 2, Func#6 on bus P2P2
              Name(_ADR,0x00030006)
              Method(_EJ0, 1) {        // Remove all power to device}
           }
           Device (S2F7) {              // Slot 2, Func#7 on bus P2P2
              Name(_ADR,0x00030007)
               Method(_EJ0, 1) {        // Remove all power to device}
           }

       }   // end P2P2
   } // end PCI0
}   // end Scope (\_SB)

OSPM will configure a PCI device on a card hot-plugged into slot 1 or slot 2, with a cache line size of 32 (Notice this field is in DWORDs), latency timer of 64, enable SERR, but leave PERR alone.
6.2.7   _HPX (Hot Plug Parameter Extensions)
This optional object provides platform-specific information to the OSPM PCI driver component responsible for configuring hot-add PCI, PCI-X, or PCI Express devices. The information conveyed applies to the entire hierarchy downward from the scope containing the _HPX object. If another _HPX object is encountered downstream, the settings conveyed by the lower-level object apply to that scope downward.
OSPM uses the information returned by _HPX to determine how to configure PCI devices hot-added to the system, and to configure devices not configured by platform firmware during initial system boot. The _HPX object is placed within the scope of a PCI-compatible bus (see Note 2 below for restrictions) where this behavior is desired, such as a bus with hot-plug slots. It returns a package that contains one or more Setting Records. Each Setting Record contains a Setting Type (INTEGER), a Revision number (INTEGER) and type/revision specific contents.
The format of data returned by the _HPX object is extensible. The Setting Type and Revision number determine the format of the Setting Record. OSPM ignores Setting Records of types that it does not understand. A Setting Record with higher Revision number supersedes that with lower revision number, however, the _HPX method can return both together, OSPM shall use the one with highest revision number that it understands.
_HPX may return multiple types or Record Settings in a single package. OSPM is responsible for detecting the type of hot plugged device and for applying the appropriate settings. OSPM is also responsible for detecting the device / port type of the PCI Express device and applying the appropriate settings provided. For example, the Secondary Uncorrectable Error Severity and Secondary Uncorrectable Error Mask settings of Type 2 record are only applicable to PCI Express to PCI-X/PCI Bridge whose device / port type is 1000b. Similarly, AER settings are only applicable to hot plug PCI Express devices that support the optional AER capability.
Arguments:
            None
Result Code:
            A package of one or more packages containing PCI(-X) Record Settings packages defined below.
The _HPX object supersedes the _HPP object. If the _HPP and _HPX objects exist within a device's scope, OSPM will only evaluate the _HPX object.
Notes:
1)     OSPM may override the settings provided by the_HPX object's Type2 record (PCI Express Settings) when OSPM has assumed native control of the corresponding feature. For example, if OSPM has assumed ownership of AER (via _OSC), OSPM may override AER related settings returned by_HPX.
2)     The_HPX object may exist under PCI compatible buses including host bridges except when the host bridge spawns a PCI Express hierarchy. For PCI Express hierarchies, the _HPX object may only exist under a root port or a switch downstream port.
3)     Since error status registers do not drive error signaling, OSPM is not required to clear error status registers as part of _HPX handling.

6.2.7.1   PCI Setting Record (Type 0)
The PCI setting record contains the setting type 0, the current revision 1 and the type/revision specific content: cache-line size, latency timer, SERR enable, and PERR enable values.
Table 6-6  PCI Setting Record Content

Field	Format	Definition
Header
Type	INTEGER	0x00: Type 0 (PCI) setting record.
Revision	INTEGER	0x01: Revision 1, defining the set of fields below.
Cache-line size	INTEGER	Cache-line size reported in number of DWORDs.
Latency timer	INTEGER	Latency timer value reported in number of PCI clock cycles.
Enable SERR	INTEGER	When set to 1, indicates that action must be performed to enable SERR in the command register.
Enable PERR	INTEGER	When set to 1, indicates that action must be performed to enable PERR in the command register.

If the hot plug device includes bridge(s) in the hierarchy, the above settings apply to the primary side (command register) of the hot plugged bridge(s). The settings for the secondary side of the bridge(s) (Bridge Control Register) are assumed to be provided by the bridge driver.
The Type 0 record is applicable to hot plugged PCI, PCI-X and PCI Express devices. OSPM will ignore settings provided in the Type0 record that are not applicable (for example, Cache-line size and Latency Timer are not applicable to PCI Express).
6.2.7.2 PCI-X Setting Record (Type 1)
The PCI-X setting record contains the setting type 1, the current revision 1 and the type/revision specific content: the maximum memory read byte count setting, the average maximum outstanding split transactions setting and the total maximum outstanding split transactions to be used when configuring PCI-X command registers for PCI-X buses and/or devices.
Table 6-7 PCI-X Setting Record Content

Field	Format	Definition
Header
Type	INTEGER	0x01: Type 1 (PCI-X) setting record.
Revision	INTEGER	0x01: Revision 1, defining the set of fields below.
Maximum memory read byte count	INTEGER	maximum memory read byte count reported: Value 0: Maximum byte count 512, Value 1: Maximum byte count 1024, Value 2: Maximum byte count 2048, Value 3: Maximum byte count 4096
Average maximum outstanding split transactions	INTEGER	The following values are defined, Value 0: Maximum outstanding split transaction 1, Value 1: Maximum outstanding split transaction 2, Value 2: Maximum outstanding split transaction 3, Value 3: Maximum outstanding split transaction 4, Value 4: Maximum outstanding split transaction 8, Value 5: Maximum outstanding split transaction 12, Value 6: Maximum outstanding split transaction 16, Value 7: Maximum outstanding split transaction 32,
Total maximum outstanding split transactions	INTEGER	See the definition for the average maximum outstanding split transactions.

For simplicity, OSPM could use the Average Maximum Outstanding Split Transactions value as the Maximum Outstanding Split Transactions register value in the PCI-X command register for each PCI-X device. Another alternative is to use a more sophisticated policy and the Total Maximum Outstanding Split Transactions Value to gain even more performance this case, the OS would examined each PCI-X device that is directly attached to the host bridge, determine the number of outstanding split transactions supported by each device, and configure each device accordingly. The goal is to ensure that the aggregate number of concurrent outstanding split transactions does not exceed the Total Maximum Outstanding Split Transactions Value: an integer denoting the number of concurrent outstanding split transactions the host bridge can support (the minimum value is 1).
This object does not address providing additional information that would be used to configure registers in bridge devices, whether architecturally-defined or specification-defined registers or device specific registers. It is expected that a driver for a bridge would be the proper implementation mechanism to address both of those issues. However, such a bridge driver should have access to the data returned by the_HPX object for use in optimizing its decisions on how to configure the bridge. Configuration of a bridge is dependent on both system specific information such as that provided by the _HPX object, as well as bridge specific information.
6.2.7.3 PCI Express Setting Record (Type 2)
The PCI Express setting record contains the setting type 2, the current revision 1 and the type/revision specific content (the control registers as listed in the table below) to be used when configuring registers in the Advanced Error Reporting Extended Capability Structure or PCI Express Capability Structure for the PCI Express devices.
The Type 2 Setting Record allows a PCI Express-aware OS that supports native hot plug to configure the specified registers of the hot plugged PCI Express device. A PCI Express-aware OS that has assumed ownership of native hot plug (via _OSC) but does not support or does not have ownership of the AER register set must use the data values returned by the _HPX object's Type 2 record to program the AER registers of a hot-added PCI Express device. However, since the Type 2 record also includes register bits that have functions other than AER, OSPM must ignore values contained within this setting record that are not applicable.
To support PCIe RsvdP semantics for reserved bits, two values for each register are provided: an "AND mask" and an "OR mask". Each bit understood by firmware to be RsvdP shall be set to 1 in the "AND mask" and 0 in the "OR mask". Each bit that firmware intends to be configured as 0 shall be set to 0 in both the "AND mask" and the "OR mask". Each bit that firmware intends to be configured a 1 shall be set to 1 in both the "AND mask" and the "OR mask".
When configuring a given register, OSPM uses the following algorithm:
1.       Read the register's current value, which contains the register's default value.
2.       Perform a bit-wise AND operation with the "AND mask" from the table below.
3.       Perform a bit-wise OR operation with the "OR mask" from the table below.
4.       Override the computed settings for any bits if deemed necessary. For example, if OSPM is aware of an architected meaning for a bit that firmware considers to be RsvdP, OSPM may choose to override the computed setting for that bit. Note that firmware sets the "AND value" to 1 and the "OR value" to 0 for each bit that it considers to be RsvdP.
5.       Write the end result value back to the register.
Note that the size of each field in the following table matches the size of the corresponding PCI Express register.
Table 6-8  PCI Express Setting Record Content

Field	Format	Definition
Header
Type	INTEGER	0x02: Type 2 (PCI Express) setting record.
Revision	INTEGER	0x01: Revision 1, defining the set of fields below.
Uncorrectable Error Mask Register AND Mask	INTEGER	Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above.
Uncorrectable Error Mask Register OR Mask	INTEGER	Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above.
Uncorrectable Error Severity Register AND Mask	INTEGER	Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above.
Uncorrectable Error Severity Register OR Mask	INTEGER	Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above.
Correctable Error Mask Register AND Mask	INTEGER	Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above.
Correctable Error Mask Register OR Mask	INTEGER	Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above.
Advanced Error Capabilities and Control Register AND Mask	INTEGER	Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above.
Advanced Error Capabilities and Control Register OR Mask	INTEGER	Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above.
Device Control Register AND Mask	INTEGER	Bits 0 to 15 contain the "AND mask" to be used in the OSPM algorithm described above.
Device Control Register OR Mask	INTEGER	Bits 0 to 15 contain the "OR mask" to be used in the OSPM algorithm described above.
Link Control Register AND Mask	INTEGER	Bits 0 to 15 contain the "AND mask" to be used in the OSPM algorithm described above.
Link Control Register OR Mask	INTEGER	Bits 0 to 15 contain the "OR mask" to be used in the OSPM algorithm described above.
Secondary Uncorrectable Error Severity Register AND Mask	INTEGER	Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above
Secondary Uncorrectable Error Severity Register OR Mask	INTEGER	Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above
Secondary Uncorrectable Error Mask Register AND Mask	INTEGER	Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above
Secondary Uncorrectable Error Mask Register OR Mask	INTEGER	Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above

6.2.7.4 _HPX Example

    Method (_HPX, 0) {
       Return (Package(2){
           Package(6){           // PCI Setting Record
              0x00,         // Type 0
              0x01,          // Revision 1
               0x08,         // CacheLineSize in DWORDS
               0x40,         // LatencyTimer in PCI clocks
              0x01,          // Enable SERR (Boolean)
               0x00          // Enable PERR (Boolean)
           },
           Package(5){           // PCI-X Setting Record
               0x01,          // Type 1
              0x01,          // Revision 1
              0x03,          // Maximum Memory Read Byte Count
              0x04,          // Average Maximum Outstanding Split Transactions
              0x07           // Total Maximum Outstanding Split Transactions
           }
        })
    }
6.2.8   _MAT (Multiple APIC Table Entry)
This optional object evaluates to a buffer returning data in the format of a series of Multiple APIC Description Table (MADT) APIC Structure entries. This object can appear under an I/O APIC or processor object definition as processors may contain Local APICs. Specific types of MADT entries are meaningful to (in other words, is processed by) OSPM when returned via the evaluation of this object as described below. Other entry types returned by the evaluation of _MAT are ignored by OSPM.
When _MAT appears under a Processor object, OSPM processes Local APIC (section 5.2.11.5, "Processor Local APIC"), Local SAPIC (section 5.2.11.13, "Local SAPIC Structure"), and local APIC NMI (section 5.2.11.10, "Local APIC NMI") entries returned from the object's evaluation. Other entry types are ignored by OSPM. OSPM uses the ACPI processor ID in the entries returned from the object's evaluation to identify the entries corresponding to either the ACPI processor ID of the Processor object or the value returned by the _UID object under a Processor device.
When _MAT appears under an I/O APIC, OSPM processes I/O APIC (section 5.2.11.6, "I/O APIC"), I/O SAPIC (section 5.2.11.12, "I/O SAPIC Structure"), non-maskable interrupt sources (section 5.2.11.9, "Non-Maskable Interrupt Sources (NMIs)"), interrupt source overrides (section 5.2.11.8, "Interrupt Source Overrides"), and platform interrupt source structure (section 5.2.11.14, "Platform Interrupt Source Structure") entries returned from the object's evaluation. Other entry types are ignored by OSPM.
Arguments:
None
Result Code:
A buffer
Example ASL for _MAT usage:

Scope(\_SB) {
    Device(PCI0) {                      // Root PCI Bus
       Name(_HID, EISAID("PNP0A03"))           // Need _HID for root device
       Name(_ADR,0)                        // Device 0 on this bus
       Method (_CRS,0){                    // Need current resources for root device
           // Return current resources for root bridge 0
       }
       Name(_PRT, Package(){                // Need PCI IRQ routing for PCI bridge
           // Package with PCI IRQ routing table information
       })

       Device (P64A) {                      // P64A ACPI
           Name(_ADR,0)
           OperationRegion(TABD, SystemMemory,     //Physical address of first
               // data byte of multiple ACPI table, Length of tables)
           Field (TABD, ByteAcc, NoLock, Preserve){
               MATD, Length of tables x 8
           }
           Method(_MAT, 0){
              Return (MATD)
           }
        } // end P64A
    } // end PCI0
} // end scope SB
6.2.9   _OSC (Operating System Capabilities)
This optional object is a control method that is used by OSPM to communicate to the platform the feature support or capabilities provided by a device's driver. This object is a child object of a device and may also exist in the \_SB scope, where it can be used to convey platform wide OSPM capabilities. When supported, _OSC is invoked by OSPM immediately after placing the device in the D0 power state. Device specific objects are evaluated after _OSC invocation. This allows the values returned from other objects to be predicated on the OSPM feature support / capability information conveyed by _OSC. OSPM may evaluate _OSC multiple times to indicate changes in OSPM capability to the device but this may be precluded by specific device requirements. As such, _OSC usage descriptions in section 9, "ACPI-Specific Device Objects", or other governing specifications describe superseding device specific _OSC capabilities and / or preclusions.
_OSC enables the platform to configure its ACPI namespace representation and object evaluations to match the capabilities of OSPM. This enables legacy operating system support for platforms with new features that make use of new namespace objects that if exposed would not be evaluated when running a legacy OS. _OSC provides the capability to transition the platform to native operating system support of new features and capabilities when available through dynamic namespace reconfiguration. _OSC also allows devices with Compatible IDs to provide superset functionality when controlled by their native (For example, _HID matched) driver as appropriate objects can be exposed accordingly as a result of OSPM's evaluation of _OSC.
Arguments:
Arg0 (Buffer): UUID
Arg1 (Integer): Revision ID
Arg2 (Integer):    Count
Arg3 (Buffer): Capabilities Buffer,
UUID – Universal Unique Identifier (16 Byte Buffer) used by the platform in conjunction with Revision ID to ascertain the format of the Capabilities buffer.
Revision ID – The revision of the Capabilities Buffer format. The revision level is specific to the UUID.
Count - Number of DWORDs in the Capabilities Buffer in Arg3
Capabilities Buffer – Buffer containing the number of DWORDs indicated by Count. The first DWORD of this buffer contains standard bit definitions as described below. Subsequent DWORDs contain UUID-specific bits that convey to the platform the capabilities and features supported by OSPM. Successive revisions of the Capabilities Buffer must be backwards compatible with earlier revisions. Bit ordering cannot be changed.
Capabilities Buffers are device-specific and as such are described under specific device definitions. See section 9, "ACPI Devices and Device Specific Objects" for any _OSC definitions for ACPI devices. The format of the Capabilities Buffer and behavior rules may also be specified by OEMs and IHVs for custom devices and other interface or device governing bodies for example, the PCI SIG.

The first DWORD in the capabilities buffer is used to return errors defined by _OSC. This DWORD must always be present and may not be redefined/reused by unique interfaces utilizing _OSC.
·      Bit 0- Query Support Flag. the _OSC invocation is a query by OSPM to determine which capabilities OSPM may take control of. In this case, _OSC sets bits for those capabilities of which OSPM may take control and clears bits for those capabilities of which OSPM may not take control. If zero, OSPM is attempting to take control of the capabilities corresponding to the bits set.
·      Bit 1- Always clear(0).
·      Bit 2- Always clear(0).
·      Bit 3- Always clear(0).
·      All others- reserved.
Result Code:
Capabilities Buffer (Buffer) – The platform acknowledges the Capabilities Buffer by returning a buffer of DWORDs of the same length. Set bits indicate acknowledgement and cleared bits indicate that the platform does not support the capability.
The first DWORD in the capabilities buffer is used to return errors defined by _OSC. This DWORD must always be present and may not be redefined/reused by unique interfaces utilizing _OSC.
·      Bit 0- Reserved (not used)
·      Bit 1- _OSC failure. Platform Firmware was unable to process the request or query. Capabilities bits may have been masked.
·      Bit 2- Unrecognized UUID. This bit is set to indicate that the platform firmware does not recognize the UUID passed in via Arg0. Capabilities bits are preserved.
·      Bit 3- Unrecognized Revision. This bit is set to indicate that the platform firmware does not recognize the Revision ID passed in via Arg1. Capabilities bits beyond those comprehended by the firmware will be masked.
·      Bit 4- Capabilities Masked. This bit is set to indicate that capabilities bits set by driver software have been cleared by platform firmware.
· All others- reserved.
At this time, platform-wide Capabilities Buffer DWORD bit definitions are not defined. As such, OSPM implementations are not expected to evaluate \_SB._OSC until a future revision of the ACPI specification specifies platform-wide Capabilities Buffer DWORD bit definitions.
Note: OSPM must not use the results of _OSC evaluation to choose a compatible device driver. OSPM must use _HID, _CID, or native enumerable bus device identification mechanisms to select an appropriate driver for a device.
The platform may issue a Notify(device, 0x08) to inform OSPM to re-evaluate _OSC when the availability of feature control changes. Platforms must not rely, however, on OSPM to evaluate _OSC after issuing a Notify for proper operation as OSPM cannot guarantee the presence of a target entity to receive and process the Notify for the device. For example, a device driver for the device may not be loaded at the time the Notify is signaled. Further, the issuance and processing rules for notification of changes in the Capabilities Buffer is device specific. As such, the allowable behavior is governed by device specifications either in section 9, " ACPI-Specific Device Objects", for ACPI-define devices, or other OEM, IHV, or device governing body's' device specifications.
It is permitted for _OSC to return all bits in the Capabilities Buffer cleared. An example of this is when significant time is required to disable platform-based feature support. The platform may then later issue a Notify to tell OSPM to re-evaluate _OSC to take over native control. This behavior is also device specific but may also rely on specific OS capability.
In general, platforms should support both OSPM taking and relinquishing control of specific feature support via multiple invocations of _OSC but the required behavior may vary on a per device basis.
Since platform context is lost when the platform enters the S4 sleeping state, OSPM must re-evaluate _OSC upon wake from S4 to restore the previous platform state. This requirement will vary depending on the device specific _OSC functionality.
6.2.9.1   _OSC Implementation Example for PCI Host Bridge Devices
The following section is an excerpt from the PCI Firmware Specification Revision 3.0 and is reproduced with the permission of the PCI SIG. Note: The PCI SIG owns the definition of _OSC behavior and parameter bit definitions for PCI devices. In the event of a discrepancy between the following example and the PCI Firmware Specification, the latter has precedence.
The _OSC interface defined in this section applies only to "Host Bridge" ACPI devices that originate PCI, PCI-X or PCI Express hierarchies. These ACPI devices must have a _HID of (or _CID including) either EISAID("PNP0A03") or EISAID("PNP0A08"). For a host bridge device that originates a PCI Express hierarchy, the _OSC interface defined in this section is required. For a host bridge device that originates a PCI/PCI-X bus hierarchy, inclusion of an _OSC object is optional.
The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is identified by the Universal Uniform Identifier (UUID) 33db4d5b-1ff7-401c-9657-7441c03dd766. A revision ID of 1 encompasses fields defined in this section of this revision of this specification, comprised of 3 DWORDs, including the first DWORD described by the generic ACPI definition of _OSC.
The first DWORD in the _OSC Capabilities Buffer contain bits are generic to _OSC and include status and error information.
The second DWORD in the _OSC capabilities buffer is the Support Field. Bits defined in the Support Field provide information regarding OS supported features. Contents in the Support Field are passed one-way; the OS will disregard any changes to this field when returned. See Table 6-8 for descriptions of capabilities bits in this field passed as a parameter into the _OSC control method.
The third DWORD in the _OSC Capabilities Buffer is the Control Field. Bits defined in the Control Field are used to submit request by the OS for control/handling of the associated feature, typically (but not excluded to) those features that utilize native interrupts or events handled by an OS-level driver. See Table 6-10 for descriptions of capabilities bits in this field passed as a parameter into the _OSC control method. If any bits in the Control Field are returned cleared (masked to zero) by the _OSC control method, the respective feature is designated unsupported by the platform and must not be enabled by the OS. Some of these features may be controlled by platform firmware prior to OS boot or during runtime for a legacy OS, while others may be disabled/inoperative until native OS support is available. See Table 6-11 for descriptions of capabilities bits in this returned field.
If the _OSC control method is absent from the scope of a host bridge device, then the OS must not enable or attempt to use any features defined in this section for the hierarchy originated by the host bridge. Doing so could contend with platform firmware operations, or produce undesired results. It is recommended that a machine with multiple host bridge devices should report the same capabilities for all host bridges, and also negotiate control of the features described in the Control Field in the same way for all host bridges.
Table 6-9  Interpretation of _OSC Support Field

Support Field bit offset	Interpretation
0	Extended PCI Config operation regions supported The OS sets this bit to 1 if it supports ASL accesses through PCI Config operation regions to extended configuration space (offsets greater than 0xFF). Otherwise, the OS sets this bit to 0.
1	Active State Power Management supported The OS sets this bit to 1 if it natively supports configuration of Active State Power Management registers in PCI Express devices. Otherwise, the OS sets this bit to 0.
2	Clock Power Management Capability supported The OS sets this bit to 1 if it supports the Clock Power Management Capability, and will enable this feature during a native hot plug insertion event if supported by the newly added device. Otherwise, the OS sets this bit to 0. Note: The Clock Power Management Capability is defined in an errata to the PCI Express Base Specification, 1.0.
3	PCI Segment Groups supported The OS sets this bit to 1 if it supports PCI Segment Groups as defined by the _SEG object, and access to the configuration space of devices in PCI Segment Groups as described by this specification. Otherwise, the OS sets this bit to 0.
4	MSI supported The OS sets this bit to 1 if it supports configuration of devices to generate message-signaled interrupts, either through the MSI Capability or the MSI-X Capability. Otherwise, the OS sets this bit to 0.
5-31	Reserved

Table 6-10 Interpretation of _OSC Control Field, Passed in via Arg3

Control Field bit offset	Interpretation
0	PCI Express Native Hot Plug control The OS sets this bit to 1 to request control over PCI Express native hot plug. If the OS successfully receives control of this feature, it must track and update the status of hot plug slots and handle hot plug events as described in the PCI Express Base Specification.
1	SHPC Native Hot Plug control The OS sets this bit to 1 to request control over PCI/PCI-X Standard Hot-Plug Controller (SHPC) hot plug. If the OS successfully receives control of this feature, it must track and update the status of hot plug slots and handle hot plug events as described in the SHPC Specification.
2	PCI Express Native Power Management Events control The OS sets this bit to 1 to request control over PCI Express native power management event interrupts (PMEs). If the OS successfully receives control of this feature, it must handle power management events as described in the PCI Express Base Specification.
3	PCI Express Advanced Error Reporting control The OS sets this bit to 1 to request control over PCI Express Advanced Error Reporting. If the OS successfully receives control of this feature, it must handle error reporting through the Advanced Error Reporting Capability as described in the PCI Express Base Specification.
4	PCI Express Capability Structure control The OS sets this bit to 1 to request control over the PCI Express Capability Structures (standard and extended) defined in the PCI Express Base Specification version 1.1. These capability structures are the PCI Express Capability, the virtual channel extended capability, the power budgeting extended capability, the advanced error reporting extended capability, and the serial number extended capability. If the OS successfully receives control of this feature, it is responsible for configuring the registers in all PCI Express Capabilities in a manner that complies with the PCI Express Base Specification. Additionally, the OS is responsible for saving and restoring all PCI Express Capability register settings across power transitions when register context may have been lost.
5-31	Reserved

Table 6-11 Interpretation of _OSC Control Field, Returned Value

Control Field bit offset	Interpretation
0	PCI Express Native Hot Plug control The firmware sets this bit to 1 to grant control over PCI Express native hot plug interrupts. If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that all hot plug events are routed to device interrupts as described in the PCI Express Base Specification. Additionally, after control is transferred to the OS, firmware must not update the state of hot plug slots, including the state of the indicators and power controller. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0.
1	SHPC Native Hot Plug control The firmware sets this bit to 1 to grant control over control over PCI/PCI-X Standard Hot-Plug Controller (SHPC)hot plug. If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that all hot plug events are routed to device interrupts as described in the SHPC Specification. Additionally, after control is transferred to the OS, firmware must not update the state of hot plug slots, including the state of the indicators and power controller. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0.
2	PCI Express Native Power Management Events control The firmware sets this bit to 1 to grant control over control over PCI Express native power management event interrupts (PMEs). If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that all PMEs are routed to root port interrupts as described in the PCI Express Base Specification. Additionally, after control is transferred to the OS, firmware must not update the PME Status field in the Root Status register or the PME Interrupt Enable field in the Root Control register. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0.
3	PCI Express Advanced Error Reporting control The firmware sets this bit to 1 to grant control over PCI Express Advanced Error Reporting. If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that error messages are routed to device interrupts as described in the PCI Express Base Specification. Additionally, after control is transferred to the OS, firmware must not modify the Advanced Error Reporting Capability. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0.
4	PCI Express Capability Structure control The firmware sets this bit to 1 to grant control over the PCI Express Capability the firmware does not grant control of this feature, firmware must handle configuration of the PCI Express Capability Structure. If firmware grants the OS control of this feature, any firmware configuration of the PCI Express Capability may be overwritten by an OS configuration, depending on OS policy.
5-31	Reserved

6.2.9.1.1 Rules for Evaluating _OSC
This section defines when and how the OS must evaluate _OSC, as well as restrictions on firmware implementation.
6.2.9.1.1.1 Query Flag
If the Query Support Flag (Capabilities DWORD 1, bit 0 ) is set by the OS when evaluating _OSC, no hardware settings are permitted to be changed by firmware in the context of the _OSC call. It is strongly recommended that the OS evaluate _OSC with the Query Support Flag set until _OSC returns the Capabilities Masked bit clear, to negotiate the set of features to be granted to the OS for native support; a platform may require a specific combination of features to be supported natively by an OS before granting native control of a given feature.
6.2.9.1.1.2 Evaluation Conditions
The OS must evaluate _OSC under the following conditions:
During initialization of any driver that provides native support for features described in the section above. These features may be supported by one or many drivers, but should only be evaluated by the main bus driver for that hierarchy. Secondary drivers must coordinate with the bus driver to install support for these features. Drivers may not relinquish control of features previously obtained. I.e. bits set in Capabilities DWORD3 after the negotiation process must be set on all subsequent negotiation attempts.
When a Notify(<device>, 8) is delivered to the PCI Host Bridge device.
Upon resume from S4. Platform firmware will handle context restoration when resuming from S1-S3.
6.2.9.1.1.3 Sequence of _OSC calls
The following rules govern sequences of calls to _OSC that are issued to the same host bridge and occur within the same boot.
· The OS is permitted to evaluate _OSC an arbitrary number of times.
· If the OS declares support of a feature in the Status Field in one call to _OSC, then it must preserve the set state of that bit (declaring support for that feature) in all subsequent calls.
· If the OS is granted control of a feature in the Control Field in one call to _OSC, then it must preserve the set state of that bit (requesting that feature) in all subsequent calls.
· Firmware may not reject control of any feature it has previously granted control to.
· There is no mechanism for the OS to relinquish control of a feature previously requested and granted..
6.2.9.1.2 ASL Example
A sample _OSC implementation for a mobile system incorporating a PCI Express hierarchy is shown below:
       Device(PCI0) // Root PCI bus
       {
           Name(_HID,EISAID("PNP0A08")) // PCI Express Root Bridge
           Name(_CID,EISAID("PNP0A03")) // Compatible PCI Root Bridge
           Name(SUPP,0) // PCI _OSC Support Field value
           Name(CTRL,0) // PCI _OSC Control Field value

           Method(_OSC,4)
           {   // Check for proper UUID
              If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
              {
                  // Create DWord-adressable fields from the Capabilities Buffer
                  CreateDWordField(Arg3,0,CDW1)
                  CreateDWordField(Arg3,4,CDW2)
                  CreateDWordField(Arg3,8,CDW3)

                  // Save Capabilities DWord2 & 3
                  Store(CDW2,SUPP)
                  Store(CDW3,CTRL)

                  // Only allow native hot plug control if OS supports:
                  // * ASPM
                  // * Clock PM
                  // * MSI/MSI-X
                  If(LNotEqual(And(SUPP, 0x16), 0x16))
                  {
                      And(CTRL,0x1E) // Mask bit 0 (and undefined bits)
                  }

                  // Always allow native PME, AER (no dependencies)

                  // Never allow SHPC (no SHPC controller in this system)
                  And(CTRL,0x1D,CTRL)

                  If(Not(And(CDW1,1))) // Query flag clear?
                  {   // Disable GPEs for features granted native control.
                      If(And(CTRL,0x01))    // Hot plug control granted?
                      {
                         Store(0,HPCE) // clear the hot plug SCI enable bit
                         Store(1,HPCS) // clear the hot plug SCI status bit
                      }
                      If(And(CTRL,0x04))    // PME control granted?
                      {
                         Store(0,PMCE) // clear the PME SCI enable bit
                         Store(1,PMCS) // clear the PME SCI status bit
                      }
                      If(And(CTRL,0x10))    // OS restoring PCIe cap structure?
                      {   // Set status to not restore PCIe cap structure
                         // upon resume from S3
                         Store(1,S3CR)
                      }
                  }

                  If(LNotEqual(Arg1,One))
                  {   // Unknown revision
                      Or(CDW1,0x08,CDW1)
                  }

                  If(LNotEqual(CDW3,CTRL))
                  {   // Capabilities bits were masked
                      Or(CDW1,0x10,CDW1)
                  }
                  // Update DWORD3 in the buffer
                  Store(CTRL,CDW3)
                  Return(Arg3)
              } Else {
                  Or(CDW1,4,CDW1)       // Unrecognized UUID
                  Return(Arg3)
               }
           }   // End _OSC
       }   // End PCI0
6.2.10   _PRS (Possible Resource Settings)
This optional object evaluates to a byte stream that describes the possible resource settings for the device. When describing a platform, specify a _PRS for all the configurable devices. Static (non-configurable) devices do not specify a _PRS object. The information in this package is used by OSPM to select a conflict-free resource allocation without user intervention. This method must not reference any operation regions that have not been declared available by a _REG method.
The format of the data in a _PRS object follows the same format as the _CRS object (for more information, see the _CRS object definition in section 6.2.1, "_CRS (Current Resource Settings)").
If the device is disabled when _PRS is called, it must remain disabled.
Arguments:
None
Result Code:
Byte stream

6.2.11 _PRT (PCI Routing Table)
PCI interrupts are inherently non-hierarchical interrupt pins are wired to interrupt inputs of the interrupt controllers _PRT object provides a mapping from PCI interrupt pins to the interrupt inputs of the interrupt controllers. The _PRT object is required under all PCI root bridges. _PRT evaluates to a package that contains a list of packages, each of which describes the mapping of a PCI interrupt pin.
Note: The PCI function number in the Address field of the _PRT packages must be 0xFFFF, indicating "any" function number or "all functions".
The _PRT mapping packages have the fields listed in Table 6-12.
Table 6-12 Mapping Fields

Field	Type	Description
Address	DWORD	The address of the device (uses the same format as _ADR).
Pin	BYTE	The PCI pin number of the device (0–INTA, 1–INTB, 2–INTC, 3–INTD).
Source	NamePath Or BYTE	Name of the device that allocates the interrupt to which the above pin is connected. The name can be a fully qualified path, a relative path, or a simple name segment that utilizes the namespace search rules. Note: This field is a NamePath and not a String literal, meaning that it should not be surrounded by quotes. If this field is the integer constant Zero (or a BYTE value of 0), then the interrupt is allocated from the global interrupt pool.
Source Index	DWORD	Index that indicates which resource descriptor in the resource template of the device pointed to in the Source field this interrupt is allocated from. If the Source field is the BYTE value zero, then this field is the global system interrupt number to which the pin is connected.

There are two ways that _PRT can be used. Typically, the interrupt input that a given PCI interrupt is on is configurable. For example, a given PCI interrupt might be configured for either IRQ 10 or 11 on an 8259 interrupt controller. In this model, each interrupt is represented in the ACPI namespace as a PCI Interrupt Link Device.
These objects have _PRS, _CRS, _SRS, and _DIS control methods to allocate the interrupt. Then, OSPM handles the interrupts not as interrupt inputs on the interrupt controller, but as PCI interrupt pins driver looks up the device's pins in the _PRT to determine which device objects allocate the interrupts. To move the PCI interrupt to a different interrupt input on the interrupt controller, OSPM uses _PRS, _CRS, _SRS, and _DIS control methods for the PCI Interrupt Link Device.
In the second model, the PCI interrupts are hardwired to specific interrupt inputs on the interrupt controller and are not configurable. In this case, the Source field in _PRT does not reference a device, but instead contains the value zero, and the Source Index field contains the global system interrupt to which the PCI interrupt is hardwired.
6.2.11.1   Example: Using _PRT to Describe PCI IRQ Routing
The following example describes two PCI slots and a PCI video chip. Notice that the interrupts on the two PCI slots are wired differently (barber-poled).

Scope(\_SB) {
    Device(LNKA){
       Name(_HID, EISAID("PNP0C0F"))                     // PCI interrupt link
       Name(_UID, 1)
       Name(_PRS, ResourceTemplate(){
           Interrupt(ResourceProducer,�) {10,11}     // IRQs 10,11
       })
       Method(_DIS) {�}
       Method(_CRS) {�}
       Method(_SRS, 1) {�}
    }
    Device(LNKB){
       Name(_HID, EISAID("PNP0C0F"))                     // PCI interrupt link
       Name(_UID, 2)
       Name(_PRS, ResourceTemplate(){
           Interrupt(ResourceProducer,�) {11,12}     // IRQs 11,12
       })
       Method(_DIS) {�}
       Method(_CRS) {�}
       Method(_SRS, 1) {�}
    }
    Device(LNKC){
       Name(_HID, EISAID("PNP0C0F"))                     // PCI interrupt link
       Name(_UID, 3)
       Name(_PRS, ResourceTemplate(){
           Interrupt(ResourceProducer,�) {12,14}     // IRQs 12,14
       })
       Method(_DIS) {�}
       Method(_CRS) {�}
       Method(_SRS, 1) {�}
    }
    Device(LNKD){
       Name(_HID, EISAID("PNP0C0F"))                     // PCI interrupt link
       Name(_UID, 4)
       Name(_PRS, ResourceTemplate(){
           Interrupt(ResourceProducer,�) {10,15}     // IRQs 10,15
       })
       Method(_DIS) {�}
       Method(_CRS) {�}
       Method(_SRS, 1) {�}
    }
    Device(PCI0){
       �
       Name(_PRT, Package{
           Package{0x0004FFFF, 0, \_SB_.LNKA, 0}, // Slot 1, INTA   // A fully
           Package{0x0004FFFF, 1, \_SB_.LNKB, 0}, // Slot 1, INTB   // qualified
           Package{0x0004FFFF, 2, \_SB_.LNKC, 0}, // Slot 1, INTC   // pathname
           Package{0x0004FFFF, 3, \_SB_.LNKD, 0}, // Slot 1, INTD   // can be used,
           Package{0x0005FFFF, 0, LNKB, 0},        // Slot 2, INTA   // or a simple
           Package{0x0005FFFF, 1, LNKC, 0},        // Slot 2, INTB   // name segment
           Package{0x0005FFFF, 2, LNKD, 0},        // Slot 2, INTC   // utilizing the
           Package{0x0005FFFF, 3, LNKA, 0},        // Slot 2, INTD   // search rules
           Package{0x0006FFFF, 0, LNKC, 0}         // Video, INTA
       })
    }
}

6.2.12 _PXM (Proximity)
This optional object is used to describe proximity domains within a machine. _PXM evaluates to an integer that identifies the device as belonging to a specific proximity domain. OSPM assumes that two devices in the same proximity domain are tightly coupled. OSPM could choose to optimize its behavior based on this. For example, in a system with four processors and six memory devices, there might be two separate proximity domains (0 and 1), each with two processors and three memory devices. In this case, the OS may decide to run some software threads on the processors in proximity domain 0 and others on the processors in proximity domain 1. Furthermore, for performance reasons, it could choose to allocate memory for those threads from the memory devices inside the proximity domain common to the processor and the memory device rather than from a memory device outside of the processor's proximity domain. _PXM can be used to identify any device belonging to a proximity domain. Children of a device belong to the same proximity domain as their parent unless they contain an overriding _PXM. Proximity domains do not imply any ejection relationships.
An OS makes no assumptions about the proximity or nearness of different proximity domains. The difference between two integers representing separate proximity domains does not imply distance between the proximity domains (in other words, proximity domain 1 is not assumed to be closer to proximity domain 0 than proximity domain 6).
Arguments:
None
Result Code:
An integer
6.2.13 _SLI (System Locality Information)
The System Locality Information Table (SLIT) table defined in Section 5.2.16, "System Locality Distance Information Table (SLIT)", provides relative distance information between all System Localities for use during OS initialization.
The value of each Entry[i,j] in the SLIT table, where i represents a row of a matrix and j represents a column of a matrix, indicates the relative distances from System Locality / Proximity Domain i to every other System Locality j in the system (including itself).
The i,j row and column values correlate to the value returned by the _PXM object in the ACPI namespace. See section 6.2.12, "_PXM (Proximity)" for more information.
Dynamic runtime reconfiguration of the system may cause the distance between System Localities to change.
_SLI is an optional object that enables the platform to provide the OS with updated relative System Locality distance information at runtime. _SLI provide OSPM with an update of the relative distance from System Locality i to all other System Localities in the system.
Arguments:
None.
Return Code:
If System Locality i ≥ N, where N is the number of System Localities, the _SLI method returns a buffer that contains the relative distances [(i, 0), (i, 1), �, (i, i-1), (i, i), (0, i), (1, i), �(i-1, i), (i, i)]; if System Locality i < N, the _SLI method returns a buffer that contains the relative distances [(i, 0), (i, 1), �, (i, i), �,(i, N-1), (0, i), (1, i),�(i, i), �, (N-1, i)]. Note: (i, i) is always a value of 10.
Example

The figure above diagrams a 4-node system where the nodes are numbered 0 through 3 (Node n = Node 3) and the granularity is at the node level for the NUMA distance information. In this example we assign System Localities / Proximity Domain numbers equal to the node numbers (0-3). The NUMA relative distances between proximity domains as implemented in this system are described in the matrix represented in Table 6-13. Proximity Domains are represented by the numbers in the top row and left column. Distances are represented by the values in cells internal in the table from the domains.
Table 6-13 Example Relative Distances Between Proximity Domains

Proximity Domain	0	1	2	3
0	10	15	20	18
1	15	10	16	24
2	20	16	10	12
3	18	24	12	10

An example of these distances between proximity domains encoded in a System Locality Information Table for consumption by OSPM at boot time is described in Table 6-14.

Table 6-14 Example System Locality Information Table

Field	Byte Length	Byte Offset	Description
Header
Signature	4	0	'SLIT'.
Length	4	4	60
Revision	1	8	1
Checksum	1	9	Entire table must sum to zero.
OEMID	6	10	OEM ID.
OEM Table ID	8	16	For the System Locality Information Table, the table ID is the manufacturer model ID.
OEM Revision	4	24	OEM revision of System Locality Information Table for supplied OEM Table ID.
Creator ID	4	28	Vendor ID of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the ID for the ASL Compiler.
Creator Revision	4	32	Revision of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the revision for the ASL Compiler.
Number of System Localities	8	36	4
Entry[0][0]	1	44	10
Entry[0][1]	1	45	15
Entry[0][2]	1	46	20
Entry[0][3]	1	47	18
Entry[1][0]	1	48	15
Entry[1][1]	1	49	10
Entry[1][2]	1	50	16
Entry[1][3]	1	51	24
Entry[2][0]	1	52	20
Entry[2][1]	1	53	16
Entry[2][2]	1	54	10
Entry[2][3]	1	55	12
Entry[3][0]	1	56	18
Entry[3][1]	1	57	24
Entry[3][2]	1	58	12
Entry[3][3]	1	59	10

If a new node, "Node 4", is added, then Table 6-15 represents the updated system's NUMA relative distances of proximity domains.
Table 6-15 Example Relative Distances Between Proximity Domains - 5 Node

Proximity Domain	0	1	2	3	4
0	10	15	20	18	17
1	15	10	16	24	21
2	20	16	10	12	14
3	18	24	12	10	23
4	17	21	14	23	10

The new node's _SLI object would evaluate to a buffer containing [17,21,14,23,10,17,21,14,23,10].
Note: some systems support interleave memory across the nodes. SLIT representation of these systems is implementation specific.
6.2.14 _SRS (Set Resource Settings)
This optional control method takes one byte stream argument that specifies a new resource allocation for a device. The resource descriptors in the byte stream argument must be specified in the same order as listed in the _CRS byte stream (for more information, see the _CRS object definition). A _CRS object can be used as a template to ensure that the descriptors are in the correct format.
The settings must take effect before the _SRS control method returns.
This method must not reference any operation regions that have not been declared available by a _REG method.
If the device is disabled, _SRS enables the device at the specified resources. _SRS is not used to disable a device; use the _DIS control method instead.
Arguments:
Byte stream
Result Code:
None
6.3 Device Insertion, Removal, and Status Objects
The objects defined in this section provide mechanisms for handling dynamic insertion and removal of devices and for determining device and notification processing status.
Device insertion and removal objects are also used for docking and undocking mobile platforms to and from a peripheral expansion dock. These objects give information about whether or not devices are present, which devices are physically in the same device (independent of which bus the devices live on), and methods for controlling ejection or interlock mechanisms.
The system is more stable when removable devices have a software-controlled, VCR-style ejection mechanism instead of a "surprise-style" ejection mechanism. In this system, the eject button for a device does not immediately remove the device, but simply signals the operating system. OSPM then shuts down the device, closes open files, unloads the driver, and sends a command to the hardware to eject the device.

In ACPI, the sequence of events for dynamically inserting a device follows the process below. Notice that this process supports hot, warm, and cold insertion of devices.

1.    If the device is physically inserted while the computer is in the working state (in other words, hot insertion), the hardware generates a general-purpose event.
2.    The control method servicing the event uses the Notify(device,0) command to inform OSPM of the bus that the new device is on or the device object for the new device the Notify command points to the device object for the new device, the control method must have changed the device's status returned by _STA to indicate that the device is now present. The performance of this process can be optimized by having the object of the Notify as close as possible, in the namespace hierarchy, to where the new device resides. The Notify command can also be used from the _WAK control method (for more information about _WAK, see section 7.3.7 "\_WAK (System Wake)") to indicate device changes that may have occurred while the computer was sleeping. For more information about the Notify command, see section 5.6.3 "Device Object Notification."."
3.    OSPM uses the identification and configuration objects to identify, configure, and load a device driver for the new device and any devices found below the device in the hierarchy.
4.    If the device has a _LCK control method, OSPM may later run this control method to lock the device.
The new device referred to in step 2 need not be a single device, but could be a whole tree of devices. For example, it could point to the PCI-PCI bridge docking connector. OSPM will then load and configure all devices it found below that bridge. The control method can also point to several different devices in the hierarchy if the new devices do not all live under the same bus. (in other words, more than one bus goes through the connector).
For removing devices, ACPI supports both hot removal (system is in the S0 state), and warm removal (system is in a sleep state:S1-S4). This is done using the _EJx control methods. Devices that can be ejected include an _EJx control method for each sleeping state the device supports (a maximum of 2 _EJx objects can be listed). For example, hot removal devices would supply an _EJ0;warm removal devices would use one of _EJ1-EJ4. These control methods are used to signal the hardware when an eject is to occur.
The sequence of events for dynamically removing a device goes as follows:
1.    The eject button is pressed and generates a general-purpose event the system was in a sleeping state, it should wake the computer).
2.    The control method for the event uses the Notify(device, 3) command to inform OSPM which specific device the user has requested to eject. Notify does not need to be called for every device that may be ejected, but for the top-level device. Any child devices in the hierarchy or any ejection-dependent devices on this device (as described by _EJD, below) are automatically removed.
3.    The OS shuts down and unloads devices that will be removed.
4.    If the device has a _LCK control method, OSPM runs this control method to unlock the device.
5.    The OS looks to see what _EJx control methods are present for the device. If the removal event will cause the system to switch to battery power (in other words, an undock) and the battery is low, dead, or not present, OSPM uses the lowest supported sleep state _EJx listed; otherwise it uses the highest state _EJx. Having made this decision, OSPM runs the appropriate _EJx control method to prepare the hardware for eject.
6.    Warm removal requires that the system be put in a sleep state. If the removal will be a warm removal, OSPM puts the system in the appropriate Sx state. If the removal will be a hot removal, OSPM skips to step 8, below.
7.    For warm removal, the system is put in a sleep state. Hardware then uses any motors, and so on, to eject the device. Immediately after ejection, the hardware transitions the computer to S0. If the system was sleeping when the eject notification came in, the OS returns the computer to a sleeping state consistent with the user's wake settings.
8.    OSPM calls _STA to determine if the eject successfully occurred this case, control methods do not need to use the Notify(device,3) command to tell OSPM of the change in _STA) If there were any mechanical failures, _STA returns 3: device present and not functioning, and OSPM informs the user of the problem.
Note: This mechanism is the same for removing a single device and for removing several devices, as in an undock.

ACPI does not disallow surprise-style removal of devices;however, this type of removal is not recommended because system and data integrity cannot be guaranteed when a surprise-style removal occurs. Because the OS is not informed, its device drivers cannot save data buffers and it cannot stop accesses to the device before the device is removed. To handle surprise-style removal, a general-purpose event must be raised. Its associated control method must use the Notify command to indicate which bus the device was removed from.
The device insertion and removal objects are listed in Table 6-16.
Table 6-16 Device Insertion, Removal, and Status Objects

Object	Description
_EDL	Object that evaluates to a package of namespace references of device objects that depend on the device containing _EDL. Whenever the named device is ejected, OSPM ejects all dependent devices.
_EJD	Object that evaluates to the name of a device object on which a device depends. Whenever the named device is ejected, the dependent device must receive an ejection notification.
_EJx	Control method that ejects a device.
_LCK	Control method that locks or unlocks a device.
_OST	Control method invoked by OSPM to convey processing status to the platform..
_RMV	Object that indicates that the given device is removable.
_STA	Control method that returns a device's status.

6.3.1 _EDL (Eject Device List)
This object evaluates to a package of namespace references containing the names of device objects that depend on the device under which the _EDL object is declared. This is primarily used to support docking stations. Before the device under which the _EDL object is declared may be ejected, OSPM prepares the devices listed in the _EDL object for physical removal.
Before OSPM ejects a device via the device's _EJx methods, all dependent devices listed in the package returned by _EDL are prepared for removal. Notice that _EJx methods under the dependent devices are not executed.
When describing a platform that includes a docking station, an _EDL object is declared under the docking station device. For example, if a mobile system can attach to two different types of docking stations, _EDL is declared under both docking station devices and evaluates to the packaged list of devices that must be ejected when the system is ejected from the docking station.
An ACPI-compliant OS evaluates the _EDL method just prior to ejecting the device.
6.3.2 _EJD (Ejection Dependent Device)
This object is used to specify the name of a device on which the device, under which this object is declared, is dependent. This object is primarily used to support docking stations. Before the device indicated by _EJD is ejected, OSPM will prepare the dependent device (in other words, the device under which this object is declared) for removal.
_EJD is evaluated once when the ACPI table loads. The EJx methods of the device indicated by _EJD will be used to eject all the dependent devices. A device's dependents will be ejected when the device itself is ejected.
Note: OSPM will not execute a dependent device's _EJx methods when the device indicated by _EJD is ejected.

When describing a platform that includes a docking station, usually more than one _EJD object will be needed. For example, if a dock attaches both a PCI device and an ACPI-configured device to a mobile system, then both the PCI device description package and the ACPI-configured device description package must include an _EJD object that evaluates to the name of the docking station (the name specified in an _ADR or _HID object in the docking station's description package). Thus, when the docking connector signals an eject request, OSPM first attempts to disable and unload the drivers for both the PCI and ACPI configured devices.
Note: An ACPI 1.0 OS evaluates the _EJD methods only once during the table load process. This greatly restricts a table designer's freedom to describe dynamic dependencies such as those created in scenarios with multiple docking stations. This restriction is illustrated in the example below; the _EJD information supplied via and ACPI 1.0-compatible namespace omits the IDE2 device from DOCK2's list of ejection dependencies. Starting in ACPI 2.0, OSPM is presented with a more in-depth view of the ejection dependencies in a system by use of the _EDL methods.
Example
An example use of _EJD and _EDL is as follows:

Scope(\_SB.PCI0) {

    Device(DOCK1) {   // Pass through dock – DOCK1
       Name(_ADR, �)
       Method(_EJ0, 0) {�}
       Method(_DCK, 1) {�}
       Name(_BDN, �)
       Method(_STA, 0) {0xF}
       Name(_EDL, Package( ) { // DOCK1 has two dependent devices – IDE2 and CB2
              \_SB.PCI0.IDE2,

           \_SB.PCI0.CB2})
    }
    Device(DOCK2) {   // Pass through dock – DOCK2
       Name(_ADR, �)
       Method(_EJ0, 0) {�}
       Method(_DCK, 1) {�}
       Name(_BDN, �)
       Method(_STA, 0) {0x0}
       Name(_EDL, Package( ) { // DOCK2 has one dependent device – IDE2
           \_SB.PCI0.IDE2})
    }

    Device(IDE1) {    // IDE Drive1 not dependent on the dock
       Name(_ADR, �)
    }

    Device(IDE2) {    // IDE Drive2
       Name(_ADR, �)
       Name(_EJD,"\\_SB.PCI0.DOCK1")   // Dependent on DOCK1
    }

    Device(CB2) {     // CardBus Controller
       Name(_ADR, �)
       Name(_EJD,"\\_SB.PCI0.DOCK1")   // Dependent on DOCK1
    }
} // end \_SB.PCIO
6.3.3   _EJx (Eject)
These control methods are optional and are supplied for devices that support a software-controlled VCR-style ejection mechanism or that require an action be performed such as isolation of power/data lines before the device can be removed from the system. To support warm (system is in a sleep state) and hot (system is in S0) removal, an _EJx control method is listed for each sleep state from which the device supports removal, where x is the sleeping state supported. For example, _EJ0 indicates the device supports hot removal; _EJ1–EJ4 indicate the device supports warm removal.

For hot removal, the device must be immediately ejected when OSPM calls the _EJ0 control method. The _EJ0 control method does not return until ejection is complete. After calling _EJ0, OSPM verifies the device no longer exists to determine if the eject succeeded. For _HID devices, OSPM evaluates the _STA method. For _ADR devices, OSPM checks with the bus driver for that device.
For warm removal, the _EJ1–_EJ4 control methods do not cause the device to be immediately ejected. Instead, they set proprietary registers to prepare the hardware to eject when the system goes into the given sleep state. The hardware ejects the device only after OSPM has put the system in a sleep state by writing to the SLP_EN register. After the system resumes, OSPM calls _STA to determine if the eject succeeded.
The _EJx control methods take one parameter to indicate whether eject should be enabled or disabled:
1–Hot eject or mark for ejection
0–Cancel mark for ejection (EJ0 will never be called with this value)
A device object may have multiple _EJx control methods. First, it lists an EJx control method for the preferred sleeping state to eject the device. Optionally, the device may list an EJ4 control method to be used when the system has no power (for example, no battery) after the eject. For example, a hot-docking notebook might list _EJ0 and _EJ4.
6.3.4   _LCK (Lock)
This control method is optional and is required only for a device that supports a software-controlled locking mechanism. When the OS invokes this control method, the associated device is to be locked or unlocked based upon the value of the argument that is passed. On a lock request, the control method must not complete until the device is completely locked.
The _LCK control method takes one parameter that indicates whether or not the device should be locked:
1 –Lock the device.
0–Unlock the device.
When describing a platform, devices use either a _LCK control method or an _EJx control method for a device.
6.3.5   _OST (OSPM Status Indication)
This object is an optional control method that is invoked by OSPM to indicate processing status to the platform. During device ejection, device hot add, or other event processing, OSPM may need to perform specific handshaking with the platform. OSPM may also need to indicate to the platform its inability to complete a requested operation; for example, when a user presses an ejection button for a device that is currently in use or is otherwise currently incapable of being ejected. In this case, the processing of the ACPI Eject Request notification by OSPM fails. OSPM may indicate this failure to the platform through the invocation of the _OST control method. As a result of the status notification indicating ejection failure, the platform may take certain action including reissuing the notification or perhaps turning on an appropriate indicator light to signal the failure to the user.
Arguments:
Arg0 – source_event: DWordConst
If the value of source_event is <= 0xFF, this argument is the ACPI notification value whose processing generated the status indication. This is the value that was passed into the Notify operator.
If the value of source_event is 0x100 or greater then the OSPM status indication is a result of an OSPM action as indicated in Table 6-17. For example, a value of 0x103 will be passed into _OST for this argument upon the failure of a user interface invoked device ejection.
If OSPM is unable to identify the originating notification value, OSPM invokes _OST with a value that contains all bits set (ones) for this parameter.
Arg1 – Status Code: DWordConst. OSPM indicates a notification value specific status. See Tables 6-18 and 6-19 for status code descriptions.
Arg2 – A buffer containing detailed OSPM-specific information about the status indication. This argument may be the null string.
Results:
None
Table 6-17   _OST Source Event Codes

Source Event Code	Description
0-0xFF	Reserved for Notification Values
0x100-0x102	Reserved
0x103	Ejection Processing
0x104-0x1FF	Reserved
0x200	Insertion Processing
0x201-0xFFFFFFFF	Reserved

Table 6-18 General Processing Status Codes

Status Code	Description
0	Success
1	Non-specific failure
2	Unrecognized Notify Code
3-0x7F	Reserved
0x80-0xFFFFFFFF	Notification value specific status codes

Table 6-19 Ejection Request / Ejection Processing (Source Events: 0x03 and 0x103) Status Codes

Status Code	Description
0x80	Device ejection not supported by OSPM
0x81	Device in use by application
0x82	Device Busy
0x83	Ejection dependency is busy or not supported for ejection by OSPM
0x84	Ejection is in progress (pending)
0x85-0xFFFFFFFF	Reserved

Table 6-20 Insertion Processing (Source Event: 0x200) Status Codes

Status Code	Description
0x80	Device insertion in progress (pending)
0x81	Device driver load failure
0x82-0x8F	Reserved
0x90-0x9F	Insertion failure – Resources Unavailable as described by the following bit encodings: Bit[3] Bus Numbers Bit[2] Interrupts Bit[1] I/O Bit[0] Memory
0xA0-0xFFFFFFFF	Reserved

It is possible for the platform to issue multiple notifications to OSPM and for OSPM to process the notifications asynchronously. As such, OSPM may invoke _OST for notifications independent of the order the notification are conveyed by the platform or by software to OSPM..
The figure below provides and example event flow of device ejection on a platform employing the _OST object.

Figure 6-1   Device Ejection Flow Example Using _OST

NOTE: To maintain compatibility with OSPM implementations of previous revisions of the ACPI specification, the platform must not rely on OSPM's evaluation of the _OST object for proper platform operation.
Example ASL for _OST usage:

Scope(\_SB.PCI4) {
    OperationRegion(LED1, SystemIO, 0x10C0, 0x20)
    Field(LED1, AnyAcc, NoLock, Preserve)
    {   // LED controls
       S0LE, 1,            // Slot 0 Ejection Progress LED
       S0LF, 1,            // Slot 0 Ejection Failure LED
       S1LE, 1,            // Slot 1 Ejection Progress LED
       S1LF, 1,            // Slot 1 Ejection Failure LED
       S2LE, 1,            // Slot 2 Ejection Progress LED
       S2LF, 1,            // Slot 2 Ejection Failure LED
       S3LE, 1,            // Slot 3 Ejection Progress LED
       S3LF, 1             // Slot 3 Ejection Failure LED
    }

    Device(SLT3) {                      // hot plug device
       Name(_ADR, 0x000C0003)
       Method(_OST, 3, Serialized) {       // OS calls _OST with notify code 3 or 0x103
                                        // and status codes 0x80-0x83
                                        // to indicate a hot remove request failure.
                                        // Status code 0x84 indicates an ejection
                                        // request pending.

           If(LEqual(Arg0,Ones))        // Unspecified event
           {
              // Perform generic event processing here
           }

           Switch(And(Arg0,0xFF))          // Mask to retain low byte
           {
              Case(0x03)               // Ejection request
              {
                  Switch(Arg1)
                  {
                      Case(Package(){0x80, 0x81, 0x82, 0x83})
                      {          // Ejection Failure for some reason
                         Store(Zero, ^^S3LE)   // Turn off Ejection Progress LED
                         Store(One, ^^S3LF)       // Turn on Ejection Failure LED
                      }
                      Case(0x84)        // Eject request pending
                      {
                         Store(One, ^^S3LE)       // Turn on Ejection Request LED
                         Store(Zero, ^^S3LF)   // Turn off Ejection Failure LED
                      }
                  }
              }
           }
       } // end _OST

       Method(_EJ0, 1)              // Successful ejection sequence
       {
           Store(Zero, ^^S3LE)      // Turn off Ejection Progress LED
       }
    } // end SLT3
} // end scope \_SB.PCI4

Scope (_GPE)
{
    _E13
    {
       Store(One, \_SB.PCI4.S3LE)          // Turn on ejection request LED
       Notify(SLT3, 3)                 // Ejection request driven from GPE13
    }
}

6.3.6   _RMV (Remove)
The optional _RMV object indicates to OSPM whether the device can be removed while the system is in the working state and does not require any ACPI system firmware actions to be performed for the device to be safely removed from the system (in other words, any device that only supports surprise-style removal). Any such removable device that does not have _LCK or _EJx control methods must have an _RMV object. This allows OSPM to indicate to the user that the device can be removed and to provide a way for shutting down the device before removing it. OSPM will transition the device into D3 before telling the user it is safe to remove the device.
This method is reevaluated after a device-check notification.
Arguments:
            None
Result Code:
            0 – The device cannot be removed.
            1 – The device can be removed.
Note: Operating Systems implementing ACPI 1.0 interpret the presence of this object to mean that the device is removable.

6.3.7   _STA (Status)
This object returns the status of a device, which can be one of the following: enabled, disabled, or removed.
Arguments:
None
Result Code (bitmap):
Bit 0           Set if the device is present.
Bit 1           Set if the device is enabled and decoding its resources.
Bit 2           Set if the device should be shown in the UI.
Bit 3           Set if the device is functioning properly (cleared if the device failed its diagnostics).
Bit 4           Set if the battery is present.
Bits 5–31     Reserved (must be cleared).
If bit 0 is cleared, then bit 1 must also be cleared (in other words, a device that is not present cannot be enabled).
A device can only decode its hardware resources if both bits 0 and 1 are set. If the device is not present (bit 0 cleared) or not enabled (bit 1 cleared), then the device must not decode its resources.
If a device is present in the machine, but should not be displayed in OSPM user interface, bit 2 is cleared. For example, a notebook could have joystick hardware (thus it is present and decoding its resources), but the connector for plugging in the joystick requires a port replicator the port replicator is not plugged in, the joystick should not appear in the UI, so bit 2 is cleared.
_STA may return bit 0 clear (not present) with bit 3 set (device is functional). This case is used to indicate a valid device for which no device driver should be loaded (for example, a bridge device.) Children of this device may be present and valid. OSPM should continue enumeration below a device whose _STA returns this bit combination.
OSPM evaluates the _STA object before it evaluates a device _INI method. The return values of the Present and Functioning bits determines whether _INI should be evaluated and whether children of the device should be enumerated and initialized. See section 6.5.1, "_INI (Init)".
If a device object (including the processor object) does not have an _STA object, then OSPM assumes that all of the above bits are set (in other words, the device is present, enabled, shown in the UI, and functioning).
This method must not reference any operation regions that have not been declared available by a _REG method.
6.4   Resource Data Types for ACPI
The _CRS, _PRS, and _SRS control methods use packages of resource descriptors to describe the resource requirements of devices.
6.4.1   ASL Macros for Resource Descriptors
ASL includes some macros for creating resource descriptors. The ASL syntax for these macros is defined in section 17.5, "ASL Operator Reference", along with the other ASL operators.
6.4.2   Small Resource Data Type
A small resource data type may be 2 to 8 bytes in size and adheres to the following format:
Table 6-21   Small Resource Data Type Tag Bit Definitions

Offset	Field
Byte 0	Tag Bit[7]	Tag Bits[6:3]	Tag Bits [2:0]
	Type–0 (Small item)	Small item name	Length–n bytes
Bytes 1 to n	Data bytes (Length 0 – 7)

The following small information items are currently defined for Plug and Play devices:
Table 6-22 Small Resource Items

Small Item Name	Value
Reserved	0x00-0x03
IRQ Format Descriptor	0x04
DMA Format Descriptor	0x05
Start Dependent Functions Descriptor	0x06
End Dependent Functions Descriptor	0x07
I/O Port Descriptor	0x08
Fixed Location I/O Port Descriptor	0x09
Reserved	0x0A–0x0D
Vendor Defined Descriptor	0x0E
End Tag Descriptor	0x0F

6.4.2.1 IRQ Descriptor
Type 0, Small Item Name 0x4, Length = 2 or 3
The IRQ data structure indicates that the device uses an interrupt level and supplies a mask with bits set indicating the levels implemented in this device. For standard PC-AT implementation there are 15 possible interrupts so a two-byte field is used. This structure is repeated for each separate interrupt required.
Table 6-23 IRQ Descriptor Definition

Offset	Field Name
Byte 0	Value = 0x22 or 0x23 (0010001nB) – Type = 0, Small item name = 0x4, Length = 2 or 3
Byte 1	IRQ mask bits[7:0], _INT Bit[0] represents IRQ0, bit[1] is IRQ1, and so on.
Byte 2	IRQ mask bits[15:8], _INT Bit[0] represents IRQ8, bit[1] is IRQ9, and so on.
Byte 3	IRQ Information. Each bit, when set, indicates this device is capable of driving a certain type of interrupt. (Optional—if not included then assume edge sensitive, high true interrupts.) These bits can be used both for reporting and setting IRQ resources. Note: This descriptor is meant for describing interrupts that are connected to PIC-compatible interrupt controllers, which can only be programmed for Active-High-Edge-Triggered or Active-Low-Level-Triggered interrupts other combination is illegal. The Extended Interrupt Descriptor can be used to describe other combinations. Bit[7:5] Reserved (must be 0) Bit[4] Interrupt is sharable, _SHR Bit[3] Interrupt Polarity, _LL 0 Active-High – This interrupt is sampled when the signal is high, or true 1 Active-Low – This interrupt is sampled when the signal is low, or false. Bit[2:1] Ignored Bit[0] Interrupt Mode, _HE 0 Level-Triggered – Interrupt is triggered in response to signal in a low state. 1 Edge-Triggered – Interrupt is triggered in response to a change in signal state from low to high.

Note: Low true, level sensitive interrupts may be electrically shared, but the process of how this might work is beyond the scope of this specification.
Note: If byte 3 is not included, High true, edge sensitive, non-shareable is assumed.
See section 17.5.57, "IRQ (Interrupt Resource Descriptor Macro)," and section 17.5.58, "IRQNoFlags (Interrupt Resource Descriptor Macro)," for a description of the ASL macros that create an IRQ descriptor.
6.4.2.2 DMA Descriptor
Type 0, Small Item Name 0x5, Length = 2
The DMA data structure indicates that the device uses a DMA channel and supplies a mask with bits set indicating the channels actually implemented in this device. This structure is repeated for each separate channel required.
Table 6-24 DMA Descriptor Definition

Offset	Field Name
Byte 0	Value = 0x2A (00101010B) – Type = 0, Small item name = 0x5, Length = 2
Byte 1	DMA channel mask bits[7:0] (channels 0 – 7), _DMA Bit[0] is channel 0, etc.
Byte 2	Bit[7] Reserved (must be 0) Bits[6:5] DMA channel speed supported, _TYP 00 Indicates compatibility mode 01 Indicates Type A DMA as described in the EISA 10 Indicates Type B DMA 11 Indicates Type F Bits[4:3] Ignored Bit[2] Logical device bus master status, _BM 0 Logical device is not a bus master 1 Logical device is a bus master Bits[1:0] DMA transfer type preference, _SIZ 00 8-bit only 01 8- and 16-bit 10 16-bit only 11 Reserved

See section 17.5.30, "DMA (DMA Resource Descriptor Macro)," for a description of the ASL macro that creates a DMA descriptor.
6.4.2.3 Start Dependent Functions Descriptor
Type 0, Small Item Name 0x6, Length = 0 or 1
Each logical device requires a set of resources. This set of resources may have interdependencies that need to be expressed to allow arbitration software to make resource allocation decisions about the logical device. Dependent functions are used to express these interdependencies data structure definitions for dependent functions are shown here. For a detailed description of the use of dependent functions refer to the next section.
Table 6-25 Start Dependent Functions Descriptor Definition

Offset	Field Name
Byte 0	Value = 0x30 or 0x31 (0011000nB) – Type = 0, small item name = 0x6, Length = 0 or 1

Start Dependent Function fields may be of length 0 or 1 bytes. The extra byte is optionally used to denote the compatibility or performance/robustness priority for the resource group following the Start DF tag. The compatibility priority is a ranking of configurations for compatibility with legacy operating systems. This is the same as the priority used in the PNPBIOS interface. For example, for compatibility reasons, the preferred configuration for COM1 is IRQ4, I/O 3F8-3FF. The performance/robustness performance is a ranking of configurations for performance and robustness reasons. For example, a device may have a high-performance, bus mastering configuration that may not be supported by legacy operating systems bus-mastering configuration would have the highest performance/robustness priority while its polled I/O mode might have the highest compatibility priority.
If the Priority byte is not included, this indicates the dependent function priority is 'acceptable'. This byte is defined as:
Table 6-26 Start Dependent Function Priority Byte Definition

Bits	Definition
1:0	Compatibility priority. Acceptable values are: 0 Good configuration: Highest Priority and preferred configuration 1 Acceptable configuration: Lower Priority but acceptable configuration 2 Sub-optimal configuration: Functional configuration but not optimal 3 Reserved
3:2	Performance/robustness. Acceptable values are: 0 Good configuration: Highest Priority and preferred configuration 1 Acceptable configuration: Lower Priority but acceptable configuration 2 Sub-optimal configuration: Functional configuration but not optimal 3 Reserved
7:4	Reserved (must be 0)

Notice that if multiple Dependent Functions have the same priority, they are further prioritized by the order in which they appear in the resource data structure. The Dependent Function that appears earliest (nearest the beginning) in the structure has the highest priority, and so on.
See section 17.5.111, "StartDependentFn (Start Dependent Function Resource Descriptor Macro)," for a description of the ASL macro that creates a Start Dependent Function descriptor.
6.4.2.4 End Dependent Functions Descriptor
Type 0, Small Item Name 0x7, Length = 0
Only one End Dependent Function item is allowed per logical device. This enforces the fact that Dependent Functions cannot be nested.
Table 6-27 End Dependent Functions Descriptor Definition

Offset	Field Name
Byte 0	Value = 0x38 (00111000B) – Type = 0, Small item name = 0x7, Length =0

See section 17.5.37, "EndDependentFn (End Dependent Function Resource Descriptor Macro," for a description of the ASL macro that creates an End Dependent Functions descriptor.
6.4.2.5 I/O Port Descriptor
Type 0, Small Item Name 0x8, Length = 7
There are two types of descriptors for I/O ranges first descriptor is a full function descriptor for programmable devices second descriptor is a minimal descriptor for old ISA cards with fixed I/O requirements that use a 10-bit ISA address decode. The first type descriptor can also be used to describe fixed I/O requirements for ISA cards that require a 16-bit address decode. This is accomplished by setting the range minimum base address and range maximum base address to the same fixed I/O value.
Table 6-28 I/O Port Descriptor Definition

Offset	Field Name	Definition
Byte 0	I/O Port Descriptor	Value = 0x47 (01000111B) – Type = 0, Small item name = 0x8, Length = 7
Byte 1	Information	Bits[7:1] Reserved and must be 0 Bit[0] (_DEC) 1 The logical device decodes 16-bit addresses 0 The logical device only decodes address bits[9:0]
Byte 2	Range minimum base address, _MIN bits[7:0]	Address bits[7:0] of the minimum base I/O address that the card may be configured for.
Byte 3	Range minimum base address, _MIN bits[15:8]	Address bits[15:8] of the minimum base I/O address that the card may be configured for.
Byte 4	Range maximum base address, _MAX bits[7:0]	Address bits[7:0] of the maximum base I/O address that the card may be configured for.
Byte 5	Range maximum base address, _MAX bits[15:8]	Address bits[15:8] of the maximum base I/O address that the card may be configured for.
Byte 6	Base alignment, _ALN	Alignment for minimum base address, increment in 1-byte blocks.
Byte 7	Range length, _LEN	The number of contiguous I/O ports requested.

See section 17.5.56, "IO (IO Resource Descriptor Macro," for a description of the ASL macro that creates an I/O Port descriptor.
6.4.2.6 Fixed Location I/O Port Descriptor
Type 0, Small Item Name 0x9, Length = 3
This descriptor is used to describe 10-bit I/O locations.
Table 6-29 Fixed-Location I/O Port Descriptor Definition

Offset	Field Name	Definition
Byte 0	Fixed Location I/O Port Descriptor	Value = 0x4B (01001011B) – Type = 0, Small item name = 0x9, Length = 3
Byte 1	Range base address, _BAS bits[7:0]	Address bits[7:0] of the base I/O address that the card may be configured for. This descriptor assumes a 10-bit ISA address decode.
Byte 2	Range base address, _BAS bits[9:8]	Address bits[9:8] of the base I/O address that the card may be configured for. This descriptor assumes a 10-bit ISA address decode.
Byte 3	Range length, _LEN	The number of contiguous I/O ports requested.

See section 17.5.47, "FixedIO (Fixed I/O Resource Descriptor Macro," for a description of the ASL macro that creates a Fixed I/O Port descriptor.
6.4.2.7 Vendor-Defined Descriptor
Type 0, Small Item Name 0xE, Length = 1 to 7
The vendor defined resource data type is for vendor use.
Table 6-30 Vendor-Defined Resource Descriptor Definition

Offset	Field Name
Byte 0	Value = 0x71 – 0x77 (01110nnnB) – Type = 0, small item name = 0xE, Length = 1–7
Byte 1 to 7	Vendor defined

See VendorShort (page 218) for a description of the ASL macro that creates a short vendor-defined resource descriptor.
6.4.2.8 End Tag
Type 0, Small Item Name 0xF, Length = 1
The End tag identifies an end of resource data.
Note: If the checksum field is zero, the resource data is treated as if the checksum operation succeeded. Configuration proceeds normally.
Table 6-31 End Tag Definition

Offset	Field Name
Byte 0	Value = 0x78 (01111001B) – Type = 0, Small item name = 0xF, Length = 1
Byte 1	Checksum covering all resource data after the serial identifier. This checksum is generated such that adding it to the sum of all the data bytes will produce a zero sum.

The End Tag is automatically generated by the ASL compiler at the end of the ResourceTemplate statement.
6.4.3 Large Resource Data Type
To allow for larger amounts of data to be included in the configuration data structure the large format is shown below. This includes a 16-bit length field allowing up to 64 KB of data.
Table 6-32 Large Resource Data Type Tag Bit Definitions

Offset	Field Name
Byte 0	Value = 1xxxxxxxB – Type = 1 (Large item), Large item name = xxxxxxxB
Byte 1	Length of data items bits[7:0]
Byte 2	Length of data items bits[15:8]
Bytes 3 to (Length + 2)	Actual data items

The following large information items are currently defined for Plug and Play ISA devices:
Table 6-33 Large Resource Items

Large Item Name	Value
Reserved	0x00
24-bit Memory Range Descriptor	0x01
Generic Register Descriptor	0x02
Reserved	0x03
Vendor Defined Descriptor	0x04
32-bit Memory Range Descriptor	0x05
32-bit Fixed Location Memory Range Descriptor	0x06
DWORD Address Space Descriptor	0x07
WORD Address Space Descriptor	0x08
Extended IRQ Descriptor	0x09
QWORD Address Space Descriptor	0x0A
Extended Address Space Descriptor	0x0B
Reserved	0x0C – 0x7F

6.4.3.1 24-Bit Memory Range Descriptor
Type 1, Large Item Name 0x1
The 24-bit memory range descriptor describes a device's memory range resources within a 24-bit address space.

Table 6-34 24-bit Memory Range Descriptor Definition
Offset	Field Name, ASL Field Name	Definition
Byte 0	24-bit Memory Range Descriptor	Value = 0x81 (10000001B) – Type = 1, Large item name = 0x01
Byte 1	Length, bits[7:0]	Value = 0x09 (9)
Byte 2	Length, bits[15:8]	Value = 0x00
Byte 3	Information	This field provides extra information about this memory. Bit[7:1] Ignored Bit[0] Write status, _RW 1 writeable (read/write) 0 non-writeable (read-only)
Byte 4	Range minimum base address, _MIN, bits[7:0]	Address bits[15:8] of the minimum base memory address for which the card may be configured.
Byte 5	Range minimum base address, _MIN, bits[15:8]	Address bits[23:16] of the minimum base memory address for which the card may be configured
Byte 6	Range maximum base address, _MAX, bits[7:0]	Address bits[15:8] of the maximum base memory address for which the card may be configured.
Byte 7	Range maximum base address, _MAX, bits[15:8]	Address bits[23:16] of the maximum base memory address for which the card may be configured
Byte 8	Base alignment, _ALN, bits[7:0]	This field contains the lower eight bits of the base alignment. The base alignment provides the increment for the minimum base address. (0x0000 = 64 KB)
Byte 9	Base alignment, _ALN, bits[15:8]	This field contains the upper eight bits of the base alignment. The base alignment provides the increment for the minimum base address. (0x0000 = 64 KB)
Byte 10	Range length, _LEN, bits[7:0]	This field contains the lower eight bits of the memory range length. The range length provides the length of the memory range in 256 byte blocks.
Byte 11	Range length, _LEN, bits[15:8]	This field contains the upper eight bits of the memory range length. The range length field provides the length of the memory range in 256 byte blocks.

Notes:
· Address bits [7:0] of memory base addresses are assumed to be 0.
· A Memory range descriptor can be used to describe a fixed memory address by setting the range minimum base address and the range maximum base address to the same value.
· 24-bit Memory Range descriptors are used for legacy devices.
· Mixing of 24-bit and 32-bit memory descriptors on the same device is not allowed.
See section 17.5.72, "Memory24 (Memory Resource Descriptor Macro)," for a description of the ASL macro that creates a 24-bit Memory descriptor.
6.4.3.2 Vendor-Defined Descriptor
Type 1, Large Item Name 0x4
The vendor defined resource data type is for vendor use.
Table 6-35 Large Vendor-Defined Resource Descriptor Definition

Offset	Field Name	Definition
Byte 0	Vendor Defined Descriptor	Value = 0x84 (10000100B) – Type = 1, Large item name = 0x04
Byte 1	Length, bits[7:0]	Lower eight bits of data length (UUID and vendor data)
Byte 2	Length, bits[15:8]	Upper eight bits of data length (UUID and vendor data)
Byte 3	UUID specific descriptor sub type	UUID specific descriptor sub type value
Byte 4-19	UUID	UUID Value
Byte 20-(Length+20)	Vendor Defined Data	Vendor defined data bytes

ACPI 3.0 defines the UUID specific descriptor subtype field and the UUID field to address potential collision of the use of this descriptor. It is strongly recommended that all newly defined vendor descriptors use these fields prior to Vendor Defined Data.
See VendorLong (page 218) for a description of the ASL macro that creates a long vendor-defined resource descriptor.
6.4.3.3 32-Bit Memory Range Descriptor
Type 1, Large Item Name 0x5
This memory range descriptor describes a device's memory resources within a 32-bit address space.
Table 6-36 32-Bit Memory Range Descriptor Definition

Offset	Field Name	Definition
Byte 0	32-bit Memory Range Descriptor	Value = 0x85 (10000101B) – Type = 1, Large item name = 0x05
Byte 1	Length, bits[7:0]	Value = 0x11 (17)
Byte 2	Length, bits[15:8]	Value = 0x00
Byte 3	Information	This field provides extra information about this memory. Bit[7:1] Ignored Bit[0] Write status, _RW 1 writeable (read/write) 0 non-writeable (read-only)
Byte 4	Range minimum base address, _MIN, bits[7:0]	Address bits[7:0] of the minimum base memory address for which the card may be configured.
Byte 5	Range minimum base address, _MIN, bits[15:8]	Address bits[15:8] of the minimum base memory address for which the card may be configured.
Byte 6	Range minimum base address, _MIN, bits[23:16]	Address bits[23:16] of the minimum base memory address for which the card may be configured.
Byte 7	Range minimum base address, _MIN, bits[31:24]	Address bits[31:24] of the minimum base memory address for which the card may be configured.
Byte 8	Range maximum base address, _MAX, bits[7:0]	Address bits[7:0] of the maximum base memory address for which the card may be configured.
Byte 9	Range maximum base address, _MAX, bits[15:8]	Address bits[15:8] of the maximum base memory address for which the card may be configured.
Byte 10	Range maximum base address, _MAX, bits[23:16]	Address bits[23:16] of the maximum base memory address for which the card may be configured.
Byte 11	Range maximum base address, _MAX, bits[31:24]	Address bits[31:24] of the maximum base memory address for which the card may be configured.
Byte 12	Base alignment, _ALN bits[7:0]	This field contains Bits[7:0] of the base alignment. The base alignment provides the increment for the minimum base address.
Byte 13	Base alignment, _ALN bits[15:8]	This field contains Bits[15:8] of the base alignment. The base alignment provides the increment for the minimum base address.
Byte 14	Base alignment, _ALN bits[23:16]	This field contains Bits[23:16] of the base alignment. The base alignment provides the increment for the minimum base address.
Byte 15	Base alignment, _ALN bits[31:24]	This field contains Bits[31:24] of the base alignment. The base alignment provides the increment for the minimum base address.
Byte 16	Range length, _LEN bits[7:0]	This field contains Bits[7:0] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
Byte 17	Range length, _LEN bits[15:8]	This field contains Bits[15:8] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
Byte 18	Range length, _LEN bits[23:16]	This field contains Bits[23:16] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
Byte 19	Range length, _LEN bits[31:24]	This field contains Bits[31:24] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.

Note: Mixing of 24-bit and 32-bit memory descriptors on the same device is not allowed.
See section 17.5.73, "Memory32 (Memory Resource Descriptor Macro)," for a description of the ASL macro that creates a 32-bit Memory descriptor.
6.4.3.4 32-Bit Fixed Memory Range Descriptor
Type 1, Large Item Name 0x6
This memory range descriptor describes a device's memory resources within a 32-bit address space.
Table 6-37 32-bit Fixed-Location Memory Range Descriptor Definition

Offset	Field Name	Definition
Byte 0	32-bit Fixed Memory Range Descriptor	Value = 0x86 (10000110B) – Type = 1, Large item name = 0x06
Byte 1	Length, bits[7:0]	Value = 0x09 (9)
Byte 2	Length, bits[15:8]	Value = 0x00
Byte 3	Information	This field provides extra information about this memory. Bit[7:1] Ignored Bit[0] Write status, _RW 1 writeable (read/write) 0 non-writeable (read-only))
Byte 4	Range base address, _BAS bits[7:0]	Address bits[7:0] of the base memory address for which the card may be configured.
Byte 5	Range base address, _BAS bits[15:8]	Address bits[15:8] of the base memory address for which the card may be configured.
Byte 6	Range base address, _BAS bits[23:16]	Address bits[23:16] of the base memory address for which the card may be configured.
Byte 7	Range base address, _BAS bits[31:24]	Address bits[31:24] of the base memory address for which the card may be configured.
Byte 8	Range length, _LEN bits[7:0]	This field contains Bits[7:0] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
Byte 9	Range length, _LEN bits[15:8]	This field contains Bits[15:8] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
Byte 10	Range length, _LEN bits[23:16]	This field contains Bits[23:16] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.
Byte 11	Range length, _LEN bits[31:24]	This field contains Bits[31:24] of the memory range length. The range length provides the length of the memory range in 1-byte blocks.

Note: Mixing of 24-bit and 32-bit memory descriptors on the same device is not allowed.
See section 17.5.74, "Memory32Fixed (Memory Resource Descriptor)," for a description of the ASL macro that creates a 32-bit Fixed Memory descriptor.
6.4.3.5 Address Space Resource Descriptors
The QWORD, DWORD, WORD, and Extended Address Space Descriptors are general-purpose structures for describing a variety of types of resources. These resources also include support for advanced server architectures (such as multiple root buses), and resource types found on some RISC processors. These descriptors can describe various kinds of resources following table defines the valid combination of each field and how they should be interpreted.
Table 6-38 Valid combination of Address Space Descriptors fields

_LEN	_MIF	_MAF	Definition
0	0	0	Variable size, variable location resource descriptor for _PRS. If _MIF is set, _MIN must be a multiple of (_GRA+1). If _MAF is set, _MAX must be (a multiple of (_GRA+1))-1. OS can pick the resource range that satisfies following conditions: · If _MIF is not set, start address is a multiple of (_GRA+1) and greater or equal to _MIN. Otherwise, start address is _MIN. · If _MAF is not set, end address is (a multiple of (_GRA+1))-1 and less or equal to _MAX. Otherwise, end address is _MAX.
0	0	1
0	1	0
0	1	1	(Illegal combination)
> 0	0	0	Fixed size, variable location resource descriptor for _PRS. _LEN must be a multiple of (_GRA+1). OS can pick the resource range that satisfies following conditions: · Start address is a multiple of (_GRA+1) and greater or equal to _MIN. · End address is (start address+_LEN-1) and less or equal to _MAX.
> 0	0	1	(Illegal combination)
> 0	1	0	(Illegal combination)
> 0	1	1	Fixed size, fixed location resource descriptor. _GRA must be 0 and _LEN must be (_MAX - _MIN +1).

6.4.3.5.1 QWord Address Space Descriptor
Type 1, Large Item Name 0xA
The QWORD address space descriptor is used to report resource usage in a 64-bit address space (like memory and I/O).
Table 6-39 QWORD Address Space Descriptor Definition

Offset	Field Name	Definition
Byte 0	QWORD Address Space Descriptor	Value = 0x8A (10001010B) – Type = 1, Large item name = 0x0A
Byte 1	Length, bits[7:0]	Variable length, minimum value = 0x2B (43)
Byte 2	Length, bits[15:8]	Variable length, minimum value = 0x00
Byte 3	Resource Type	Indicates which type of resource this descriptor describes. Defined values are: 0 Memory range 1 I/O range 2 Bus number range 3–191 Reserved 192-255 Hardware Vendor Defined
Byte 4	General Flags	Flags that are common to all resource types: Bits[7:4] Reserved (must be 0) Bit[3] Max Address Fixed, _MAF: 1 The specified maximum address is fixed 0 The specified maximum address is not fixed and can be changed Bit[2] Min Address Fixed,_MIF: 1 The specified minimum address is fixed 0 The specified minimum address is not fixed and can be changed Bit[1] Decode Type, _DEC: 1 This bridge subtractively decodes this address (top level bridges only) 0 This bridge positively decodes this address Bit[0] Consumer/Producer: 1–This device consumes this resource 0–This device produces and consumes this resource
Byte 5	Type Specific Flags	Flags that are specific to each resource type. The meaning of the flags in this field depends on the value of the Resource Type field (see above).
Byte 6	Address space granularity, _GRA bits[7:0]	A set bit in this mask means that this bit is decoded. All bits less significant than the most significant set bit must be set. That is, the value of the full Address Space Granularity field (all 64 bits) must be a number (2ⁿ-1).
Byte 7	Address space granularity, _GRA bits[15:8]
Byte 8	Address space granularity, _GRA bits[23:16]
Byte 9	Address space granularity, _GRA bits[31:24]
Byte 10	Address space granularity, _GRA bits[39:32]
Byte 11	Address space granularity, _GRA bits[47:40]
Byte 12	Address space granularity, _GRA bits[55:48]
Byte 13	Address space granularity, _GRA bits[63:56]
Byte 14	Address range minimum, _MIN bits[7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 15	Address range minimum, _MIN bits[15:8]
Byte 16	Address range minimum, _MIN bits[23:16]
Byte 17	Address range minimum, _MIN bits[31:24]
Byte 18	Address range minimum, _MIN bits[39:32]
Byte 19	Address range minimum, _MIN bits[47:40]
Byte 20	Address range minimum, _MIN bits[55:48]
Byte 21	Address range minimum, _MIN bits[63:56]
Byte 22	Address range maximum, _MAX bits[7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 23	Address range maximum, _MAX bits[15:8]
Byte 24	Address range maximum, _MAX bits[23:16]
Byte 25	Address range maximum, _MAX bits[31:24]
Byte 26	Address range maximum, _MAX bits[39:32]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 27	Address range maximum, _MAX bits[47:40]
Byte 28	Address range maximum, _MAX bits[55:48]
Byte 29	Address range maximum, _MAX bits[63:56]
Byte 30	Address Translation offset, _TRA bits[7:0]	For bridges that translate addresses across the bridge, this is the offset that must be added to the address on the secondary side to obtain the address on the primary side. Non-bridge devices must list 0 for all Address Translation offset bits.
Byte 31	Address Translation offset, _TRA bits[15:8]
Byte 32	Address Translation offset, _TRA bits[23:16]
Byte 33	Address Translation offset, _TRA bits[31:24]
Byte 34	Address Translation offset, _TRA bits[39:32]
Byte 35	Address Translation offset, _TRA bits[47:40]
Byte 36	Address Translation offset, _TRA bits[55:48]
Byte 37	Address Translation offset, _TRA bits[63:56]
Byte 38	Address length, _LEN bits[7:0]
Byte 39	Address length, _LEN, bits[15:8]
Byte 40	Address length, _LEN bits[23:16]
Byte 41	Address length, _LEN bits[31:24]
Byte 42	Address length, _LEN bits[39:32]
Byte 43	Address length, _LEN bits[47:40]
Byte 44	Address length, _LEN bits[55:48]
Byte 45	Address length, _LEN bits[63:56]
Byte 46	Resource Source Index	(Optional) Only present if Resource Source (below) is present. This field gives an index to the specific resource descriptor that this device consumes from in the current resource template for the device object pointed to in Resource Source.
String	Resource Source	(Optional) If present, the device that uses this descriptor consumes its resources from the resources produced by the named device object. If not present, the device consumes its resources out of a global pool. If not present, the device consumes this resource from its hierarchical parent.

See QWordIO (page 218), QWordMemory (page 218) and ASL_QWordAddressSpace for a description of the ASL macros that creates a QWORD Address Space descriptor.
6.4.3.5.2 DWord Address Space Descriptor
Type 1, Large Item Name 0x7
The DWORD address space descriptor is used to report resource usage in a 32-bit address space (like memory and I/O).
Table 6-40 DWORD Address Space Descriptor Definition

Offset	Field Name	Definition
Byte 0	DWORD Address Space Descriptor	Value = 0x87 (10000111B) – Type = 1, Large item name = 0x07
Byte 1	Length, bits[7:0]	Variable: Value = 23 (minimum)
Byte 2	Length, bits[15:8]	Variable: Value = 0 (minimum)
Byte 3	Resource Type	Indicates which type of resource this descriptor describes. Defined values are: 0 Memory range 1 I/O range 2 Bus number range 3–191 Reserved 192-255 Hardware Vendor Defined
Byte 4	General Flags	Flags that are common to all resource types: Bits[7:4] Reserved (must be 0) Bit[3] Max Address Fixed, _MAF: 1 The specified maximum address is fixed 0 The specified maximum address is not fixed and can be changed Bit[2] Min Address Fixed,_MIF: 1 The specified minimum address is fixed 0 The specified minimum address is not fixed and can be changed Bit[1] Decode Type, _DEC: 1 This bridge subtractively decodes this address (top level bridges only) 0 This bridge positively decodes this address Bit[0] Consumer/Producer: 1–This device consumes this resource 0–This device produces and consumes this resource
Byte 5	Type Specific Flags	Flags that are specific to each resource type. The meaning of the flags in this field depends on the value of the Resource Type field (see above).
Byte 6	Address space granularity, _GRA bits[7:0]	A set bit in this mask means that this bit is decoded. All bits less significant than the most significant set bit must be set. (in other words, the value of the full Address Space Granularity field (all 32 bits) must be a number (2ⁿ-1).
Byte 7	Address space granularity, _GRA bits[15:8]
Byte 8	Address space granularity, _GRA bits [23:16]
Byte 9	Address space granularity, _GRA bits [31:24]
Byte 10	Address range minimum, _MIN bits [7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 11	Address range minimum, _MIN bits [15:8]
Byte 12	Address range minimum, _MIN bits [23:16]
Byte 13	Address range minimum, _MIN bits [31:24]
Byte 14	Address range maximum, _MAX bits [7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 15	Address range maximum, _MAX bits [15:8]
Byte 16	Address range maximum, _MAX bits [23:16]
Byte 17	Address range maximum, _MAX bits [31:24]
Byte 18	Address Translation offset, _TRAbits [7:0]	For bridges that translate addresses across the bridge, this is the offset that must be added to the address on the secondary side to obtain the address on the primary side. Non-bridge devices must list 0 for all Address Translation offset bits.
Byte 19	Address Translation offset, _TRA bits [15:8]
Byte 20	Address Translation offset, _TRA bits [23:16]
Byte 21	Address Translation offset, _TRA bits [31:24]
Byte 22	Address Length, _LEN, bits [7:0]
Byte 23	Address Length, _LEN, bits [15:8]
Byte 24	Address Length, _LEN, bits [23:16]
Byte 25	Address Length, _LEN, bits [31:24]
Byte 26	Resource Source Index	(Optional) Only present if Resource Source (below) is present. This field gives an index to the specific resource descriptor that this device consumes from in the current resource template for the device object pointed to in Resource Source.
String	Resource Source	(Optional) If present, the device that uses this descriptor consumes its resources from the resources produced by the named device object. If not present, the device consumes its resources out of a global pool. If not present, the device consumes this resource from its hierarchical parent.

See DWordIO (page 218), DWordMemory (page 218) and ASL_DWordAddressSpace for a description of the ASL macro that creates a DWORD Address Space descriptor
6.4.3.5.3 Word Address Space Descriptor
Type 1, Large Item Name 0x8
The WORD address space descriptor is used to report resource usage in a 16-bit address space (like memory and I/O).
Note: This descriptor is exactly the same as the DWORD descriptor specified in Table 6-27;the only difference is that the address fields are 16 bits wide rather than 32 bits wide.
Table 6-41 WORD Address Space Descriptor Definition

Offset	Field Name	Definition
Byte 0	WORD Address Space Descriptor	Value = 0x88 (10001000B) – Type = 1, Large item name = 0x08
Byte 1	Length, bits[7:0]	Variable length, minimum v alue = 0x0D (13)
Byte 2	Length, bits[15:8]	Variable length, minimum v alue = 0x00
Byte 3	Resource Type	Indicates which type of resource this descriptor describes. Defined values are: 0 Memory range 1 I/O range 2 Bus number range 3–191 Reserved 192-255 Hardware Vendor Defined
Byte 4	General Flags	Flags that are common to all resource types: Bits[7:4] Reserved (must be 0) Bit[3] Max Address Fixed, _MAF: 1 The specified maximum address is fixed 0 The specified maximum address is not fixed and can be changed Bit[2] Min Address Fixed,_MIF: 1 The specified minimum address is fixed 0 The specified minimum address is not fixed and can be changed Bit[1] Decode Type, _DEC: 1 This bridge subtractively decodes this address (top level bridges only) 0 This bridge positively decodes this address Bit[0] Consumer/Producer: 1–This device consumes this resource 0–This device produces and consumes this resource
Byte 5	Type Specific Flags	Flags that are specific to each resource type. The meaning of the flags in this field depends on the value of the Resource Type field (see above).
Byte 6	Address space granularity, _GRA bits[7:0]	A set bit in this mask means that this bit is decoded. All bits less significant than the most significant set bit must be set. (In other words, the value of the full Address Space Granularity field (all 16 bits) must be a number (2ⁿ-1).
Byte 7	Address space granularity, _GRA bits[15:8]
Byte 8	Address range minimum, _MIN, bits [7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 9	Address range minimum, _MIN, bits [15:8]
Byte 10	Address range maximum, _MAX, bits [7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 11	Address range maximum, _MAX, bits [15:8]
Byte 12	Address Translation offset, _TRA, bits [7:0]	For bridges that translate addresses across the bridge, this is the offset that must be added to the address on the secondary side to obtain the address on the primary side. Non-bridge devices must list 0 for all Address Translation offset bits.
Byte 13	Address Translation offset, _TRA, bits [15:8]
Byte 14	Address Length, _LEN, bits [7:0]
Byte 15	Address Length, _LEN, bits [15:8]
Byte 16	Resource Source Index	(Optional) Only present if Resource Source (below) is present. This field gives an index to the specific resource descriptor that this device consumes from in the current resource template for the device object pointed to in Resource Source.
String	Resource Source	(Optional) If present, the device that uses this descriptor consumes its resources from the resources produced by the named device object. If not present, the device consumes its resources out of a global pool. If not present, the device consumes this resource from its hierarchical parent.

See WordIO (page 218), WordBusNumber (page 218) and ASL_WordAddressSpace for a description of the ASL macros that create a Word address descriptor.
6.4.3.5.4 Extended Address Space Descriptor
Type 1, Large Item Name 0xB
The Extended Address Space descriptor is used to report resource usage in the address space (like memory and I/O).
Table 6-42 Extended Address Space Descriptor Definition

Offset	Field Name	Definition
Byte 0	Extended Address Space Descriptor	Value = 0x8B (10001011B) – Type = 1, Large item name = 0x0B
Byte 1	Length, bits[7:0]	Value = 0x35 (53)
Byte 2	Length, bits[15:8]	Value = 0x00
Byte 3	Resource Type	Indicates which type of resource this descriptor describes. Defined values are: 0 Memory range 1 I/O range 2 Bus number range 3–191 Reserved 192-255 Hardware Vendor Defined
Byte 4	General Flags	Flags that are common to all resource types: Bits[7:4] Reserved (must be 0) Bit[3] Max Address Fixed, _MAF: 1 The specified maximum address is fixed 0 The specified maximum address is not fixed and can be changed Bit[2] Min Address Fixed,_MIF: 1 The specified minimum address is fixed 0 The specified minimum address is not fixed and can be changed Bit[1] Decode Type, _DEC: 1 This bridge subtractively decodes this address (top level bridges only) 0 This bridge positively decodes this address Bit[0] Consumer/Producer: 1–This device consumes this resource 0–This device produces and consumes this resource
Byte 5	Type Specific Flags	Flags that are specific to each resource type. The meaning of the flags in this field depends on the value of the Resource Type field (see above). For the Memory Resource Type, the definition is defined in section 6.4.3.5.5. For other Resource Types, refer to the existing definitions for the Address Space Descriptors.
Byte 6	Revision ID	Indicates the revision of the Extended Address Space descriptor. For ACPI 3.0, this value is 1.
Byte 7	Reserved	0

Table 6-42 Extended Address Space Descriptor Definition (continued)

Offset	Field Name	Definition
Byte 8	Address space granularity, _GRA bits[7:0]	A set bit in this mask means that this bit is decoded bits less significant than the most significant set bit must be set. That is, the value of the full Address Space Granularity field (all 64 bits) must be a number (2ⁿ-1).
Byte 9	Address space granularity, _GRA bits[15:8]
Byte 10	Address space granularity, _GRA bits[23:16]
Byte 11	Address space granularity, _GRA bits[31:24]
Byte 12	Address space granularity, _GRA bits[39:32]
Byte 13	Address space granularity, _GRA bits[47:40]
Byte 14	Address space granularity, _GRA bits[55:48]
Byte 15	Address space granularity, _GRA bits[63:56]
Byte 16	Address range minimum, _MIN bits[7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 17	Address range minimum, _MIN bits[15:8]
Byte 18	Address range minimum, _MIN bits[23:16]
Byte 19	Address range minimum, _MIN bits[31:24]
Byte 20	Address range minimum, _MIN bits[39:32]
Byte 21	Address range minimum, _MIN bits[47:40]

Table 6-42 Extended Address Space Descriptor Definition (continued)

Offset	Field Name	Definition
Byte 22	Address range minimum, _MIN bits[55:48]
Byte 23	Address range minimum, _MIN bits[63:56]
Byte 24	Address range maximum, _MAX bits[7:0]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 25	Address range maximum, _MAX bits[15:8]
Byte 26	Address range maximum, _MAX bits[23:16]
Byte 27	Address range maximum, _MAX bits[31:24]
Byte 28	Address range maximum, _MAX bits[39:32]	For bridges that translate addresses, this is the address space on the secondary side of the bridge.
Byte 29	Address range maximum, _MAX bits[47:40]
Byte 30	Address range maximum, _MAX bits[55:48]
Byte 31	Address range maximum, _MAX bits[63:56]
Byte 32	Address Translation offset, _TRA bits[7:0]	For bridges that translate addresses across the bridge, this is the offset that must be added to the address on the secondary side to obtain the address on the primary side. Non-bridge devices must list 0 for all Address Translation offset bits.
Byte 33	Address Translation offset, _TRA bits[15:8]
Byte 34	Address Translation offset, _TRA bits[23:16]
Byte 35	Address Translation offset, _TRA bits[31:24]

Table 6-42 Extended Address Space Descriptor Definition (continued)

Offset	Field Name	Definition
Byte 36	Address Translation offset, _TRA bits[39:32]
Byte 37	Address Translation offset, _TRA bits[47:40]
Byte 38	Address Translation offset, _TRA bits[55:48]
Byte 39	Address Translation offset, _TRA bits[63:56]
Byte 40	Address length, _LEN bits[7:0]
Byte 41	Address length, _LEN, bits[15:8]
Byte 42	Address length, _LEN bits[23:16]
Byte 43	Address length, _LEN bits[31:24]
Byte 44	Address length, _LEN bits[39:32]
Byte 45	Address length, _LEN bits[47:40]
Byte 46	Address length, _LEN bits[55:48]
Byte 47	Address length, _LEN bits[63:56]
Byte 48	Type Specific Attribute, _ATT bits[7:0]	Attributes that are specific to each resource type meaning of the attributes in this field depends on the value of the Resource Type field (see above). For the Memory Resource Type, the definition is defined section <ref>. For other Resource Types, this field is reserved to 0.
Byte 49	Type Specific Attribute, _ATT bits[15:8]
Byte 50	Type Specific Attribute, _ATT bits[23:16]
Byte 51	Type Specific Attribute, _ATT bits[31:24]
Byte 52	Type Specific Attribute, _ATT bits[39:32]
Byte 53	Type Specific Attribute, _ATT bits[47:40]
Byte 54	Type Specific Attribute, _ATT bits[55:48]
Byte 55	Type Specific Attribute, _ATT bits[63:56]

See section 17.5.41, "ExtendedSpace (Extended Address Space Resource Descriptor Macro)," for a description of the ASL macro that creates an Extended Address Space descriptor.

6.4.3.5.4.1 Type Specific Attributes
The meaning of the Type Specific Attributes field of the Extended Address Space Descriptor depends on the value of the Resource Type field in the descriptor. When Resource Type = 0 (memory resource), the Type Specific Attributes field values are defined as follows:

// These attributes can be "ORed" together as needed.

#define ACPI_MEMORY_UC 0x0000000000000001
#define ACPI_MEMORY_WC 0x0000000000000002
#define ACPI_MEMORY_WT 0x0000000000000004
#define ACPI_MEMORY_WB 0x0000000000000008
#define ACPI_MEMORY_UCE 0x0000000000000010
#define ACPI_MEMORY_NV 0x0000000000008000

Bits

Meaning

Bits[7:6]

Reserved (must be 0)

Bit[5]

Memory to I/O Translation, _TTP

1 TypeTranslation: This resource, which is memory on the secondary side of the bridge, is I/O on the primary side of the bridge.

0 TypeStatic: This resource, which is memory on the secondary side of the bridge, is also memory on the primary side of the bridge.

Bits[4:3]

Memory attributes, _MTP. These bits are only defined if this memory resource describes system RAM a definition of the labels described here, see section 15, "System Address Map Interfaces."

     0    AddressRangeMemory
     1    AddressRangeReserved
     2    AddressRangeACPI
     3    AddressRangeNVS

Bits[2:1]

Memory attributes, _MEM

     0    The memory is non-cacheable.
     1    The memory is cacheable.
     2    The memory is cacheable and supports write combining.
     3    The memory is cacheable and prefetchable.

(Notice: OSPM ignores this field in the Extended address space descriptor. Instead it uses the Type Specific Attributes field to determine memory attributes)

Bit[0]

Write status, _RW
     1    This memory range is read-write.
     0    This memory range is read-only.

Table 6-44   I/O Resource Flag (Resource Type = 1) Definitions

Bits	Meaning
Bits[7:6]	Reserved (must be 0)
Bit[5]	Sparse Translation, _TRS. This bit is only meaningful if Bit[4] is set. 1 SparseTranslation: The primary-side memory address of any specific I/O port within the secondary-side range can be found using the following function. address = (((port & 0xFFFc) << 10) \|\| (port & 0xFFF)) + _TRA In the address used to access the I/O port, bits[11:2] must be identical to bits[21:12], this gives four bytes of I/O ports on each 4 KB page. 0 DenseTranslation: The primary-side memory address of any specific I/O port within the secondary-side range can be found using the following function. address = port + _TRA
Bit[4]	I/O to Memory Translation, _TTP 1 TypeTranslation: This resource, which is I/O on the secondary side of the bridge, is memory on the primary side of the bridge. 0 TypeStatic: This resource, which is I/O on the secondary side of the bridge, is also I/O on the primary side of the bridge.
Bit[3:2]	Reserved (must be 0)
Bit[1:0]	_RNG 3 Memory window covers the entire range 2 ISARangesOnly. This flag is for bridges on systems with multiple bridges. Setting this bit means the memory window specified in this descriptor is limited to the ISA I/O addresses that fall within the specified window. The ISA I/O ranges are: n000-n0FF, n400-n4FF, n800-n8FF, nC00-nCFF. This bit can only be set for bridges entirely configured through ACPI namespace. 1 NonISARangesOnly. This flag is for bridges on systems with multiple bridges. Setting this bit means the memory window specified in this descriptor is limited to the non-ISA I/O addresses that fall within the specified window. The non-ISA I/O ranges are: n100-n3FF, n500-n7FF, n900-nBFF, nD00-nFFF. This bit can only be set for bridges entirely configured through ACPI namespace. 0 Reserved

Table 6-45 Bus Number Range Resource Flag (Resource Type = 2) Definitions

Bits	Meaning
Bit[7:0]	Reserved (must be 0)

6.4.3.6 Extended Interrupt Descriptor
Type 1, Large Item Name 0x9
The Extended Interrupt Descriptor is necessary to describe interrupt settings and possibilities for systems that support interrupts above 15.
To specify multiple interrupt numbers, this descriptor allows vendors to list an array of possible interrupt numbers, any one of which can be used.
Table 6-46 Extended Interrupt Descriptor Definition

Offset	Field Name	Definition
Byte 0	Extended Interrupt Descriptor	Value = 0x89 (10001001B) – Type = 1, Large item name = 0x09
Byte 1	Length, bits[7:0]	Variable length, minimum value = 0x06
Byte 2	Length, bits[15:8]	Variable length, minimum value = 0x00
Byte 3	Interrupt Vector Flags	Interrupt Vector Information. Bit[7:4] Reserved (must be 0) Bit[3] Interrupt is shareable, _SHR Bit[2] Interrupt Polarity, _LL 0 Active-High: This interrupt is sampled when the signal is high, or true. 1 Active-Low: This interrupt is sampled when the signal is low, or false. Bit[1] Interrupt Mode, _HE 0 Level-Triggered: Interrupt is triggered in response to the signal being in either a high or low state. 1 Edge-Triggered: This interrupt is triggered in response to a change in signal state, either high to low or low to high. Bit[0] Consumer/Producer: 1–This device consumes this resource 0–This device produces and consumes this resource
Byte 4	Interrupt table length	Indicates the number of interrupt numbers that follow. When this descriptor is returned from _CRS, or when OSPM passes this descriptor to _SRS, this field must be set to 1.
Byte 4n+5	Interrupt Number, _INT bits [7:0]	Interrupt number
Byte 4n+6	Interrupt Number, _INT bits [15:8]
Byte 4n+7	Interrupt Number, _INT bits [23:16]
Byte 4n+8	Interrupt Number, _INT bits [31:24]
�	�	Additional interrupt numbers
Byte x	Resource Source Index	(Optional) Only present if Resource Source (below) is present. This field gives an index to the specific resource descriptor that this device consumes from in the current resource template for the device object pointed to in Resource Source.
String	Resource Source	(Optional) If present, the device that uses this descriptor consumes its resources from the resources produces by the named device object. If not present, the device consumes its resources out of a global pool. If not present, the device consumes this resource from its hierarchical parent.

Note: Low true, level sensitive interrupts may be electrically shared, the process of how this might work is beyond the scope of this specification.
If the OS is running using the 8259 interrupt model, only interrupt number values of 0-15 will be used, and interrupt numbers greater than 15 will be ignored.
See Interrupt (page 218) for a description of the ASL macro that creates an Extended Interrupt descriptor.
6.4.3.7 Generic Register Descriptor
Type 1, Large Item Name 0x2
The generic register descriptor describes the location of a fixed width register within any of the ACPI-defined address spaces.
Table 6-47 Generic Register Descriptor Definition

Offset	Field Name, ASL Field Name	Definition
Byte 0	Generic Register Descriptor	Value = 0x82 (10000010B) Type = 1, Large item name = 0x02
Byte 1	Length, bits[7:0]	Value = 0x0C (12)
Byte 2	Length, bits[15:8]	Value = 0x00
Byte 3	Address Space ID, _ASI	The address space where the data structure or register exists. Defined values are: 0x00 System Memory 0x01 System I/O 0x02 PCI Configuration Space 0x03 >Embedded Controller 0x04 >SMBus 0x7F Functional Fixed Hardware
Byte 4	Register Bit Wid^th, _RBW	Indicates the register width in bits.
Byte 5	Register Bit Offset, _RBO	Indicates the offset to the start of the register in bits from the Register Address.
Byte 6	Address Size, _ASZ	Specifies access size. 0-Undefined (legacy reasons) 1-Byte access 2-Word access 3-Dword access 4-Qword access
Byte 7	Register Address, _ADR bits[7:0]	Register Address
Byte 8	Register Address, _ADR bits[15:8]
Byte 9	Register Address, _ADR bits[23:16]
Byte 10	Register Address, _ADR bits[31:24]
Byte 11	Register Address, _ADR bits[39:32]
Byte 12	Register Address, _ADR bits[47:40]
Byte 13	Register Address, _ADR bits[55:48]
Byte 14	Register Address, _ADR bits[63:56]

See Register (page 218) for a description of the ASL macro that creates a Generic Register resource descriptor.
6.5 Other Objects and Control Methods
Table 6-48 Other Objects and Methods

Object	Description
_INI	Device initialization method that is run shortly after ACPI has been enabled.
_DCK	Indicates that the device is a docking station.
_BDN	Correlates a docking station between ACPI and legacy interfaces.
_REG	Notifies AML code of a change in the availability of an operation region.
_BBN	PCI bus number set up by the BIOS.
_SEG	Indicates a bus segment location.
_GLK	Indicates the Global Lock must be acquired when accessing a device.

6.5.1 _INI (Init)
_INI is a device initialization object that performs device specific initialization. This control method is located under a device object and is run only when OSPM loads a description table. There are restrictions related to when this method is called and governing writing code for this method. The _INI method must only access Operation Regions that have been indicated to available as defined by the _REG method. The _REG method is described in section 6.5.4, "_REG (Region)." This control method is run before _ADR, _CID, _HID, _SUN, and _UID are run.
Before evaluating the _INI object, OSPM evaluates the _STA object for the device. If the _STA object does not exist for the device, the device is assumed to be both present and functional. If the _STA method indicates that the device is present, OSPM will evaluate the _INI for the device (if the _INI method exists) and will examine each of the children of the device for _INI methods. If the _STA method indicates that the device is not present and is not functional, OSPM will not run the _INI and will not examine the children of the device for _INI methods. If the _STA object evaluation indicates that the device is not present but is functional, OSPM will not evaluate the _INI object, but will examine each of the children of the device for _INI objects (see the description of _STA for the explanation of this special case.) If the device becomes present after the table has already been loaded, OSPM will not evaluate the _INI method, nor examine the children for _INI methods.
The OSPM performed _INI object actions based upon the _STA Present and Functional bits are summarized in the table below.
Table 6-49 OSPM _INI Object Actions

_STA Present Bit	_STA Functional Bit	Actions
0	0	Do not run _INI, do not examine device children
0	1	Do not run _INI, examine device children
1	0	Run _INI, examine device children
1	1	Run _INI, examine device children

The _INI control method is generally used to switch devices out of a legacy operating mode. For example, BIOSes often configure CardBus controllers in a legacy mode to support legacy operating systems. Before enumerating the device with an ACPI operating system, the CardBus controllers must be initialized to CardBus mode. For such systems, the vendor can include an _INI control method under the CardBus controller to switch the device into CardBus mode.
In addition to device initialization, OSPM unconditionally evaluates an _INI object under the \_SB namespace, if present, at the beginning of namespace initialization.
6.5.2   _DCK (Dock)
This control method is located in the device object that represents the docking station (that is, the device object with all the _EJx control methods for the docking station) presence of _DCK indicates to the OS that the device is really a docking station.
_DCK also controls the isolation logic on the docking connector. This allows an OS to prepare for docking before the bus is activated and devices appear on the bus.
Arguments:
            Arg0
            1–Dock (that is, remove isolation from connector)
            0–Undock (isolate from connector)
Return Code:
            1 if successful, 0 if failed.
Note: When _DCK is called with 0, OSPM will ignore the return value. The _STA object that follows the _EJx control method will notify whether or not the portable has been ejected.
6.5.3   _BDN (BIOS Dock Name)
_BDN is used to correlate a docking station reported via ACPI and the same docking station reported via legacy interfaces. It is primarily used for upgrading over non-ACPI environments.
_BDN must appear under a device object that represents the dock, that is, the device object with _Ejx methods. This object must return a DWORD that is the EISA-packed DockID returned by the Plug and Play BIOS Function 5 (Get Docking Station Identifier) for a dock.
Note: If the machine does not support PNPBIOS, this object is not required.
6.5.4   _REG (Region)
The OS runs _REG control methods to inform AML code of a change in the availability of an operation region. When an operation region handler is unavailable, AML cannot access data fields in that region. (Operation region writes will be ignored and reads will return indeterminate data.).
Except for the cases shown below, control methods must assume all operation regions inaccessible until the _REG(RegionSpace, 1) method is executed. Once _REG has been executed for a particular operation region, indicating that the operation region handler is ready, a control method can access fields in the operation region. Conversely, control methods must not access fields in operation regions when _REG method execution has not indicated that the operation region handler is ready.

For example, until the Embedded Controller driver is ready, the control methods cannot access the Embedded Controller. Once OSPM has run _REG(EmbeddedControl, 1), the control methods can then access operation regions in Embedded Controller address space. Furthermore, if OSPM executes _REG(EmbeddedControl, 0), control methods must stop accessing operation regions in the Embedded Controller address space.
The exceptions for this rule are:
1.     OSPM must guarantee that the following operation regions must always be accessible:
· PCI_Config operation regions on a PCI root bus containing a _BBN object.
· I/O operation regions.
· Memory operation regions when accessing memory returned by the System Address Map reporting interfaces.
2.     OSPM must make Embedded Controller operation regions, accessed via the Embedded Controllers described in ECDT, available before executing any control method. These operation regions may become inaccessible after OSPM runs _REG(EmbeddedControl, 0).
Place _REG in the same scope as operation region declarations. The OS will run the _REG in a given scope when the operation regions declared in that scope are available for use.
For example:

    Scope(\_SB.PCI0) {
       OperationRegion(OPR1, PCI_Config, ...)
       Method(_REG, 2) {...}        // OSPM executes this when PCIO operation region handler
                                 // status changes
       Device(PCI1) {
           Method(_REG, 2) {...}
           Device(ETH0) {
              OperationRegion(OPR2, PCI_Config, ...)
              Method(_REG,2) {...}
           }

       }
       Device(ISA0) {
           OperationRegion(OPR3, I/O, ...)
           Method(_REG, 2) {...} // OSPM executes this when ISAO operation region handler
                                // status changes

           Device(EC0) {
              Name(_HID, EISAID("PNP0C09"))
              OperationRegion(OPR4, EC, ...)
              Method(_REG, 2) {...} // OSPM executes this when EC operation region
                                    // handler status changes

           }
       }
    }
When the PCI0 operation region handler is ready, OSPM will run the _REG method declared in PCI0 scope to indicate that PCI Config space operation region access is available within the PCI0 scope (in other words, OPR1 access is allowed). When the ISA0 operation handler is ready, OSPM will run the _REG method in the ISA0 scope to indicate that the I/O space operation region access is available within that scope (in other words, OPR3 access is allowed). Finally, when the Embedded Controller operation region handler is ready, OSPM will run the _REG method in the EC0 scope to indicate that EC space operation region access is available within the EC0 scope (in other words, OPR4 access is allowed). It should be noted that PCI Config Space Operation Regions are ready as soon the host controller or bridge controller has been programmed with a bus number. PCI1's _REG method would not be run until the PCI-PCI bridge has been properly configured. At the same time, the OS will also run ETH0's _REG method since its PCI Config Space would be also available. The OS will again run ETH0's _REG method when the ETH0 device is started. Also, when the host controller or bridge controller is turned off or disabled, PCI Config Space Operation Regions for child devices are no longer available. As such, ETH0's _REG method will be run when it is turned off and will again be run when PCI1 is turned off.
Note: The OS only runs _REG methods that appear in the same scope as operation region declarations that use the operation region type that has just been made available. For example, _REG in the EC device would not be run when the PCI bus driver is loaded since the operation regions declared under EC do not use any of the operation region types made available by the PCI driver (namely, config space, I/O, and memory).
Arguments:
            Arg0:    Integer:Operation region space:
0                      SystemMemory
1                      SystemIO
2                      PCI_Config
3                      Embedded Controller
4                      SMBus
5                      CMOS
6                      PCIBARTarget
0x80-0xFF         OEM region space handler
            Arg1:    Integer:1 for connecting the handler, 0 for disconnecting the handler
6.5.5   _BBN (Base Bus Number)
For multi-root PCI platforms, the _BBN object evaluates to the PCI bus number that the BIOS assigns. This is needed to access a PCI_Config operation region for the specific bus. The _BBN object is located under a PCI host bridge and must be unique for every host bridge within a segment since it is the PCI bus number.

6.5.6   _SEG (Segment)
The optional _SEG object is located under a PCI host bridge and evaluates to an integer that describes the PCI Segment Group (see PCI Firmware Specification v3.0). If _SEG does not exist, OSPM assumes that all PCI bus segments are in PCI Segment Group 0.
PCI Segment Group is purely a software concept managed by system firmware and used by OSPM. It is a logical collection of PCI buses (or bus segments). There is no tie to any physical entities. It is a way to logically group the PCI bus segments and PCI Express Hierarchies. _SEG is a level higher than _BBN.
PCI Segment Group supports more than 256 buses in a system by allowing the reuse of the PCI bus numbers. Within each PCI Segment Group, the bus numbers for the PCI buses must be unique. PCI buses in different PCI Segment Group are permitted to have the same bus number.
A PCI Segment Group contains one or more PCI host bridges.
The lower 16 bits of _SEG returned integer is the PCI Segment Group number. Other bits are reserved.
6.5.6.1   Example

Device(ND0) { // this is a node 0
   Name(_HID, "ACPI0004")

   // Returns the "Current Resources"
   Name(_CRS,
      ResourceTemplate() {
          �
      }
   )
    Device(PCI0) {
      Name(_HID, EISAID("PNP0A03"))
      Name(_ADR, 0x00000000)
      Name(_SEG, 0) // The buses below the host bridge belong to PCI segment 0
          �
      Name(_BBN, 0)
      �
   }
   Device(PCI1) {
      �
      Name(_SEG, 0) // The buses below the host bridge belong to PCI segment 0
      �
      Name(_BBN, 16)
      �
   }
   �
}
Device(ND1) { // this is a node 1
   Name(_HID, "ACPI0004")

   // Returns the "Current Resources"
   Name(_CRS,
      ResourceTemplate() {
          �
      }
   )
    Device(PCI0) {
      Name(_HID, EISAID("PNP0A03"))
      Name(_ADR, 0x00000000)
      Name(_SEG, 1) // The buses below the host bridge belong to PCI segment 1
          �
      Name(_BBN, 0)
      �
   }
   Device(PCI1) {
      �
      Name(_SEG, 1) // The buses below the host bridge belong to PCI segment 1
      �
      Name(_BBN, 16)
      �
   }
}
6.5.7   _GLK (Global Lock)
This optional named object is located in a device object. This object returns a value that indicates to any entity that accesses this device (in other words, OSPM or any device driver) whether the Global Lock must be acquired when accessing the device. OS-based device accesses must be performed while in acquisition of the Global Lock when potentially contentious accesses to device resources are performed by non-OS code, such as System Management Mode (SMM)-based code in Intel architecture-based systems.
An example of this device resource contention is a device driver for an SMBus-based device contending with SMM-based code for access to the Embedded Controller, SMB-HC, and SMBus target device. In this case, the device driver must acquire and release the Global Lock when accessing the device to avoid resource contention with SMM-based code that accesses any of the listed resources.
Return Codes:
            1 Global Lock required, 0 Global Lock not required

7   Power and Performance Management
This section specifies the device power management objects and system power management objects. OSPM uses these objects to manage the platform by achieving a desirable balance between performance and energy conservation goals.
Device performance states (Px states) are power consumption and capability states within the active (D0) device power state. Performance states allow OSPM to make tradeoffs between performance and energy conservation. Device performance states have the greatest impact when the implementation is such that the states invoke different device efficiency levels as opposed to a linear scaling of performance and energy consumption. Since performance state transitions occur in the active device states, care must be taken to ensure that performance state transitions do not adversely impact the system.
Device performance state objects, when necessary, are defined on a per device class basis as described in the device class specifications (See Appendix A).
The system state indicator objects are also specified in this section.
7.1   Declaring a Power Resource Object
An ASL PowerResource statement is used to declare a PowerResource object. A Power Resource object refers to a software-controllable power plane, clock plane, or other resource upon which an integrated ACPI power-managed device might rely. Power resource objects can appear wherever is convenient in namespace.
The syntax of a PowerResource statement is:
PowerResource (resourcename, systemlevel, resourceorder) {NamedList}

where the systemlevel parameter is a number and the resourceorder parameter is a numeric constant (a WORD). For a formal definition of the PowerResource statement syntax, see section 17, "ACPI Source Language Reference."
Systemlevel is the lowest power system sleep level OSPM must maintain to keep this power resource on (0 equates to S0, 1 equates to S1, and so on).
Each power-managed ACPI device lists the resources it requires for its supported power levels. OSPM multiplexes this information from all devices and then enables and disables the required Power Resources accordingly. The resourceorder field in the Power Resource object is a unique value per Power Resource, and it provides the system with the order in which Power Resources must be enabled or disabled. Power Resources are enabled from low values to high values and are disabled from high values to low values. The operating software enables or disables all affected Power Resources in any one resourceorder level at a time before moving on to the next ordered level. Putting Power Resources in different order levels provides power sequencing and serialization where required.

A Power Resource can have named objects under its Namespace location. For a description of the ACPI-defined named objects for a Power Resource, see section 7.2, "Device Power Management Objects."
The following block of ASL sample code shows a use of PowerResource.

PowerResource(PIDE, 0, 0) {
    Method(_STA) {
       Return (Xor (GIO.IDEI, One, Zero)) // inverse of isolation
    }
    Method(_ON) {
       Store (One, GIO.IDEP)    // assert power
       Sleep (10)               // wait 10ms
       Store (One, GIO.IDER)    // de-assert reset#
       Stall (10)               // wait 10us
       Store (Zero, GIO.IDEI)       // de-assert isolation
    }
    Method(_OFF) {
       Store (One, GIO.IDEI)    // assert isolation
       Store (Zero, GIO.IDER)       // assert reset#
       Store (Zero, GIO.IDEP)       // de-assert power
    }
}
7.1.1   Defined Child Objects for a Power Resource
Each power resource object is required to have the following control methods to allow basic control of each power resource OSPM changes the state of device objects in the system, the power resources that are needed will also change causing OSPM to turn power resources on and off. To determine the initial power resource settings the _STA method can be used.
Table 7-1   Power Resource Child Objects

Object	Description
_OFF	Set the resource off.
_ON	Set the resource on.
_STA	Object that evaluates to the current on or off state of the Power Resource. 0–OFF, 1–ON

7.1.2 _OFF
This power resource control method puts the power resource into the OFF state. The control method does not complete until the power resource is off. OSPM only turns on or off one resource at a time, so the AML code can obtain the proper timing sequencing by using Stall or Sleep within the ON (or OFF) method to cause the proper sequencing delays between operations on power resources.
Arguments:
None
Result Code:
None

7.1.3   _ON
This power resource control method puts the power resource into the ON state. The control method does not complete until the power resource is on. OSPM only turns on or off one resource at a time, so the AML code can obtain the proper timing sequencing by using Stall or Sleep within the ON (or OFF) method to cause the proper sequencing delays between operations on power resources.
Arguments:
None
Result Code:
None
7.1.4   _STA (Status)
Returns the current ON or OFF status for the power resource.
Arguments:
None
Result Code:
0 indicates the power resource is currently off.
1 indicates the power resource is currently on.
7.2   Device Power Management Objects
For a device that is power-managed using ACPI, a Definition Block contains one or more of the objects found in the table below. Power management of a device is done using two different paradigms:
·      Power Resource control
·      Device-specific control
Power Resources are resources that could be shared amongst multiple devices. The operating software will automatically handle control of these devices by determining which particular Power Resources need to be in the ON state at any given time. This determination is made by considering the state of all devices connected to a Power Resource.
By definition, a device that is OFF does not have any power resource or system power state requirements. Therefore, device objects do not list power resources for the OFF power state.
For OSPM to put the device in the D3 state, the following must occur:
·      All Power Resources no longer referenced by any device in the system must be in the OFF state.
·      If present, the _PS3 control method is executed to set the device into the D3 device state.
The only transition allowed from the D3 device state is to the D0 >device state.
For many devices the Power Resource control is all that is required; however, device objects may include their own device-specific control method.
These two types of power management controls (through Power Resources and through specific devices) can be applied in combination or individually as required.
For systems that do not control device power states through power plane management, but whose devices support multiple D-states, more information is required by the OS to determine the S-state to D-state mapping for the device. The ACPI BIOS can give this information to OSPM by way of the _SxD methods. These methods tell OSPM for S-state "x", the highest D-state supported by the device is "y." OSPM is allowed to pick a lower D-state for a given S-state, but OSPM is not allowed to exceed the given D-state.
Further rules that apply to device power management objects are:
·       >For a given S-state, a device cannot be in a higher D-state than its parent device.
·       >If there exists an ACPI Object to turn on a device (either through _PSx or _PRx objects), then a corresponding object to turn the device off must also be declared and vice versa.
·       >If there exists an ACPI Object that controls power (_PSx or _PRx, where x =0, 1, 2, or 3), then methods to set the device into D0 and D3 device states must be present.
·       >If a mixture of _PSx and _PRx methods is declared for the device, then the device states supported through _PSx methods must be identical to the device states supported through _PRx methods. ACPI system firmware may enable device power state control exclusively through _PSx (or _PRx) method declarations.

When controlling power to devices which must wake the system during a system sleeping state:

·      The device must declare its ability to wake the system by declaring either the _PRW or _PSW object.
·      If _PR0 is present, then OSPM must choose a sleeping state which is less than or equal to the sleeping state specified.
·      After OSPM has called _PTS, it must call the device's _PSW to enable wake.
·      OSPM must transition the device into a D-state which is greater than or equal that specified by the device's _SxD object, but less than or equal to that specified by the device's _SxW object.
·      OSPM may transition the system to the specified sleep state.
Table 7-2   Device Power Management Child Objects

Object	Description
_DSW	Control method that enables or disables the device's wake function for device-only wake.
_PS0	Control method that puts the device in the D0 device state (device fully on).
_PS1	Control method that puts the device in the D1 device state.
_PS2	Control method that puts the device in the D2 device state.
_PS3	Control method that puts the device in the D3 device state (device off).
_PSC	Object that evaluates to the device's current power state.
_PR0	Object that evaluates to the device's power requirements in the D0 device state (device fully on).
_PR1	Object that evaluates to the device's power requirements in the D1 device state. The only devices that supply this level are those that can achieve the defined D1 device state according to the related device class.
_PR2	Object that evaluates to the device's power requirements in the D2 device state. The only devices that supply this level are those that can achieve the defined D2 device state according to the related device class.
_PRW	Object that evaluates to the device's power requirements in order to wake the system from a system sleeping state.
_PSW	Control method that enables or disables the device's wake function.
_IRC	Object that signifies the device has a significant inrush current draw.
_S1D	Highest D-state supported by the device in the S1 state
_S2D	Highest D-state supported by the device in the S2 state
_S3D	Highest D-state supported by the device in the S3 state
_S4D	Highest D-state supported by the device in the S4 state
_S0W	Lowest D-state supported by the device in the S0 state which can wake the device
_S1W	Lowest D-state supported by the device in the S1 state which can wake the system.
_S2W	Lowest D-state supported by the device in the S2 state which can wake the system.
_S3W	Lowest D-state supported by the device in the S3 state which can wake the system.
_S4W	Lowest D-state supported by the device in the S4 state which can wake the system.

7.2.1 _DSW (Device Sleep Wake)
In addition to _PRW, this control method can be used to enable or disable the device's ability to wake a sleeping system. This control method can only access Operation Regions that are either always available while in a system working state or that are available when the Power Resources referenced by the _PRW object are all ON. For example, do not put a power plane control for a bus controller within configuration space located behind the bus. The method should enable the device only for the last system state/device state combination passed in by OSPM. OSPM will only pass in combinations allowed by the _SxD and _SxW objects.

The arguments provided to _DSW indicate the eventual Device State the device will be transitioned to and the eventual system state that the system will be transitioned to. The target system state is allowed to be the system working state (S0). The _DSW method will be run before the device is placed in the designated state and also before the system is placed in the designated system state.
Compatibility Note: The _PSW method is deprecated in ACPI 3.0. The _DSW method should be used instead. OSPM will only use the _PSW method if OSPM does not support _DSW or if the _DSW method is not present.
Arguments:
0– Enable / Disable:         0 to disable the device's wake capabilities.
                                    1 to enable the device's wake capabilities.
1- Target System State     0 to indicate system will be in S0
                                    1 to indicate system will be in S1
                                    �
2-Target Device State      0 to indicate that the device will remain in D0
                                    1 to indicate that the device will be placed in either D0 or D1
                                    2 to indicate that the device will be placed in either D0, D1, or D2
                                    3 to indicate that the device will be placed in either D0, D1, D2, or D3
Result Code:
None
7.2.2   _PS0 (Power State 0)
This Control Method is used to put the specific device into its D0 state. This Control Method can only access Operation Regions that are either always available while in a system working state or that are available when the Power Resources references by the _PR0 >object are all ON.
Arguments:
None
Result Code:
None
7.2.3   _PS1 (Power State 1)
This control method is used to put the specific device into its D1 state. This control method can only access Operation Regions that are either always available while in a system working state or that are available when the Power Resources references by the _PR1 object are all ON.
Arguments:
None
Result Code:
None
7.2.4   _PS2 (Power State 2)
This control method is used to put the specific device into its D2 state. This control method can only access Operation Regions that are either always available while in a system working state or that are available when the Power Resources references by the _PR2 object are all ON.
Arguments:
None
Result Code:
None
7.2.5   _PS3 (Power State 3)
This control method is used to put the specific device into its D3 state. This control method can only access Operation Regions that are always available while in a system working state.
A device in the D3 state must no longer be using its resources (for example, its memory space and I/O ports are available to other devices).
Arguments:
None
Result Code:
None

7.2.6 _PSC (Power State Current)
This control method evaluates to the current device state. This control method is not required if the device state can be inferred by the Power Resource settings. This would be the case when the device does not require a _PS0, _PS1, _PS2, or _PS3 control method.
Arguments:
None
Result Code:
The result codes are shown in Table 7-3.
Table 7-3 _PSC Control Method Result Codes

Result	Device State
0	D0
1	D1
2	D2
3	D3

7.2.7 _PR0 (Power Resources for D0)
This object evaluates to a package of the following definition:
Table 7-4 Power Resource Requirements Package

Element	Object	Description
1	object reference	Reference to required Power Resource #0
N	object reference	Reference to required Power Resource #N

For OSPM to put the device in the D0 device state, the following must occur:
1.    All Power Resources referenced by elements 1 through N must be in the ON state.
2.    All Power Resources no longer referenced by any device in the system must be in the OFF state.
3.    If present, the _PS0 control method is executed to set the device into the D0 device state.
_PR0 must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
7.2.8   _PR1 (Power Resources for D1)
This object evaluates to a package as defined in Table 7-4. For OSPM to put the device in the D1 device state, the following must occur:
1.    All Power Resources referenced by elements 1 through N must be in the ON state.
2.    All Power Resources no longer referenced by any device in the system must be in the OFF state.
3.    If present, the _PS1 control method is executed to set the device into the D1 device state.
_PR1 must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
7.2.9   _PR2 (Power Resources for D2)
This object evaluates to a package as defined in Table 7-4. For OSPM to put the device in the D2 device state, the following must occur:
1.    All Power Resources referenced by elements 1 through N must be in the ON state.
2.    All Power Resources no longer referenced by any device in the system must be in the OFF state.
3.    If present, the _PS2 control method is executed to set the device into the D2 device state.
_PR2 must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
7.2.10   _PRW (Power Resources for Wake)
This object is only required for devices that have the ability to wake the system from a system sleeping state. This object evaluates to a package of the following definition:
Table 7-5   Wake Power Requirements Package

Element	Object Type	Description
0	Numeric or package	If the data type of this package element is numeric, then this _PRW package element is the bit index in the GPEx_EN, in the GPE blocks described in the FADT, of the enable bit that is enabled for the wake event. If the data type of this package element is a package, then this _PRW package element is itself a package containing two elements first is an object reference to the GPE Block device that contains the GPE that will be triggered by the wake event. The second element is numeric and it contains the bit index in the GPEx_EN, in the GPE Block referenced by the first element in the package, of the enable bit that is enabled for the wake event. For example, if this field is a package then it is of the form: Package(){\_SB.PCI0.ISA.GPE, 2}
1	Numeric	The lowest power system sleeping state that can be entered while still providing wake functionality.
2	Object Reference	Reference to required Power Resource #0
N	Object Reference	Reference to required Power Resource #N

For OSPM to have the defined wake capability properly enabled for the device, the following must occur:
1.    All Power Resources referenced by elements 2 through N are put into the ON state.
2.    If present, the _PSW control method is executed to set the device-specific registers to enable the wake functionality of the device.
3.    The D-state being entered must be at least that specified in the _SxD state but no greater than that specified in the _SxW state.

Then, if the system enters a sleeping state OSPM must ensure:
1.    Interrupts are disabled.
2.    The sleeping state being entered must be less than or equal to the power state declared in element 1 of the _PRW object.
3.    The proper general-purpose register bits are enabled.
The system sleeping state specified must be a state that the system supports (in other words, a corresponding \_Sx object must exist in the namespace).

_PRW must return the same data each time it is evaluated. All power resources referenced must exist in the namespace.
7.2.11   _PSW (Power State Wake)
In addition to the _PRWcontrol method, this control method can be used to enable or disable the device's ability to wake a sleeping system. This control method can only access Operation Regions that are either always available while in a system working state or that are available when the Power Resources references by the _PRW object are all ON. For example, do not put a power plane control for a bus controller within configuration space located behind the bus.
Compatibility Note: The _PSW method is deprecated in ACPI 3.0. OSPM must use _DSW if it is present. Otherwise, it may use _PSW.
Arguments:
0– Enable / Disable:                     0 to disable the device's wake capabilities.
                                                1 to enable the device's wake capabilities.
Result Code:
None
7.2.12   _IRC (In Rush Current)
The presence of this object signifies that transitioning the device to its D0 state causes a system-significant in-rush current load general, such operations need to be serialized such that multiple operations are not attempted concurrently. Within ACPI, this type of serialization can be accomplished with the resourceorder parameter of the device's Power Resources; however, this does not serialize ACPI-controlled devices with non-ACPI controlled devices. IRC is used to signify this fact outside of OSPM to OSPM such that OSPM can serialize all devices in the system that have in-rush current serialization requirements. OSPM can only transition one device containing an _IRC object within its device scope to the D0 state at a time. It is important to note that OSPM does not evaluate the _IRC object. It has no defined input arguments nor does it return any value. OSPM derives meaning simply from the existence of the _IRC object.
7.2.13   _S1D (S1 Device State)
This object evaluates to an integer that conveys to OSPM the highest power (lowest number) D-state supported by this device in the S1 system sleeping state. _S1D must return the same integer each time it is evaluated. This value overrides an S-state to D-state mapping OSPM may ascertain from the device's power resource declarations. See Table 7-3 for valid result codes.
If the device can wake the system from the S1 system sleeping state (see _PRW) then the device must support wake in the D-state returned by this object. However, OSPM cannot assume wake from the S1 system sleeping state is supported in any lower D-state unless specified by a corresponding _S1W object. The table below provides a mapping from Desired Actions to Resultant D-state entered based on the values returned from the _S1D, _PRW, and _S1W objects if they exist . (D/C means Don't Care –evaluation is irrelevant, and N/A means Non Applicable – object does not exist).
Table 7-6   S1 Action / Result Table

Desired Action	_S1D	_PRW	_S1W	Resultant D-state
Enter S1	D/C	D/C	D/C	OSPM decides
Enter S1, No Wake	2	D/C	D/C	Enter D2 or D3
Enter S1, Wake	2	1	N/A	Enter D2
Enter S1, Wake	2	1	3	Enter D2 or D3
Enter S1, Wake	N/A	1	2	Enter D0,D1 or D2

7.2.14 _S2D (S2 Device State)
This object evaluates to an integer that conveys to OSPM the highest power (lowest number) D-state supported by this device in the S2 system sleeping state. _S2D must return the same integer each time it is evaluated. This value overrides an S-state to D-state mapping OSPM may ascertain from the device's power resource declarations. See Table 7-3 for valid result codes.

If the device can wake the system from the S2 system sleeping state (see _PRW) then the device must support wake in the D-state returned by this object. However, OSPM cannot assume wake from the S2 system sleeping state is supported in any lower D-state unless specified by a corresponding _S2W object. The table below provides a mapping from Desired Actions to Resultant D-state entered based on the values returned from the _S2D, _PRW, and _S2W objects if they exist . (D/C means Don't Care –evaluation is irrelevant, and N/A means Non Applicable – object does not exist).

Table 7-7 S2 Action / Result Table

Desired Action	_S2D	_PRW	_S2W	Resultant D-state
Enter S2	D/C	D/C	D/C	OSPM decides
Enter S2, No Wake	2	D/C	D/C	Enter D2 or D3
Enter S2, Wake	2	2	N/A	Enter D2
Enter S2, Wake	2	2	3	Enter D2 or D3
Enter S2, Wake	N/A	2	2	Enter D0,D1 or D2

7.2.15 _S3D (S3 Device State)
This object evaluates to an integer that conveys to OSPM the highest power (lowest number) D-state supported by this device in the S3 system sleeping state. _S3D must return the same integer each time it is evaluated. This value overrides an S-state to D-state mapping OSPM may ascertain from the device's power resource declarations. See Table 7-3 for valid result codes.

If the device can wake the system from the S3 system sleeping state (see _PRW) then the device must support wake in the D-state returned by this object. However, OSPM cannot assume wake from the S3 system sleeping state is supported in any lower D-state unless specified by a corresponding _S3W object. The table below provides a mapping from Desired Actions to Resultant D-state entered based on the values returned from the _S3D, _PRW, and _S3W objects if they exist . (D/C means Don't Care –evaluation is irrelevant, and N/A means Non Applicable – object does not exist).
Table 7-8 S3 Action / Result Table

Desired Action	_S3D	_PRW	_S3W	Resultant D-state
Enter S3	N/A	D/C	N/A	OSPM decides
Enter S3, No Wake	2	D/C	D/C	Enter D2 or D3
Enter S3, Wake	2	3	N/A	Enter D2
Enter S3, Wake	2	3	3	Enter D2 or D3
Enter S3, Wake	N/A	3	2	Enter D0, D1 or D2

7.2.16 _S4D (S4 Device State)
This object evaluates to an integer that conveys to OSPM the highest power (lowest number) D-state supported by this device in the S4 system sleeping state. _S4D must return the same integer each time it is evaluated. This value overrides an S-state to D-state mapping OSPM may ascertain from the device's power resource declarations. See Table 7-3 for valid result codes.

If the device can wake the system from the S4 system sleeping state (see _PRW) then the device must support wake in the D-state returned by this object. However, OSPM cannot assume wake from the S4 system sleeping state is supported in any lower D-state unless specified by a corresponding _S4W object. The table below provides a mapping from Desired Actions to Resultant D-state entered based on the values returned from the _S4D, _PRW, and _S4W objects if they exist . (D/C means Don't Care –evaluation is irrelevant, and N/A means Non Applicable – object does not exist).

Table 7-9 S4 Action / Result Table

Desired Action	_S4D	_PRW	_S4W	Resultant D-state
Enter S4	N/A	D/C	N/A	OSPM decides
Enter S4, No Wake	2	D/C	D/C	Enter D2 or D3
Enter S4, Wake	2	4	N/A	Enter D2
Enter S4, Wake	2	4	3	Enter D2 or D3
Enter S4, Wake	N/A	4	2	Enter D0, D1 or D2

7.2.17 _S0W (S0 Device Wake State)

This object evaluates to an integer that conveys to OSPM the lowest power (highest number) D-state supported by this device in the S0 system sleeping state where the device can wake itself. _S0W must return the same integer each time it is evaluated. This value allows OSPM to choose the lowest power D-state and still achieve wake functionality. If object evaluates to zero, then the device cannot wake itself from any lower sleeping state.
7.2.18 _S1W (S1 Device Wake State)

This object evaluates to an integer that conveys to OSPM the lowest power (highest number) D-state supported by this device in the S1 system sleeping state which can wake the system. _S1W must return the same integer each time it is evaluated. This value allows OSPM to choose a lower S-state to D-state mapping than specified by _S1D. This value must always be greater than or equal to _S1D, if _S1D is present.
7.2.19 _S2W (S2 Device Wake State)

This object evaluates to an integer that conveys to OSPM the lowest power (highest number) D-state supported by this device in the S2 system sleeping state which can wake the system. _S2W must return the same integer each time it is evaluated. This value allows OSPM to choose a lower S-state to D-state mapping than specified by _S2D. This value must always be greater than or equal to _S2D, if _S2D is present.
7.2.20 _S3W (S3 Device Wake State)

This object evaluates to an integer that conveys to OSPM the lowest power (highest number) D-state supported by this device in the S3 system sleeping state which can wake the system. _S3W must return the same integer each time it is evaluated. This value allows OSPM to choose a lower S-state to D-state mapping than specified by _S3D. This value must always be greater than or equal to _S3D, if _S3D is present.
7.2.21 _S4W (S4 Device Wake State)

This object evaluates to an integer that conveys to OSPM the lowest power (highest number) D-state supported by this device in the S4 system sleeping state which can wake the system. _S4W must return the same integer each time it is evaluated. This value allows OSPM to choose a lower S-state to D-state mapping than specified by _S4D. This value must always be greater than or equal to _S4D, if _S4D is present.
7.3 OEM-Supplied System-Level Control Methods
An OEM-supplied Definition Block provides some number of controls appropriate for system-level management. These are used by OSPM to integrate to the OEM-provided features. The following table lists the defined OEM system controls that can be provided.
Table 7-10 BIOS-Supplied Control Methods for System-Level Functions

Object	Description
\_BFS	Control method executed immediately following a wake event.
\_PTS	Control method used to notify the platform of impending sleep transition.
\_GTS	Control method executed just prior to setting the sleep enable (SLP_EN) bit.
\_S0	Package that defines system \_S0 state mode.
\_S1	Package that defines system \_S1 state mode.
\_S2	Package that defines system \_S2 state mode.
\_S3	Package that defines system \_S3 state mode.
\_S4	Package that defines system \_S4 state mode.
\_S5	Package that defines system \_S5 state mode.
\_TTS	Control method used to prepare to sleep and run once awakened
\_WAK	Control method run once awakened.

7.3.1   \_BFS (Back From Sleep)
_BFS is an optional control method. If it exists, OSPM must execute the _BFS method immediately following wake from any sleeping state S1, S2, S3, or S4. _BFS allows ACPI system firmware to perform any required system specific functions when returning a system sleep state. OSPM will execute the _BFS control method before performing any other physical I/O or enabling any interrupt servicing upon returning from a sleeping state. A value that indicates the sleeping state from which the system was awoken (in other words, 1=S1, 2=S2, 3=S3, 4=S4) is passed as an argument to the _BFS control method.
The _BFS method must be self-contained (not call other methods). Additionally, _BFS may only access OpRegions that are currently available (see the _REG method for details).
Arguments:
0:     The value of the previous sleeping state (1 for S1, 2 for S2, and so on).
7.3.2   \_PTS (Prepare To Sleep)
The _PTS control method is executed by the OS during the sleep transition process for S1, S2, S3, S4, and for orderly S5 shutdown sleeping state value (For example, 1, 2, 3, 4 or 5 for the S5 soft-off state) is passed to the _PTS control method. This method is called after OSPM has notified native device drivers of the sleep state transition and before the OSPM has had a chance to fully prepare the system for a sleep state transition. Thus, this control method can be executed a relatively long time before actually entering the desired sleeping state. If OSPM aborts the sleep state transition, OSPM should run the _WAK method to indicate this condition to the platform.
The _PTS control method cannot modify the current configuration or power state of any device in the system. For example, _PTS would simply store the sleep type in the embedded controller in sequencing the system into a sleep state when the SLP_EN bit is set.
The platform must not make any assumptions about the state of the machine when _PTS is called. For example, operation region accesses that require devices to be configured and enabled may not succeed, as these devices may be in a non-decoding state due to plug and play or power management operations.
Arguments:
0:          The value of the sleeping state (1 for S1, 2 for S2, and so on).
7.3.3   \_GTS (Going To Sleep)
_GTS is an optional control method. If it exists, OSPM must execute the _GTS control method just prior to setting the sleep enable (SLP_EN) bit in the PM1 control register when entering the S1, S2, S3, and S4 sleeping states and when entering S5 for orderly shutdown. _GTS allows ACPI system firmware to perform any required system specific functions prior to entering a system sleep state. OSPM will set the sleep enable (SLP_EN) bit in the PM1 control register immediately following the execution of the _GTS control method without performing any other physical I/O or allowing any interrupt servicing. The sleeping state value (1, 2, 3, 4, or 5) is passed as an argument to the _GTS control method. The _GTS method must not attempt to directly place the system into a sleeping state. OSPM performs this function by setting the sleep enable bit upon return from _GTS. In the case of entry into the S5 soft off state however, _GTS may indeed perform operations that place the system into the S5 state as OSPM will not regain control.
The _GTS method must be self-contained (not call other methods). Additionally, _GTS may only access OpRegions that are currently available (see the _REG method for details).
Arguments:
0:         The value of the sleeping state (1 for S1, 2 for S2, and so on).
7.3.4   System \_Sx states
All system states supported by the system must provide a package containing the DWORD value of the following format in the static Definition Block. The system states, known as S0–S5, are referenced in the namespace as \_S0–\_S5 and for clarity the short Sx names are used unless specifically referring to the named \_Sx object. For each Sx state, there is a defined system behavior.

Table 7-11 System State Package

Byte Length	Byte Offset	Description
1	0	Value for PM1a_CNT.SLP_TYP register to enter this system state.
1	1	Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any given state, OSPM must write the PM1a_CNT.SLP_TYP register before the PM1b_CNT.SLP_TYP register.
2	2	Reserved

States S1–S4 represent some system sleeping state. The S0 state is the system working state. Transition into the S0 state from some other system state (such as sleeping) is automatic, and, by virtue that instructions are being executed, OSPM assumes the system to be in the S0 state. Transition into any system sleeping state is only accomplished by the operating software directing the hardware to enter the appropriate state, and the operating software can only do this within the requirements defined in the Power Resource and Bus/Device Package objects.
All run-time system state transitions (for example, to and from the S0 state), except S4 and S5, are done similarly such that the code sequence to do this is the following:

/*
* Intel Architecture SetSleepingState example
*/

    ULONG
    SetSystemSleeping (
       IN ULONG NewState
    )
    {
    PROCESSOR_CONTEXT Context;
    ULONG             PowerSeqeunce;
    BOOLEAN               FlushCaches;
    USHORT            SlpTyp;

// Required environment: Executing on the system boot
// processor. All other processors stopped. Interrupts
// disabled. All Power Resources (and devices) are in
// corresponding device state to support NewState.

       // Get h/w attributes for this system state
       FlushCaches   = SleepType[NewState].FlushCache;
       SlpTyp     = SleepType[NewState].SlpTyp & SLP_TYP_MASK;

       _asm {
       lea    eax, OsResumeContext
       push   eax                   ;Build real mode handler the resume
       push   offset sp50          ;context, with eip = sp50
       call   SaveProcessorState

       mov    eax, ResumeVector     ; set firmware's resume vector
       mov    [eax], offset OsRealModeResumeCode

       mov    edx, PM1a_STS         ;Make sure wake status is clear
       mov    ax, WAK_STS              ;(cleared by asserting the bit
       out    dx, ax                ;in the status register)

       mov    edx, PM1b_STS         ;
       out    dx, ax                ;

       and    eax, not SLP_TYP_MASK
       or     eax, SlpTyp              ;set SLP_TYP
       or     ax, SLP_EN            ; set SLP_EN

       cmp    FlushCaches, 0
       jz     short sp10            ; If needed, ensure no dirty data in

       call   FlushProcessorCaches ;the caches while sleeping

sp10: mov    edx, PM1a_SLP_TYP     ;get address for PM1a_SLP_TYP
       out    dx, ax                ;start h/w sequencing
       mov    edx, PM1b_SLP_TYP     ; get address for PM1b_SLP_TYP
       out    dx, ax                ;start h/w sequencing

       mov    edx, PM1a_STS         ; get address for PM1x_STS
       mov    ecx, PM1b_STS

sp20: in     ax, dx                ;wait for WAK status
       xchg   edx, ecx
       test   ax, WAK_STS
       jz     short sp20

sp50:
}
       // Done..
       *ResumeVector = NULL;
       return 0;
       }

7.3.4.1   System \_S0 State (Working)
While the system is in the S0 state, it is in the system working state. The behavior of this state is defined as:
·      The processors are in the C0, C1, C2, or C3 states processor-complex context is maintained and instructions are executed as defined by any of these processor states.
·      Dynamic RAM context is maintained and is read/write by the processors.
·      Devices states are individually managed by the operating software and can be in any device state (D0, D1, D2, or D3).
·      Power Resources are in a state compatible with the current device states.
Transition into the S0 state from some system sleeping state is automatic, and by virtue that instructions are being executed OSPM, assumes the system to be in the S0 state.
7.3.4.2   System \_S1 State (Sleeping with Processor Context Maintained)
While the system is in the S1 sleeping state, its behavior is the following:
·      The processors are not executing instructions processor-complex context is maintained.
·      Dynamic RAM context is maintained.
·      Power Resources are in a state compatible with the system S1 state. All Power Resources that supply a System-Level reference of S0 are in the OFF state.
·      Devices states are compatible with the current Power Resource states. Only devices that solely reference Power Resources that are in the ON state for a given device state can be in that device state. In all other cases, the device is in the D3 (off) state[10].

·      Devices that are enabled to wake the system and that can do so from their current device state can initiate a hardware event that transitions the system state to S0. This transition causes the processor to continue execution where it left off.
To transition into the S1 state, the OSPM must flush all processor caches.
7.3.4.3   System \_S2 State
The S2 sleeping state is logically lower than the S1 state and is assumed to conserve more power behavior of this state is defined as:
·      The processors are not executing instructions processor-complex context is not maintained.
·      Dynamic RAM context is maintained.
·      Power Resources are in a state compatible with the system S2 state. All Power Resources that supply a System-Level reference of S0 or S1 are in the OFF state.
·      Devices states are compatible with the current Power Resource states. Only devices that solely reference Power Resources that are in the ON state for a given device state can be in that device state. In all other cases, the device is in the D3 (off) state.
·      Devices that are enabled to wake the system and that can do so from their current device state can initiate a hardware event that transitions the system state to S0. This transition causes the processor to begin execution at its boot location. The BIOS performs initialization of core functions as needed to exit an S2 state and passes control to the firmware resume vector. See section 15.3.2, "BIOS Initialization of Memory," for more details on BIOS initialization.
Because the processor context can be lost while in the S2 state, the transition to the S2 state requires that the operating software flush all dirty cache to dynamic RAM (DRAM).

7.3.4.4   System \_S3 State
The S3 state is logically lower than the S2 state and is assumed to conserve more power. The behavior of this state is defined as follows:
·      The processors are not executing instructions processor-complex context is not maintained.
·      Dynamic RAM context is maintained.
·      Power Resources are in a state compatible with the system S3 state. All Power Resources that supply a System-Level reference of S0, S1, or S2 are in the OFF state.
·      Devices states are compatible with the current Power Resource states. Only devices that solely reference Power Resources that are in the ON state for a given device state can be in that device state. In all other cases, the device is in the D3 (off) state.
·      Devices that are enabled to wake the system and that can do so from their current device state can initiate a hardware event that transitions the system state to S0. This transition causes the processor to begin execution at its boot location. The BIOS performs initialization of core functions as necessary to exit an S3 state and passes control to the firmware resume vector. See section 15.3.2, "BIOS Initialization of Memory," for more details on BIOS initialization.
From the software viewpoint, this state is functionally the same as the S2 state. The operational difference can be that some Power Resources that could be left ON to be in the S2 state might not be available to the S3 state. As such, additional devices may need to be in a logically lower D0, D1, D2, or D3 state for S3 than S2. Similarly, some device wake events can function in S2 but not S3.
Because the processor context can be lost while in the S3 state, the transition to the S3 state requires that the operating software flush all dirty cache to DRAM.
7.3.4.5   System \_S4 State
While the system is in this state, it is in the system S4 sleeping state. The state is logically lower than the S3 state and is assumed to conserve more power. The behavior of this state is defined as follows:
·      The processors are not executing instructions processor-complex context is not maintained.
·      DRAM context is not maintained.
·      Power Resources are in a state compatible with the system S4 state. All Power Resources that supply a System-Level reference of S0, S1, S2, or S3 are in the OFF state.
·      Devices states are compatible with the current Power Resource states. In other words, all devices are in the D3 state when the system state is S4.
·      Devices that are enabled to wake the system and that can do so from their device state in S4 can initiate a hardware event that transitions the system state to S0. This transition causes the processor to begin execution at its boot location.
After OSPM has executed the _PTS control method and has put the entire system state into main memory, there are two ways that OSPM may handle the next phase of the S4 state transition; saving and restoring main memory. The first way is to use the operating system's drivers to access the disks and file system structures to save a copy of memory to disk and then initiate the hardware S4 sequence by setting the SLP_EN register bit. When the system wakes, the firmware performs a normal boot process and transfers control to the OS via the firmware_waking_vector loader. The OS then restores the system's memory and resumes execution.
The alternate method for entering the S4 state is to utilize the BIOS via the S4BIOS transition. The BIOS uses firmware to save a copy of memory to disk and then initiates the hardware S4 sequence. When the system wakes, the firmware restores memory from disk and wakes OSPM by transferring control to the FACS waking vector.
The S4BIOS transition is optional, but any system that supports this mechanism must support entering the S4 state via the direct OS mechanism. Thus the preferred mechanism for S4 support is the direct OS mechanism as it provides broader platform support. The alternate S4BIOS transition provides a way to achieve S4 support on operating systems that do not have support for the direct method.

7.3.4.6   System \_S5 State (Soft Off)
The S5 state is similar to the S4 state except that OSPM does not save any context. The system is in the soft off state and requires a complete boot when awakened (BIOS and OS). Software uses a different state value to distinguish between this state and the S4 state to allow for initial boot operations within the BIOS to distinguish whether or not the boot is going to wake from a saved memory image. OSPM does not disable wake events before setting the SLP_EN bit when entering the S5 system state. This provides support for remote management initiatives by enabling Remote Start capability. An ACPI-compliant OS must provide an end user accessible mechanism for disabling all wake devices, with the exception of the system power button, from a single point in the user interface.
7.3.5 _SWS (System Wake Source)
This object provides a means for OSPM to definitively determine the source of an event that caused the system to enter the S0 state. General-purpose event and fixed-feature hardware registers containing wake event sources information are insufficient for this purpose as the source event information may not be available after transitions to the S0 state from all other system states (S1-S5). To determine the source event that caused the system to transition to the S0 state, OSPM will evaluate the _SWS object, when it exists, under the \_GPE scope (for all fixed-feature general-purpose events from the GPE Blocks), under the \_SB scope (for fixed-feature hardware events), and within the scope of a GPE Block device (for GPE events from this device). _SWS objects may exist in any or all of these locations as necessary for the platform to determine the source event that caused the system to transition to the S0 state.
To enable OSPM to determine the source of the S0 state transition via the _SWS object, hardware or firmware should detect and save the event that caused the transition so that it can be returned during _SWS object evaluation. The single wake source for the system may be latched in hardware during the transition so that no false wake events can be returned by _SWS implementation that does not use hardware to latch a single wake source for the system and instead uses firmware to save the wake source must do so as quickly as possible after the wakeup event occurs, so that _SWS does not return values that correspond to events that occurred after the sleep-to-wake transition. Such an implementation must also take care to ensure that events that occur subsequent to the wakeup source being saved do not overwrite the original wakeup source. The source event data returned by _SWS must be determined for each transition into the S0 state. The value returned by _SWS must also be persistent during the system's residency in the S0 state as OSPM may evaluate _SWS multiple times. In this case, the platform must return the same source event information for each invocation.
Arguments:
            None
Result Code
      SourceEvent: DWordConst
Where:
SourceEvent is the index of the GPE input that caused the system to transition to the S0 state if OSPM evaluates _SWS under the \_GPE scope.
SourceEvent is the index of the GPE input that caused the system to transition to the S0 state if OSPM evaluates _SWS within the scope of a GPE Block device. In this case the index is relative to the GPE block device, and is not unique system-wide.
SourceEvent is the index in the PM1 Status register that caused the system to transition to the S0 state if OSPM evaluates _SWS under the \_SB scope .
SourceEvent has all bits set (Ones) if the event that caused the system to transition to the S0 state cannot be determined when OSPM evaluates _SWS under any of the three scopes listed above.
After evaluating an _SWS object within the \_GPE scope or within the scope of a GPE block device, OSPM will invoke the _Wxx control method corresponding to the GPE index returned by _SWS if it exists. This allows the platform to further determine source event if the GPE is shared among multiple devices. See Section 5.6.2.2.4 for details.
7.3.6 \_TTS (Transition To State)
The _TTS control method is executed by the OSPM at the beginning of the sleep transition process for S1, S2, S3, S4, and orderly S5 shutdown. OSPM will invoke _TTS before it has notified any native mode device drivers of the sleep state transition. The sleeping state value (For example, 1, 2, 3, 4 or 5 for the S5 soft-off state) is passed to the _TTS control method.
The _TTS control method is also executed by the OSPM at the end of any sleep transition process when the system transitions to S0 from S1, S2, S3, or S4. OSPM will invoke _TTS after it has notified any native mode device drivers of the end of the sleep state transition. The working state value (0) is passed to the _TTS control method.
If OSPM aborts the sleep transition process, OSPM will still run _TTS for an S0 transition to indicate the OSPM has returned to the S0 state. The platform must assume that if OSPM invokes the _TTS control method for an S1, S2, S3, or S4 transition, that OSPM will invoke _TTS control method for an S0 transition before returning to the S0 state.
The platform must not make any assumptions about the state of the machine when _TTS is called. For example, operation region accesses that require devices to be configured and enabled may not succeed, as these devices may be in a non-decoding state due to plug and play or power management operations.
Arguments:
0:         The value of the sleeping state (1 for S1, 2 for S2, and so on)
7.3.7   \_WAK (System Wake)
After the system wakes from a sleeping state, it will invoke the \_WAK method and pass the sleeping state value that has ended. This operation occurs asynchronously with other driver notifications in the system and is not the first action to be taken when the system wakes. The AML code for this control method issues device, thermal, and other notifications to ensure that OSPM checks the state of devices, thermal zones, and so on, that could not be maintained during the system sleeping state. For example, if the system cannot determine whether a device was inserted or removed from a bus while in the S2 state, the _WAK method would issue a devicecheck type of notification for that bus when issued with the sleeping state value of 2 (for more information about types of notifications, see section 5.6.3, "Device Object Notifications"). Notice that a device check notification from the \_SB node will cause OSPM to re-enumerate the entire tree^[11].
Hardware is not obligated to track the state needed to supply the resulting status; however, this method must return status concerning the last sleep operation initiated by OSPM. The result codes can be used to provide additional information to OSPM or user.
Arguments:
0         The value of the sleeping state (1 for S1, 2 for S2, and so on).
Result Code (2 DWORD package):
Status    Bit field of defined conditions that occurred during sleep.
            0x00000000     Wake was signaled and was successful
            0x00000001     Wake was signaled but failed due to lack of power.
            0x00000002     Wake was signaled but failed due to thermal condition.

            Other              Reserved
PSS      If non-zero, the effective S-state the power supply really entered.

This value is used to detect when the targeted S-state was not entered because of too much current being drawn from the power supply. For example, this might occur when some active device's current consumption pushes the system's power requirements over the low power supply mark, thus preventing the lower power mode from being entered as desired.
7.4 OSPM usage of _GTS, _PTS, _TTS, _WAK, and _BFS
OSPM will invoke _GTS, _PTS, _TTS, _WAK, and _BFS in the following order:
1.OSPM decides (through a policy scheme) to place the system into a sleeping state.
2._TTS(Sx) is run, where Sx is the desired sleep state to enter.
3. OSPM notifies all native device drivers of the sleep state transition
4._PTS is run
5.OSPM readies system for the sleep state transition
6._GTS is run
7.OSPM writes the sleep vector and the system enters the specified Sx sleep state.
8.System Wakes up
9._BFS is run
10.OSPM readies system for the return from the sleep state transition
11._WAK is run
12. OSPM notifies all native device drivers of the return from the sleep state transition
13._TTS(0) is run to indicate the return to the S0 state.

Figure 7-1 Working / Sleeping State object evaluation flow

8   Processor Power and Performance State Configuration and Control
This section describes the configuration and control of the processor's power and performance states. The major controls over the processors are:
·       Processor power states: C0, C1, C2, C3, � Cn
·       Processor clock throttling
·       Processor performance states: P0, P1, � Pn
These controls are used in combination by OSPM to achieve the desired balance of the following sometimes conflicting goals:
·       Performance

·       Power consumption and battery life
·       Thermal requirements
·       Noise-level requirements

Because the goals interact with each other, the operating software needs to implement a policy as to when and where tradeoffs between the goals are to be made[12]. For example, the operating software would determine when the audible noise of the fan is undesirable and would trade off that requirement for lower thermal requirements, which can lead to lower processing performance. Each processor configuration and control interface is discussed in the following sections along with how controls interacts with the various goals.
8.1   Processor Power States
ACPI defines the power state of system processors while in the G0 working state [13] as being either active (executing) or sleeping (not executing). Processor power states include are designated C0, C1, C2, C3, �Cn. The C0 power state is an active power state where the CPU executes instructions. The C1 through Cn power states are processor sleeping states where the processor consumes less power and dissipates less heat than leaving the processor in the C0 state. While in a sleeping state, the processor does not execute any instructions. Each processor sleeping state has a latency associated with entering and exiting that corresponds to the power savings general, the longer the entry/exit latency, the greater the power savings when in the state. To conserve power, OSPM places the processor into one of its supported sleeping states when idle. While in the C0 state, ACPI allows the performance of the processor to be altered through a defined "throttling" process and through transitions into multiple performance states (P-states). A diagram of processor power states is provided below.

Figure 8-1 Processor Power States
ACPI defines logic on a per-CPU basis that OSPM uses to transition between the different processor power states. This logic is optional, and is described through the FADT table and processor objects (contained in the hierarchical namespace). The fields and flags within the FADT table describe the symmetrical features of the hardware, and the processor object contains the location for the particular CPU's clock logic (described by the P_BLK register block and _CST objects).
The P_LVL2 and P_LVL3 registers provide optional support for placing the system processors into the C2 or C3 states. The P_LVL2 register is used to sequence the selected processor into the C2 state, and the P_LVL3 register is used to sequence the selected processor into the C3 state. Additional support for the C3 state is provided through the bus master status and arbiter disable bits (BM_STS in the PM1_STS register and ARB_DIS in the PM2_CNT register). System software reads the P_LVL2 or P_LVL3 registers to enter the C2 or C3 power state. The Hardware must put the processor into the proper clock state precisely on the read operation to the appropriate P_LVLx register. The platform may alternatively define interfaces allowing OSPM to enter C-states using the _CST object, which is defined in Section 8.4.2.1, "_CST (C States)".
Processor power state support is symmetric when presented via the FADT and P_BLK interfaces; OSPM assumes all processors in a system support the same power states. If processors have non-symmetric power state support, then the BIOS will choose and use the lowest common power states supported by all the processors in the system through the FADT table example, if the CPU0 processor supports all power states up to and including the C3 state, but the CPU1 processor only supports the C1 power state, then OSPM will only place idle processors into the C1 power state (CPU0 will never be put into the C2 or C3 power states). Notice that the C1 power state must be supported. The C2 and C3 power states are optional (see the PROC_C1 flag in the FADT table description in section 5.2.6, "System Description Table Header").
The following sections describe processor power states in detail.

8.1.1 Processor Power State C0
While the processor is in the C0 power state, it executes instructions. While in the C0 power state, OSPM can generate a policy to run the processor at less than maximum performance. The clock throttling mechanism provides OSPM with the functionality to perform this task in addition to thermal control. The mechanism allows OSPM to program a value into a register that reduces the processor's performance to a percentage of maximum performance.

Figure 8-2 Throttling Example
The FADT contains the duty offset and duty width values. The duty offset value determines the offset within the P_CNT register of the duty value. The duty width value determines the number of bits used by the duty value (which determines the granularity of the throttling logic) performance of the processor by the clock logic can be expressed with the following equation:

Equation 1 Duty Cycle Equation

Nominal performance is defined as "close as possible, but not below the indicated performance level." OSPM will use the duty offset and duty width to determine how to access the duty setting field. OSPM will then program the duty setting based on the thermal condition and desired power of the processor object. OSPM calculates the nominal performance of the processor using the equation expressed in Equation 1. Notice that a dutysetting of zero is reserved.

For example, the clock logic could use the stop grant cycle to emulate a divided processor clock frequency on an IA processor (through the use of the STPCLK# signal). This signal internally stops the processor's clock when asserted LOW. To implement logic that provides eight levels of clock control, the STPCLK# pin could be asserted as follows (to emulate the different frequency settings):

Figure 8-3 Example Control for the STPCLK#
To start the throttling logic OSPM sets the desired duty setting and then sets the THT_EN bit HIGH. To change the duty setting, OSPM will first reset the THT_EN bit LOW, then write another value to the duty setting field while preserving the other unused fields of this register, and then set the THT_EN bit HIGH again.
The example logic model is shown below:

Figure 8-4 ACPI Clock Logic (One per Processor)
Implementation of the ACPI processor power state controls minimally requires the support a single CPU sleeping state (C1). All of the CPU power states occur in the G0/S0 system state; they have no meaning when the system transitions into the sleeping state(S1-S4). ACPI defines the attributes (semantics) of the different CPU states (defines four of them). It is up to the platform implementation to map an appropriate low-power CPU state to the defined ACPI CPU state.
ACPI clock control is supported through the optional processor register block (P_BLK). ACPI requires that there be a unique processor register block for each CPU in the system. Additionally, ACPI requires that the clock logic for multiprocessor systems be symmetrical when using the P_BLK and FADT interfaces; if the P0 processor supports the C1, C2, and C3 states, but P1 only supports the C1 state, then OSPM will limit all processors to enter the C1 state when idle.
The following sections define the different ACPI CPU sleeping states.

8.1.2   Processor Power State C1
All processors must support this power state. This state is supported through a native instruction of the processor (HLT for IA 32-bit processors), and assumes no hardware support is needed from the chipset hardware latency of this state must be low enough that OSPM does not consider the latency aspect of the state when deciding whether to use it. Aside from putting the processor in a power state, this state has no other software-visible effects. In the C1 power state, the processor is able to maintain the context of the system caches.
The hardware can exit this state for any reason, but must always exit this state when an interrupt is to be presented to the processor.
8.1.3   Processor Power State C2
This processor power state is optionally supported by the system. If present, the state offers improved power savings over the C1 state and is entered by using the P_LVL2 command register for the local processor or an alternative mechanism as indicated by the _CST object. The worst-case hardware latency for this state is declared in the FADT and OSPM can use this information to determine when the C1 state should be used instead of the C2 state. Aside from putting the processor in a power state, this state has no other software-visible effects. OSPM assumes the C2 power state has lower power and higher exit latency than the C1 power state.
The C2 power state is an optional ACPI clock state that needs chipset hardware support. This clock logic consists of an interface that can be manipulated to cause the processor complex to precisely transition into a C2 power state. In a C2 power state, the processor is assumed capable of keeping its caches coherent; for example, bus master and multiprocessor activity can take place without corrupting cache context.
The C2 state puts the processor into a low-power state optimized around multiprocessor and bus master systems. OSPM will cause an idle processor complex to enter a C2 state if there are bus masters or Multiple processor activity (which will prevent OSPM from placing the processor complex into the C3 state). The processor complex is able to snoop bus master or multiprocessor CPU accesses to memory while in the C2 state.
The hardware can exit this state for any reason, but must always exit this state whenever an interrupt is to be presented t o the processor.
8.1.4   Processor Power State C3
This processor power state is optionally supported by the system. If present, the state offers improved power savings over the C1 and C2 state and is entered by using the P_LVL3 command register for the local processor or an alternative mechanism as indicated by the _CST object worst-case hardware latency for this state is declared in the FADT, and OSPM can use this information to determine when the C1 or C2 state should be used instead of the C3 state. While in the C3 state, the processor's caches maintain state but the processor is not required to snoop bus master or multiprocessor CPU accesses to memory.
The hardware can exit this state for any reason, but must always exit this state when an interrupt is to be presented to the processor or when BM_RLD is set and a bus master is attempting to gain access to memory.
OSPM is responsible for ensuring that the caches maintain coherency. In a uniprocessor environment, this can be done by using the PM2_CNT.ARB_DIS bus master arbitration disable register to ensure bus master cycles do not occur while in the C3 state. In a multiprocessor environment, the processors' caches can be flushed and invalidated such that no dynamic information remains in the caches before entering the C3 state.

There are two mechanisms for supporting the C3 power state:
·      Having OSPM flush and invalidate the caches prior to entering the C3 state.
·      Providing hardware mechanisms to prevent masters from writing to memory (uniprocessor-only support).
In the first case, OSPM will flush the system caches prior to entering the C3 state. As there is normally much latency associated with flushing processor caches, OSPM is likely to only support this in multiprocessor platforms for idle processors. Flushing of the cache is accomplished through one of the defined ACPI mechanisms (described below in section 8.2, "Flushing Caches").
In uniprocessor-only platforms that provide the needed hardware functionality (defined in this section), OSPM will attempt to place the platform into a mode that will prevent system bus masters from writing into memory while the processor is in the C3 state. This is accomplished by disabling bus masters prior to entering a C3 power state. Upon a bus master requesting an access, the CPU will awaken from the C3 state and re-enable bus master accesses.
OSPM uses the BM_STS bit to determine the power state to enter when considering a transition to or from the C2/C3 power state BM_STS is an optional bit that indicates when bus masters are active. OSPM uses this bit to determine the policy between the C2 and C3 power states: a lot of bus master activity demotes the CPU power state to the C2 (or C1 if C2 is not supported), no bus master activity promotes the CPU power state to the C3 power state. OSPM keeps a running history of the BM_STS bit to determine CPU power state policy.
The last hardware feature used in the C3 power state is the BM_RLD bit. This bit determines if the Cx power state was exited as a result of bus master requests. If set, then the Cx power state was exited upon a request from a bus master. If reset, the power state was not exited upon bus master requests the C3 state, bus master requests need to transition the CPU back to the C0 state (as the system is capable of maintaining cache coherency), but such a transition is not needed for the C2 state. OSPM can optionally set this bit when using a C3 power state, and clear it when using a C1 or C2 power state.
8.1.5   Additional Processor Power States
ACPI introduced optional processor power states beyond C3 starting in ACPI 2.0. These power states, C4� Cn, are conveyed to OSPM through the _CST object defined in section 8.4.2.1, "_CST (C-States)." These additional power states are characterized by equivalent operational semantics to the C1 through C3 power states, as defined in the previous sections, but with different entry/exit latencies and power savings. See section 8.4.2.1, "_CST (C-States)," for more information.
8.2   Flushing Caches
To support the C3 power state without using the ARB_DIS feature, the hardware must provide functionality to flush and invalidate the processors' caches (for an IA processor, this would be the WBINVD instruction). To support the S1, S2 or S3 sleeping states, the hardware must provide functionality to flush the platform caches. Flushing of caches is supported by one of the following mechanisms:
·      Processor instruction to write back and invalidate system caches (WBINVD instruction for IA processors).
·      Processor instruction to write back but not invalidate system caches (WBINVD instruction for IA processors and some chipsets with partial support; that is, they don't invalidate the caches).
The ACPI specification expects all platforms to support the local CPU instruction for flushing system caches (with support in both the CPU and chipset), and provides some limited "best effort" support for systems that don't currently meet this capability. The method used by the platform is indicated through the appropriate FADT fields and flags indicated in this section.
ACPI specifies parameters in the FADT that describe the system's cache capabilities. If the platform properly supports the processor's write back and invalidate instruction (WBINVD for IA processors), then this support is indicated to OSPM by setting the WBINVD flag in the FADT.

If the platform supports neither of the first two flushing options, then OSPM can attempt to manually flush the cache if it meets the following criteria:
·      A cache-enabled sequential read of contiguous physical memory of not more than 2 MB will flush the platform caches.
There are two additional FADT fields needed to support manual flushing of the caches:
·      FLUSH_SIZE, typically twice the size of the largest cache in the system.
·      FLUSH_STRIDE, typically the smallest cache line size in the system.
8.3   Power, Performance, and Throttling State Dependencies
Cost and complexity trade-off considerations have driven into the platform control dependencies between logical processors when entering power, performance, and throttling states. These dependencies exist in various forms in multi-processor, multi-threaded processor, and multi-core processor-based platforms. These dependencies may also be hierarchical example, a multi-processor system consisting of processors containing multiple cores containing multiple threads may have various dependencies as a result of the hardware implementation.
Unless OSPM is aware of the dependency between the logical processors, it might lead to scenarios where one logical processor is implicitly transitioned to a power, performance, or throttling state when it is unwarranted, leading to incorrect / non-optimal system behavior. Given knowledge of the dependencies, OSPM can coordinate the transitions between logical processors, choosing to initiate the transition when doing so does not lead to incorrect or non-optimal system behavior. This OSPM coordination is referred to as Software (SW) Coordination. Alternately, it might be possible for the underlying hardware to coordinate the state transition requests on multiple logical processors, causing the processors to transition to the target state when the transition is guaranteed to not lead to incorrect or non-optimal system behavior. This scenario is referred to as Hardware (HW) coordination. When hardware coordinates transitions, OSPM continues to initiate state transitions as it would if there were no dependencies. However, in this case it is required that hardware provide OSPM with a means to determine actual state residency so that correct / optimal control policy can be realized.
Platforms containing logical processors with cross-processor dependencies in the power, performance, or throttling state control areas use ACPI defined interfaces to group logical processors into what is referred to as a dependency domain. The Coordination Type characteristic for a domain specifies whether OSPM or underlying hardware is responsible for the coordination. When OSPM coordinates, the platform may require that OSPM transition ALL (0xFC) or ANY ONE (0xFD) of the processors belonging to the domain into a particular target state. OSPM may choose at its discretion to perform coordination even though the underlying hardware supports hardware coordination. In this case, OSPM must transition all logical processors in the dependency domain to the particular target state.
There are no dependencies implied between a processor's C-states, P-states or T-states. Hence, for example it is possible to use the same dependency domain number for specifying dependencies between P-states among one set of processors and C-states among another set of processors without any dependencies being implied between the P-State transitions on a processor in the first set and C-state transitions on a processor in the second set.
8.4 Declaring Processors
Each processor in the system must be declared in the ACPI namespace in either the \_SB or \_PR scope but not both. Declaration of processor in the \_PR scope is required for platforms desiring compatibility with ACPI 1.0-based OSPM implementations. Processors are declared either via the ASL Processor statement or the ASL Device statement. A Processor > definition declares a processor object that provides processor configuration information and points to the processor register block (P_BLK). A Device definition for a processor is declared using the ACPI0007 hardware identifier (HID). In this case, processor configuration information is provided exclusively by objects in the processor device's object list.
When the platform uses the APIC interrupt model, OSPM associates processors declared in the namespace with entries in the MADT. Prior to ACPI 3.0, this was accomplished using the processor object's ProcessorID and the ACPI Processor ID fields in MADT entries. UID fields have been added to MADT entries in ACPI 3.0. By expanding processor declaration using Device definitions, UID object values under a processor device can now be used to associate processor devices with entries in the MADT. This removes the previous 256 processor declaration limit.
Processor-specific objects may be included in the processor object's optional object list or declared within the processor device's scope. These objects serve multiple purposes including providing alternative definitions for the registers described by the processor register block (P_BLK) and processor performance state control. Other ACPI-defined device-related objects are also allowed in the processor object's object list or under the processor device's scope (for example, the unique identifier object _UID).
With device-like characteristics attributed to processors, it is implied that a processor device driver will be loaded by OSPM to, at a minimum, process device notifications. OSPM will enumerate processors in the system using the ACPI Namespace, processor-specific native identification instructions, and optionally the _HID method.
OSPM will ignore definitions of ACPI-defined objects in an object list of a processor object declared under the \_PR namespace.
For more information on the declaration of the processor object, see section 17.5.93, "Processor (Declare Processor)." Processor-specific objects are described in the following sections.
8.4.1   _PDC (Processor Driver Capabilities)
This optional object is a method that is used by OSPM to communicate to the platform the level of processor power management support provided by OSPM. This object is a child object of the processor. OSPM evaluates _PDC prior to evaluating any other processor power management objects returning configuration information.
The _PDC object provides OSPM a mechanism to convey to the platform the capabilities supported by OSPM for processor power management. This allows the platform to modify the ACPI namespace objects returning configuration information for processor power management based on the level of support provided by OSPM. Using this method provides a mechanism for OEMs to provide support for new technologies on legacy OSes, while also allowing OSPM to leverage new technologies on platforms capable of supporting them. This method is evaluated once during processor device initialization, and will not be re-evaluated during resume from a sleep state transition. The platform must preserve state information across S1-S3 sleep state transitions.
Syntax
_PDC (PDCBuffer)=> Null
Arguments
PDCBuffer
DWordConst Buffer (RevisionID, Count, CapabilitiesDWORD1 style='font-size:90%'>,�,CapabilitiesDWORDn)

RevisionID
The revision ID of the CapabilitiesDWORD format.

Count
The number of CapabilitiesDWORD style='font-size:90%;font-family:"Courier New"'> values in the buffer.

CapabiltiesDWORD1-n
Capabilities DWords, where each bit defines capabilities and features supported by OSPM for processor configuration and power management as specified by the CPU manufacturer.
The use of _PDC is deprecated in ACPI 3.0 in favor of _OSC. For backwards compatibility, _PDC may be implemented using _OSC as follows:

Method(_PDC,1)
{
    CreateDwordField (Arg0, 0, REVS)
    CreateDwordField (Arg0, 4, SIZE)

    //
    // Local0 = Number of bytes for Arg0
    //
    Store (SizeOf (Arg0), Local0)

    //
    // Local1 = Number of Capabilities bytes in Arg0
    //
    Store (Subtract (Local0, 8), Local1)

    //
    // TEMP = Temporary field holding Capability DWORDs
    //
    CreateField (Arg0, 64, Multiply (Local1, 8), TEMP)

    //
    // Create the Status (STS0) buffer with the first DWORD = 0
    // This is required to return errors defined by _OSC.
    //
    Name (STS0, Buffer () {0x00, 0x00, 0x00, 0x00})

    //
    // Concatenate the _PDC capabilities bytes to the STS0 Buffer
    // and store them in a local variable for calling OSC
    //
    Concatenate (STS0, TEMP, Local2)

    // Note: The UUID passed into _OSC is CPU vendor specific. Consult CPU
    // vendor documentation for UUID and Capabilities Buffer bit definitions
    _OSC (ToUUID("4077A616-290C-47BE-9EBD-D87058713953"), REVS, SIZE, Local2)
}
Section 6.2.9, "_OSC (Operating System Capabilities)", describes the _OSC object, which can be used to convey processor related OSPM capabilities to the platform. Consult CPU vendor specific documentation for the UUID and Capabilities Buffer bit definitions used by _OSC for a specific processor.

8.4.2   Processor Power State Control
ACPI defines two processor power state (C state) control interfaces. These are:
1)     The Processor Register Block's (P_BLK's) P_LVL2 and P_LVL3 registers coupled with FADT P_LVLx_LAT values and
2)     The _CST object in the processor's object list.
P_BLK based C state controls are described in Section 4, "ACPI Hardware Specification" and Section 8.1, "Processor Power States". _CST based C state controls expand the functionality of the P_BLK based controls allowing the number and type of C states to be dynamic and accommodate CPU architecture specific C state entry and exit mechanisms as indicated by registers defined using the Functional Fixed Hardware address space.
8.4.2.1   _CST (C States)
_CST is an optional object that provides an alternative method to declare the supported processor power states (C States). Values provided by the _CST object override P_LVLx values in P_BLK and P_LVLx_LAT values in the FADT. The _CST object allows the number of processor power states to be expanded beyond C1, C2, and C3 to an arbitrary number of power states. The entry semantics for these expanded states, (in other words), the considerations for entering these states, are conveyed to OSPM by the C-state_Type field and correspond to the entry semantics for C1, C2, and C3 as described in sections 8.1.2 through 8.1.4. _CST defines ascending C-states characterized by lower power and higher entry/exit latency.
Syntax
_CST => CSTPackage
Return Value
CSTPackage: Package (Count, CState,�, CState) where:
Count: style='font-size:90%;font-family:"Courier New"'>ByteConst
The number of CState packages included in CSTPackage
CState: Package (Register, Type, style='font-size:80%;font-family:"Courier New";font-style:normal'> Latency, Power)
Where:
Register: RegisterTerm
A register that OSPM reads to place the processor in the corresponding C state.
Type: ByteConst
The C State type (for example, 1=C1, 2=C2, 3=C3). This field conveys the semantics to be used by OSPM when entering/exiting the C state. Zero is not a valid value
Latency: WordConst
The worst-case latency in microseconds to enter and exit the C State. There are no latency restrictions.
Power: DWordConst
The average power consumption in milliwatts of the processor when in the corresponding C State.
The platform must expose a _CST object for either all or none of its processors. If the _CST object exists, OSPM uses the C state information specified in the _CST object in lieu of P_LVL2 and P_LVL3 registers defined in P_BLK and the P_LVLx_LAT values defined in the FADT. Also notice that if the _CST object exists and the _PTC object does not exist, OSPM will use the Processor Control Register defined in P_BLK and the C_State_Register registers in the _CST object.
The platform may change the number or type of C States available for OSPM use dynamically by issuing a Notify events on the processor object with a notification value of 0x81. This will cause OSPM to re-evaluate any _CST object residing under the processor object notified. For example, the platform might notify OSPM that the number of supported C States has changed as a result of an asynchronous AC insertion / removal event.
The platform must specify unique C_State_Register addresses for all entries within a given _CST object.
_CST eliminates the ACPI 1.0 restriction that all processors must have C State parity. With _CST, each processor can have its own characteristics independent of other processors. For example, processor 0 can support C1, C2 and C3, while processor 1 supports only C1.
The fields in the processor structure remain for backward compatibility.
EXAMPLE

Processor (
\_SB.CPU0,    // Processor Name
1,            // ACPI Processor number
0x120,        // PBlk system IO address
6 )           // PBlkLen
{
Name(_CST, Package()
{
4,     // There are four C-states defined here with three semantics
       // The third and fourth C-states defined have the same C3 entry semantics
Package(){ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, 1, 20, 1000},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x161)}, 2, 40, 750},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x162)}, 3, 60, 500},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x163)}, 3, 100, 250}
})
}
Notice in the example above that OSPM should anticipate the possibility of a _CST object providing more than one entry with the same C_State_Type value. In this case OSPM must decide which C_State_Register it will use to enter that C state.
EXAMPLE
This is an example usage of the _CST object using the typical values as defined in ACPI 1.0.

Processor (
\_SB.CPU0,    // Processor Name
1,            // ACPI Processor number
0x120,        // PBLK system IO address
6 )           // PBLK Len
{
Name(_CST, Package()
{
2,         // There are two C-states defined here – C2 and C3
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x124)}, 2, 2, 750},
Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x125)}, 3, 65, 500}
})
}

The platform will issue a Notify(\_SB.CPU0, 0x81) to inform OSPM to re-evaluate this object when the number of available processor power states changes.
8.4.2.2   _CSD (C-State Dependency)
This optional object provides C-state control cross logical processor dependency information to OSPM. The _CSD object evaluates to a packaged list of information that correlates with the C-state information returned by the _CST object. Each packaged list entry identifies the C-state for which the dependency is being specified (as an index into the _CST object list), a dependency domain number for that C-state, the coordination type for that C-state and the number of logical processors belonging to the domain for the particular C-state. It is possible that a particular C-state may belong to multiple domains. That is, it is possible to have multiple entries in the _CSD list with the same CStateIndex value.
Syntax
_CSD => CSDPackage
Return Value
CSDPackage:Package (CStateDep,�, style='font-size:80%;font-family:"Courier New"'>CStateDep)
Where:
CStateDep: Package (NumberOfEntries, Revision, Domain, style='font-size:80%;font-family:"Courier New";font-style:normal'> CoordType, NumProcessors, Index)
Where:
NumberOfEntries:ByteConst
The number of entries in the CStateDep package including this field. Current value is 6.
Revision: style='font-size:90%;font-family:"Courier New"'>ByteConst
The revision number of the CStateDep package format. Current value is 0.
Domain: DWordConst
The dependency domain number to which this C state entry belongs.
CoordType: DWordConst
The type of coordination that exists (hardware) or is required (software) as a result of the underlying hardware dependency. Could be either 0xFC (SW_ALL), 0xFD (SW_ANY) or 0xFE (HW_ALL) indicating whether OSPM is responsible for coordinating the C-state transitions among processors with dependencies (and needs to initiate the transition on all or any processor in the domain) or whether the hardware will perform this coordination.
NumProcessors: DWordConst
The number of processors belonging to the domain for the particular C-state. OSPM will not start performing power state transitions to a particular C-state until this number of processors belonging to the same domain for the particular C-state have been detected and started.
Index: DWordConst
Indicates the index of the C-State entry in the _CST object for which the dependency applies.
Given that the number or type of available C States may change dynamically, ACPI supports Notify events on the processor object, with Notify events of type 0x81 causing OSPM to re-evaluate any _CST objects residing under the particular processor object notified. On receipt of Notify events of type 0x81, OSPM should re-evaluate any present _CSD objects also.
EXAMPLE
This is an example usage of the _CSD structure in a Processor structure in the name space. The example represents a two processor configuration. The C1-type state can be independently entered on each processor. For the C2-type state, there exists dependence between the two processors, such that one processor transitioning to the C2-type state, causes the other processor to transition to the C2-type state. A similar dependence exists for the C3-type state. OSPM will be required to coordinate the C2 and C3 transitions between the two processors. Also OSPM can initiate a transition on either processor to cause both to transition to the common target C-state.

Processor (
\_SB.CPU0,    // Processor Name
1,            // ACPI Processor number
0x120,        // PBlk system IO address
6 )           // PBlkLen
{
Name (_CST, Package()
{
    3,      // There are three C-states defined here with three semantics
    Package(){ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, 1, 20, 1000},
    Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x161)}, 2, 40, 750},
    Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x162)}, 3, 60, 500}
})
Name(_CSD, Package()
{
    Package(){6, 0, 0, 0xFD, 2, 1},     // 6 entries, Revision 0, Domain 0, OSPM Coordinate
                                // Initiate on Any Proc, 2 Procs , Index 1 (C2-type)
    Package(){6, 0, 0, 0xFD, 2, 2}     // 6 entries, Revision 0, Domain 0, OSPM Coordinate
                                // Initiate on Any Proc, 2 Procs, Index 2 (C3-type)
})
}
Processor (
\_SB.CPU1,    // Processor Name
2,            // ACPI Processor number
,             // PBlk system IO address
)             // PBlkLen
{
Name(_CST, Package()
{
    3,      // There are three C-states defined here with three semantics
    Package(){ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, 1, 20, 1000},
    Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x161)}, 2, 40, 750},
    Package(){ResourceTemplate(){Register(SystemIO, 8, 0, 0x162)}, 3, 60, 500}
})
Name(_CSD, Package()
{
    Package(){6, 0, 0, 0xFD, 2, 1},     // 6 entries, Revision 0, Domain 0, OSPM Coordinate
                                // Initiate on any Proc, 2 Procs, Index 1 (C2-type)
    Package(){6, 0, 0, 0xFD, 2, 2}     // 6 entries, Revision 0, Domain 0, OSPM Coordinate
                                // Initiate on any Proc, 2 Procs, Index 2 (C3-type)
})
}
When the platform issues a Notify(\_SB.CPU0, 0x81) to inform OSPM to re-evaluate _CST when the number of available processor power states changes, OSPM should also evaluate _CSD.
8.4.3   Processor Throttling Controls
ACPI defines two processor throttling (T state) control interfaces. These are:
1)     The Processor Register Block's (P_BLK's) P_CNT register and
2)     The combined _PTC, _TSS, and _TPC objects in the processor's object list.
P_BLK based throttling state controls are described in Section 4, "ACPI Hardware Specification" and Section 8.1.1, "Processor Power State C0". Combined _PTC, _TSS, and _TPC based throttling state controls expand the functionality of the P_BLK based control allowing the number of T states to be dynamic and accommodate CPU architecture specific T state control mechanisms as indicated by registers defined using the Functional Fixed Hardware address space. While platform definition of the _PTC, _TSS, and _TPC objects is optional, all three objects must exist under a processor for OSPM to successfully perform processor throttling via these controls.
8.4.3.1   _PTC (Processor Throttling Control)
_PTC is an optional object that defines a processor throttling control interface alternative to the I/O address spaced-based P_BLK throttling control register (P_CNT) described in section 4, "ACPI Hardware Specification". The processor throttling control register mechanism remains as defined in section 8.1.1, " Processor Power State C0."
OSPM performs processor throttling control by writing the Control field value for the target throttling state (T-state), retrieved from the Throttling Supported States object (_TSS), to the Throttling Control Register (THROTTLE_CTRL) defined by the _PTC object. OSPM may select any processor throttling state indicated as available by the value returned by the _TPC control method.
Success or failure of the processor throttling state transition is determined by reading the Throttling Status Register (THROTTLE_STATUS) to determine the processor's current throttling state. If the transition was successful, the value read from THROTTLE_STATUS will match the "Status" field in the _TSS entry that corresponds to the targeted processor throttling state.

The _PTC object contains data in the following format:

Name (_PTC, Package()
{
    ResourceTemplate(){Throttling_Control_Register}, //Generic Register Descriptor
    ResourceTemplate(){Throttling_Status_Register}    //Generic Register Descriptor

}) // End of _PTC

The platform must expose a _PTC object for either all or none of its processors. Notice that if the _PTC object exists, the specified register is used instead of the P_CNT register specified in the Processor term. Also notice that if the _PTC object exists and the _CST object does not exist, OSPM will use the processor control register from the _PTC object and the P_LVLx registers from the P_BLK.
EXAMPLE
This is an example usage of the _PTC object in a Processor object list:

    Processor (
       \_SB.CPU0,    // Processor Name
       1,            // ACPI Processor number
       0x120,        // PBlk system IO address
       6 )           // PBlkLen
    { //Object List

        Name(_PTC, Package ()    // Processor Throttling Control object
       {
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},          // Throttling_CTRL
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}           // Throttling_STATUS
       }) // End of _PTC object
    } // End of Object List

EXAMPLE
This is an example usage of the _PTC object using the values defined in ACPI 1.0. This is an illustrative example to demonstrate the mechanism with well-known values.

    Processor (
       \_SB.CPU0, // Processor Name
       1,         // ACPI Processor number
       0x120,     // PBLK system IO address
       6 )        // PBLK Len
    { //Object List

       Name(_PTC, Package ()    // Processor Throttling Control object –
                         //32 bit wide IO space-based register at the <P_BLK> address
       {
           ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)},     // Throttling_CTRL
           ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)}         // Throttling_STATUS
       }) // End of _PTC object
    } // End of Object List

8.4.3.2 _TSS (Throttling Supported States)
This optional object indicates to OSPM the number of supported processor throttling states that a platform supports. This object evaluates to a packaged list of information about available throttling states including percentage of maximum internal CPU core frequency, maximum power dissipation, control register values needed to transition between throttling states, and status register values that allow OSPM to verify throttling state transition status after any OS-initiated transition change request. The list is sorted in descending order by power dissipation. As a result, the zeroth entry describes the highest performance throttling state (no throttling applied) and the 'nth' entry describes the lowest performance throttling state (maximum throttling applied).

Name (_TSS, Package()
{      // Field Name                   Field Type

    Package ()                              // Throttle State 0 Definition – T0
    {
       FreqPercentageOfMaximum,        // DWordConst
       Power,                           // DWordConst
       TransitionLatency,                  // DWordConst
       Control,                        // DWordConst
       Status                           // DWordConst
    },
    .
    .
    .
    Package ()                             // Throttle State n Definition – Tn
    {
       FreqPercentageOfMaximum,        // DWordConst
       Power,                           // DWordConst
       TransitionLatency,                  // DWordConst
       Control,                        // DWordConst
       Status                           // DWordConst
    }
}) // End of _TSS object
Each throttling state entry contains five data fields as follows:
·      FreqPercentageOfMaximum. Indicates the percent of the core CPU operating frequency that will be available when this throttling state is invoked range for this field is 1-100. This percentage applies independent of the processor's performance state (P-state). That is, this throttling state will invoke the percentage of maximum frequency indicated by this field as applied to the CoreFreq field of the_PSS entry corresponding to the P-state for which the processor is currently resident.
·      Power. Indicates the throttling state's maximum power dissipation (in milliWatts). OSPM ignores this field on platforms the support P-states, which provide power dissipation information via the _PSS object.
·      TransitionLatency. Indicates the worst-case latency in microseconds that the CPU is unavailable during a transition from any throttling state to this throttling state.
·      Control. Indicates the value to be written to the Processor Control Register (THROTTLE_CTRL) in order to initiate a transition to this throttling state.
·      Status. Indicates the value that OSPM will compare to a value read from the Throttle Status Register (THROTTLE_STATUS) to ensure that the transition to the throttling state was successful. OSPM may always place the CPU in the lowest power throttling state, but additional states are only available when indicated by the _TPC control method. A value of zero indicates the transition to the Throttling state is asynchronous, and as such no status value comparison is required.

When providing the _TSS, the platform must supply a _TSS entry whose FreqPercentageOfMaximum field value is 100. This provides a means for OSPM to disable throttling and achieve maximum performance.
8.4.3.3 _TPC (Throttling Present Capabilities)
This optional object is a method that dynamically indicates to OSPM the number of throttling states currently supported by the platform. This method returns a number that indicates the _TSS entry number of the highest power throttling state that OSPM can use at a given time. OSPM may choose the corresponding state entry in the _TSS as indicated by the value returned by the _TPC method or any lower power (higher numbered) state entry in the _TSS.
Arguments:
            None
Returned Value:
            Number of states supported (integer)
                        0 – states 0 .. n^th state available (all states available)
                        1 – state 1 .. n^th state available
                        2 – state 2 .. n^th state available
                        �
                        n – state n available only
In order to support dynamic changes of _TPC object, Notify events on the processor object of type 0x82 will cause OSPM to reevaluate any _TPC object in the processor's object list. This allows AML code to notify OSPM when the number of supported throttling states may have changed as a result of an asynchronous event. OSPM ignores _TPC Notify events on platforms that support P-states unless the platform has limited OSPM's use of P-states to the lowest power P-state. OSPM may choose to disregard any platform conveyed T-state limits when the platform enables OSPM usage of other than the lowest power P-state.
8.4.3.4   _TSD (T-State Dependency)
This optional object provides T-state control cross logical processor dependency information to OSPM. The _TSD object evaluates to a packaged list of information that correlates with the T-state information returned by the _TSS object. Each packaged list entry identifies a dependency domain number for the logical processor's T-states, the coordination type for that T-state and the number of logical processors belonging to the domain.
Syntax
_TSD => TSDPackage
Return Value
TSDPackage: Package (TStateDep,�, TStateDep)
Where:
TStateDep: Package (NumberOfEntries, Revision, Domain, style='font-size:80%;font-family:"Courier New";font-style:normal'> CoordType, NumProcessors)
Where:
NumberOfEntries:ByteConst
The number of entries in the TStateDep package including this field. Current value is 5.
Revision: style='font-size:90%;font-family:"Courier New"'>ByteConst
The revision number of the TStateDep package format. Current value is 0.
Domain: DWordConst
The dependency domain number to which this T-state entry belongs.
CoordType: DWordConst
The type of coordination that exists (hardware) or is required (software) as a result of the underlying hardware dependency. Could be either 0xFC (SW_ALL), 0xFD (SW_ANY) or 0xFE (HW_ALL) indicating whether OSPM is responsible for coordinating the T-state transitions among processors with dependencies (and needs to initiate the transition on all or any processor in the domain) or whether the hardware will perform this coordination.
NumProcessors: DWordConst
The number of processors belonging to the domain for this logical processor's T-states. OSPM will not start performing power state transitions to a particular T-state until this number of processors belonging to the same domain have been detected and started.

EXAMPLE
This is an example usage of the _TSD structure in a Processor structure in the name space. The example represents a two processor configuration with three T-states per processor. For all T-states, there exists dependence between the two processors, such that one processor transitioning to a particular T-state, causes the other processor to transition to the same T-state. OSPM will be required to coordinate the T-state transitions between the two processors and can initiate a transition on either processor to cause both to transition to the common target T-state.

Processor (
       \_SB.CPU0,    // Processor Name
        1,            // ACPI Processor number
        0x120,        // PBlk system IO address
        6)            // PBlkLen
    { //Object List

       Name(_PTC, Package ()    // Processor Throttling Control object –
                         //32 bit wide IO space-based register at the <P_BLK> address
       {
           ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)},     // Throttling_CTRL
           ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)}         // Throttling_STATUS
       }) // End of _PTC object

       Name (_TSS, Package()
       {
           Package() {
              0x64,      // Frequency Percentage (100%, Throttling OFF state)
              0x0,       // Power
              0x0,       // Transition Latency
              0x7,       // Control THT_EN:0 THTL_DTY:111
              0x0,       // Status
           }

           Package() {
              0x58,      // Frequency Percentage (87.5%)
              0x0,       // Power
              0x0,       // Transition Latency
              0xF,       // Control THT_EN:1 THTL_DTY:111
              0x0,       // Status
           }

           Package() {
              0x4B,      // Frequency Percentage (75%)
              0x0,       // Power
              0x0,       // Transition Latency
              0xE,       // Control THT_EN:1 THTL_DTY:110
              0x0,       // Status
           }
       })

        Name (_TSD, Package()
        {
           Package(){5, 0, 0, 0xFD, 2}     // 5 entries, Revision 0, Domain 0, OSPM Coordinate, 2 Procs
       }) // End of _TSD object

       Method (_TPC, 0)      // Throttling Present Capabilities method
       {
           If (\_SB.AC)
           {
               Return(0)     // All Throttle States are available for use.
           }
           Else
           {
               Return(2)     // Throttle States 0 an 1 won't be used.
           }
       } // End of _TPC method
    } // End of processor object list

    Processor (
       \_SB.CPU1,    // Processor Name
       2,            // ACPI Processor number
       ,             // PBlk system IO address
       )             // PBlkLen
    { //Object List

       Name(_PTC, Package ()    // Processor Throttling Control object –
                         //32 bit wide IO space-based register at the <P_BLK> address
       {
           ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)},     // Throttling_CTRL
           ResourceTemplate(){Register(SystemIO, 32, 0, 0x120)}         // Throttling_STATUS
       }) // End of _PTC object

       Name (_TSS, Package()
       {
           Package() {
              0x64,      // Frequency Percentage (100%, Throttling OFF state)
              0x0,       // Power
              0x0,       // Transition Latency
              0x7,       // Control THT_EN:0 THTL_DTY:111
              0x0,       // Status
           }

           Package() {
              0x58,      // Frequency Percentage (87.5%)
              0x0,       // Power
              0x0,       // Transition Latency
              0xF,       // Control THT_EN:1 THTL_DTY:111
              0x0,       // Status
           }`

           Package() {
              0x4B,      // Frequency Percentage (75%)
              0x0,       // Power
              0x0,       // Transition Latency
              0xE,       // Control THT_EN:1 THTL_DTY:110
              0x0,   // Status
           }
       })

        Name (_TSD, Package()
        {
           Package(){5, 0, 0, 0xFD, 2}     // 5 entries, Revision 0, Domain 0, OSPM Coordinate, 2 Procs
       }) // End of _TSD object

        Method (_TPC, 0)      // Throttling Present Capabilities method
       {
           If (\_SB.AC)
           {
               Return(0)     // All Throttle States are available for use.
           }
           Else
           {
               Return(2)     // Throttle States 0 an 1 won't be used.
           }
       } // End of _TPC method
    } // End of processor object list
8.4.4   Processor Performance Control
Processor performance control is implemented through three optional objects whose presence indicates to OSPM that the platform and CPU are capable of supporting multiple performance states. The platform must supply all three objects if processor performance control is implemented. The platform must expose processor performance control objects for either all or none of its processors. The processor performance control objects define the supported processor performance states, allow the processor to be placed in a specific performance state, and report the number of performance states currently available on the system.

In a multiprocessing environment, all CPUs must support the same number of performance states and each processor performance state must have identical performance and power-consumption parameters. Performance objects must be present under each processor object in the system for OSPM to utilize this feature.
Processor performance control objects include the 'PCT'package, '_PSS' package, and the '_PPC' method as detailed below.
8.4.4.1 _PCT (Performance Control)
This optional object declares an interface that allows OSPM to transition the processor into a performance state. OSPM performs processor performance transitions by writing the performance state–specific control value to a Performance Control Register (PERF_CTRL).
OSPM may select a processor performance state as indicated by the performance state value returned by the _PPC method, or any lower power (higher numbered) state. The control value to write is contained in the corresponding _PSS entry's "Control" field.
Success or failure of the processor performance transition is determined by reading a Performance Status Register (PERF_STATUS) to determine the processor's current performance state. If the transition was successful, the value read from PERF_STATUS will match the "Status" field in the _PSS entry that corresponds to the desired processor performance state.
This object evaluates to a package that declares the above-mentioned transition control and status addresses as follows:

Name (_PCT, Package()
{
ResourceTemplate(){Perf_Ctrl_Register}, //Generic Register Descriptor

ResourceTemplate(){Perf_Status_Register} //Generic Register Descriptor
}) // End of _PCT
8.4.4.2 _PSS (Performance Supported States)
This optional object indicates to OSPM the number of supported processor performance states that any given system can support. This object evaluates to a packaged list of information about available performance states including internal CPU core frequency, typical power dissipation, control register values needed to transition between performance states, and status register values that allow OSPM to verify performance transition status after any OS-initiated transition change request. The list is sorted in descending order by typical power dissipation. As a result, the zeroth entry describes the highest performance state and the 'nth' entry describes the lowest performance state.

Name (_PSS, Package()
{      // Field Name                    Field Type

    Package ()                             // Performance State 0 Definition – P0
    {
       CoreFreq,                        // DWordConst
       Power,                           // DWordConst
       TransitionLatency,                  // DWordConst
       BusMasterLatency,               // DWordConst
       Control,                        // DWordConst
       Status                           // DWordConst
    },
    .
    .
    .
    Package ()                             // Performance State n Definition –Pn
    {
       CoreFreq,                        // DWordConst
       Power,                           // DWordConst
       TransitionLatency,                  // DWordConst
       BusMasterLatency,               // DWordConst
       Control,                        // DWordConst
       Status                           // DWordConst
    }
}) // End of _PSS object

Each performance state entry contains six data fields as follows:
·      CoreFreq. Indicates the core CPU operating frequency (in MHz).
·      Power. Indicates the performance state's maximum power dissipation (in milliWatts).
·      TransitionLatency. Indicates the worst-case latency in microseconds that the CPU is unavailable during a transition from any performance state to this performance state.
·      BusMasterLatency. Indicates the worst-case latency in microseconds that Bus Masters are prevented from accessing memory during a transition from any performance state to this performance state.
·      Control. Indicates the value to be written to the Performance Control Register (PERF_CTRL) in order to initiate a transition to the performance state.
·      Status. Indicates the value that OSPM will compare to a value read from the Performance Status Register (PERF_STATUS) to ensure that the transition to the performance state was successful. OSPM may always place the CPU in the lowest power state, but additional states are only available when indicated by the _PPC method.
8.4.4.3   _PPC (Performance Present Capabilities)
This optional object is a method that dynamically indicates to OSPM the number of performance states currently supported by the platform. This method returns a number that indicates the _PSS entry number of the highest performance state that OSPM can use at a given time. OSPM may choose the corresponding state entry in the _PSS as indicated by the value returned by the _PPC method or any lower power (higher numbered) state entry in the _PSS.
Arguments:
            None
Returned Value:
            Number of states supported (integer)
                        0          states 0 .. n^th state available (all states available)
                        1          state 1 .. n^th state available
                        2          state 2 .. n^th state available
                        �
                        n          state n available only
In order to support dynamic changes of _PPC object, Notify events on the processor object. Notify events of type 0x80 will cause OSPM to reevaluate any _PPC objects residing under the particular processor object notified. This allows AML code to notify OSPM when the number of supported states may have changed as a result of an asynchronous event (AC insertion/removal, docked, undocked, and so on).
8.4.4.4   Processor Performance Control Example
EXAMPLE:
This is an example of processor performance control objects in a processor object list.
In this example, a uniprocessor platform that has processor performance capabilities with support for three performance states as follows:
1.    500 MHz (8.2W) supported at any time
2.    600 MHz (14.9W) supported only when AC powered
3.    650 MHz (21.5W) supported only when docked

It takes no more than 500 microseconds to transition from one performance state to any other performance state.
During a performance transition, bus masters are unable to access memory for a maximum of 300 microseconds.
The PERF_CTRL and PERF_STATUS registers are implemented as Functional Fixed Hardware.
The following ASL objects are implemented within the system:
\_SB.DOCK:      Evaluates to 1 if system is docked, zero otherwise.
\_SB.AC:          Evaluates to 1 if AC is connected, zero otherwise.

    Processor (
       \_SB.CPU0,    // Processor Name
       1,            // ACPI Processor number
       0x120,        // PBlk system IO address
       6 )           // PBlkLen
    {
       Name(_PCT, Package ()     // Performance Control object
       {
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},        // PERF_CTRL
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}           // PERF_STATUS
       }) // End of _PCT object

       Name (_PSS, Package()
       {
           Package(){650, 21500, 500, 300, 0x00, 0x08},   // Performance State zero (P0)
           Package(){600, 14900, 500, 300, 0x01, 0x05},   // Performance State one (P1)
           Package(){500, 8200, 500, 300, 0x02, 0x06}    // Performance State two (P2)
       }) // End of _PSS object

       Method (_PPC, 0)      // Performance Present Capabilities method
       {
           If (\_SB.DOCK)
           {
               Return(0)     // All _PSS states available (650, 600, 500).
           }
           If (\_SB.AC)
           {
               Return(1)     // States 1 and 2 available (600, 500).
           }
           Else
           {
               Return(2)     // State 2 available (500)
           }
       } // End of _PPC method
    } // End of processor object list
The platform will issue a Notify(\_SB.CPU0, 0x80) to inform OSPM to re-evaluate this object when the number of available processor performance states changes.
8.4.4.5   _PSD (P-State Dependency)
This optional object provides P-state control cross logical processor dependency information to OSPM. The _PSD object evaluates to a packaged list of information that correlates with the P-state information returned by the _PSS object. Each packaged list entry identifies a dependency domain number for the logical processor's P-states, the coordination type for that P-state and the number of logical processors belonging to the domain.
Syntax
_PSD => PSDPackage
Return Value
PSDPackage: Package (PStateDep,�, PStateDep)
Where:
PStateDep: Package (NumberOfEntries, Revision, Domain, style='font-size:80%;font-family:"Courier New";font-style:normal'> CoordType, NumProcessors)
Where:
NumberOfEntries:ByteConst
The number of entries in the PStateDep package including this field. Current value is 5.
Revision: style='font-size:90%;font-family:"Courier New"'>ByteConst
The revision number of the PStateDep package format. Current value is 0.
Domain: DWordConst
The dependency domain number to which this P-state entry belongs.
CoordType: DWordConst
The type of coordination that exists (hardware) or is required (software) as a result of the underlying hardware dependency. Could be either 0xFC (SW_ALL), 0xFD (SW_ANY) or 0xFE (HW_ALL) indicating whether OSPM is responsible for coordinating the P-state transitions among processors with dependencies (and needs to initiate the transition on all or any processor in the domain) or whether the hardware will perform this coordination.
NumProcessors: DWordConst
The number of processors belonging to the domain for this logical processor's P-states. OSPM will not start performing power state transitions to a particular P-state until this number of processors belonging to the same domain have been detected and started.

EXAMPLE
This is an example usage of the _PSD structure in a Processor structure in the name space. The example represents a two processor configuration with three performance states per processor. For all performance states, there exists dependence between the two processors, such that one processor transitioning to a particular performance state, causes the other processor to transition to the same performance state. OSPM will be required to coordinate the P-state transitions between the two processors and can initiate a transition on either processor to cause both to transition to the common target P-state.

    Processor (
       \_SB.CPU0,    // Processor Name
       1,            // ACPI Processor number
       0x120,        // PBlk system IO address
       6 )           // PBlkLen
    {
       Name(_PCT, Package () // Performance Control object
       {
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},        // PERF_CTRL
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}           // PERF_STATUS
       }) // End of _PCT object

       Name (_PSS, Package()
       {
           Package(){650, 21500, 500, 300, 0x00, 0x08},   // Performance State zero (P0)
           Package(){600, 14900, 500, 300, 0x01, 0x05},   // Performance State one (P1)
           Package(){500, 8200, 500, 300, 0x02, 0x06}    // Performance State two (P2)
       }) // End of _PSS object

       Method (_PPC, 0)      // Performance Present Capabilities method
       {
       } // End of _PPC method

       Name (_PSD, Package()
       {
           Package(){5, 0, 0, 0xFD, 2} // 5 entries, Revision 0), Domain 0, OSPM
                                    // Coordinate, Initiate on any Proc, 2 Procs
       }) // End of _PSD object
    } // End of processor object list

    Processor (
       \_SB.CPU1,    // Processor Name
       2,            // ACPI Processor number
       ,             // PBlk system IO address
       )             // PBlkLen
    {
       Name(_PCT, Package () // Performance Control object
       {
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)},        // PERF_CTRL
           ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}           // PERF_STATUS
       }) // End of _PCT object

       Name (_PSS, Package()
       {
           Package(){650, 21500, 500, 300, 0x00, 0x08},   // Performance State zero (P0)
           Package(){600, 14900, 500, 300, 0x01, 0x05},   // Performance State one (P1)
           Package(){500, 8200, 500, 300, 0x02, 0x06}    // Performance State two (P2)
       }) // End of _PSS object

       Method (_PPC, 0)      // Performance Present Capabilities method
       {
       }   // End of _PPC method

       Name (_PSD, Package()
       {
           Package(){5, 0, 0, 0xFD, 2} // 5 entries, Revision 0, Domain 0, OSPM
                                    // Coordinate, Initiate on any Proc, 2 Procs
       }) // End of _PSD object
    } // End of processor object list

9   ACPI-Devices and Device Specific Objects
This section describes ACPI defined devices and device-specific objects. The system status indicator objects, declared under the \_SI scope in the ACPI Namespace, are also specified in this section.
9.1   \_SI System Indicators
ACPI provides an interface for a variety of simple and icon-style indicators on a system. All indicator controls are in the \_SI portion of the namespace. The following table lists all defined system indicators. (Notice that there are also per-device indicators specified for battery devices).
Table 9-1   System Indicator Control Methods

Object	Description
_SST	System status indicator
_MSG	Messages waiting indicator

9.1.1   _SST (System Status)
This optional object is a control method that OSPM invokes to set the system status indicator as desired.
Arguments:
0                No system state indication. Indicator off.
1                Working
2                Waking
3                Sleeping. Used to indicate system state S1, S2 or S3.
4                Sleeping with context saved to non-volatile storage.
9.1.2   _MSG (Message)
This control method sets the system's message-waiting status indicator.
Arguments:
0             Number of messages waiting
9.1.3 BLT (Battery Level Threshold)
This optional control method is used by OSPM to indicate to the platform the user's preference for various battery level thresholds. This method allows platform battery indicators to be synchronized with OSPM provided battery notification levels. Note that if _BLT is implemented on a multi-battery system, it is required that the power unit for all batteries must be the same. See section 10.2 for more details on battery levels.
Arguments:
Argument 1: DWORD:
0x00000001 –0x7FFFFFFF (in units of mWh or mAh, depending on the Power Units value)

User's preference for battery warning level. If the level specified is less than the design capacity of warning, it may be ignored by the platform so that the platform can ensure a successful wake on low battery.
Argument 2: DWORD:
0x00000001 –0x7FFFFFFF (in units of mWh or mAh, depending on the Power Units value)

User's preference for battery low level. If this level is less than the design capacity of low, it may be ignored by the platform.

Argument 3: DWORD:
0x00000001 –0x7FFFFFFF (in units of mWh or mAh, depending on the Power Units value)

User's preference for battery wake level. If this level is less than the platform's current wake on low battery level, it may be ignored by the platform. If the platform does not support a configurable wake on low battery level, this may be ignored by the platform..

9.2 Control Method Ambient Light Sensor Device
The following section illustrates the operation and definition of the Control Method Ambient Light Sensor (ALS) device.
The ambient light sensor device can optionally support power management objects (e.g. _PS0, _PS3) to allow the OS to manage the device's power consumption.
The Plug and Play ID of an ACPI control method ambient light sensor device is ACPI0008.
Table 9-2: Control Method Ambient Light Sensor Device

Object	Description
_ALI	The current ambient light illuminance reading in lux (lumen per square meter). [Required]
_ALC	The current ambient light color chromacity reading, specified using x and y coordinates per the CIE Yxy color model. [Optional]
_ALT	The current ambient light color temperature reading in degrees Kelvin. [Optional]
_ALR	Returns a set of ambient light illuminance to display brightness mappings that can be used by an OS to calibrate its ambient light policy. [Required]
_ALP	Ambient light sensor polling frequency in tenths of seconds. [Optional]

9.2.1 Overview
This definition provides a standard interface by which the OS may query properties of the ambient light environment the system is currently operating in, as well as the ability to detect meaningful changes in these values when the environment changes. Two ambient light properties are currently supported by this interface: illuminance and color.

Ambient light illuminance readings are obtained via the _ALI method. Illuminance readings indicate the amount of light incident upon (falling on) a specified surface area. Values are specified in lux (lumen per square meter) and give an indication of how "bright" the environment is. For example, an overcast day is roughly 1000 lux, a typical office environment 300-400 lux, and a dimly-lit conference room around 10 lux.

A possible use of ambient light illuminance data by the OS is to automatically adjust the brightness (or luminance) of the display device – e.g. increase display luminance in brightly-lit environments and decrease display luminance in dimly-lit environments. Note that Luminance is a measure of light radiated (reflected, transmitted, or emitted) by a surface, and is typically measured in nits. The _ALR method provides a set of ambient light illuminance to display luminance mappings that can be used by an OS to calibrate its policy for a given platform configuration.

Ambient light color readings are obtained via the _ALT and/or _ALC methods. Two methods are defined to allow varying types/complexities of ambient light sensor hardware to be used. _ALT returns color temperature readings in degrees Kelvin. Color temperature values correlate a light source to a standard black body radiator and give an indication of the type of light source present in a given environment (e.g. daylight, fluorescent, incandescent). ALC returns color chromacity readings per the CIE Yxy color model. Chromacity x and y coordinates provide a more straightforward indication of ambient light color characteristics. Note that the CIE Yxy color model is defined by the International Commission on Illumination (abbreviated as CIE from its French title Commission Internationale de l'Eclairage) and is based on human perception instead of absolute color.

A possible use of ambient light color data by the OS is to automatically adjust the color of displayed images depending on the environment the images are being viewed in. This may be especially important for reflective/transflective displays where the type of ambient light may have a large impact on the colors perceived by the user.
9.2.2   _ALI (Ambient Light Illuminance)
This control method returns the current ambient light illuminance reading in lux (lumen per square meter). Expected values range from ~1 lux for a dark room, ~300 lux for a typical office environment, and 10,000+ lux for daytime outdoor environments – although readings may vary depending on the location of the sensor to the light source. Special values are reserved to indicate out of range conditions (see below).
Arguments:
None
Result Code:
Zero:                       The current reading is below the supported range or sensitivity of the sensor.
Ones:                      The current reading is above the supported range or sensitivity of the sensor.
All other values:        The current ambient light brightness in lux (lumens per square meter).
9.2.3   _ALT (Ambient Light Temperature)
This optional control method returns the current ambient light color temperature reading in degrees Kelvin (�K). Lower color temperatures imply warmer light (emphasis on yellow and red); higher color temperatures imply a colder light (emphasis on blue). This value can be used to gauge various properties of the lighting environment – for example, the type of light source. Expected values range from ~1500�K for candlelight, ~3000�K for a 200-Watt incandescent bulb, and ~5500�K for full sunlight on a summer day – although readings may vary depending on the location of the sensor to the light source. Special values are reserved to indicate out of range conditions (see below).
Arguments:
None
Result Code:
Zero:                       The current reading is below the supported range or sensitivity of the sensor.
Ones:                      The current reading is above the supported range or sensitivity of the sensor.
All other values:        The current ambient light temperature in degrees Kelvin.
9.2.4 _ALC (Ambient Light Color Chromacity)
This optional control method returns the current ambient light color chromacity readings per the CIE Yxy color model. The x and y (chromacity) coordinates are specified using a fixed 10^-4notation due to the lack of floating point values in ACPI. Valid values are within the range 0 (0x0000) through 1 (0x2710). A single 32-bit integer value is used, where the x coordinate is stored in the high word and the y coordinate in the low word. For example, the value 0x0C370CDA would be used to specify the white point for the CIE Standard Illuminant D65 (a standard representation of average daylight) with x = 0.3127 and y = 0.3290. Special values are reserved to indicate out of range conditions (see below).
Arguments:
None
Result Code:
Zero:                       The current reading is below the supported range or sensitivity of the sensor.
Ones:                      The current reading is above the supported range or sensitivity of the sensor.
All other values:        The current ambient light color chromacity x and y coordinate values, per the CIE Yxy color model.
9.2.5   _ALR (Ambient Light Response)
This object evaluates to a package of ambient light illuminance to display luminance mappings that can be used by an OS to calibrate its ambient light policy for a given sensor configuration. The OS can use this information to extrapolate an ALS response curve - noting that these values may be treated differently depending on the OS implementation but should be used in some form to calibrate ALS policy.
The data set is specified as a package of packages, where each tuple (inner package) consists of the pair of integer values of the form:
            {<display luminance adjustment>, <ambient light illuminance>}
Package elements should be listed in monotonically increasing order based upon the ambient light illuminance value (the Y-coordinate on the graph) to simplify parsing by the OS.
Ambient light illuminance values are specified in lux (lumens per square meter). Display luminance (or brightness) adjustment values are specified using relative percentages in order simplify the means by which these adjustments are applied in lieu of changes to the user's display brightness preference. A value of 100 is used to indicate no (0%) display brightness adjustment given the lack of signed data types in ACPI. Values less than 100 indicate a negative adjustment (dimming); values greater than 100 indicate a positive adjustment (brightening). For example, a display brightness adjustment value of 75 would be interpreted as a -25% adjustment, and a value of 110 as a +10% adjustment.

Figure 9-1: A five-point ALS Response Curve
Figure 9-1 illustrates the use of five points to approximate an example response curve, where the dotted line represents an approximation of the desired response (solid curve). Extrapolation of the values between these points is OS-specific – although for the purposes of this example we'll assume a piecewise linear approximation. The ALS response curve (_ALR) would be specified as follows:

    Name(_ALR, Package(5) {
       Package{70, 0},     // Min         ( -30% adjust at 0 lux)
       Package{73, 10},     //            ( -27% adjust at 10 lux)
       Package{85, 80},     //            ( -15% adjust at 80 lux)
       Package{100,300},         // Baseline       ( 0% adjust at 300 lux)
       Package{150,1000}     // Max         (+50% adjust at 1000 lux)
    })

Within this data set exist three points of particular interest: baseline, min, and max. The baseline value represents an ambient light illuminance value (in lux) for the environment where this system is most likely to be used. When the system is operating in this ambient environment the ALS policy will apply no (0%) adjustment to the default display brightness setting. For example, given a system with a 300 lux baseline, operating in a typical office ambient environment (~300 lux), configured with a default display brightness setting of 50% (e.g. 60 nits), the ALS policy would apply no backlight adjustment, resulting in an absolute display brightness setting of 60 nits.
Min and max are used to indicate cutoff points in order to prevent an over-zealous response by the ALS policy and to influence the policy's mode of operation. For example, the min and max points from the figure above would be specified as (70,0) and (150,1000) respectively – where min indicates a maximum negative adjustment of 30% and max represents a maximum positive adjustment of 500%. Using a large display brightness adjustment for max allows an ALS response that approaches a fully-bright display (100% absolute) in very bright ambient environments regardless of the user's display brightness preference. Using a small value for max (e.g. 0% @ 300 lux) would influence the ALS policy to limit the use of this technology solely as a power-saving feature (never brighten the display). Conversely, setting min to a 0% adjustment instructs ALS policy to brighten but never dim.
A minimum of two data points are required in the return package, interpreted as min and max. Note that the baseline style='font-style:normal'>value does not have to be explicitly stated; it can be derived from the response curve. Addition elements can be provided to fine-tune the response between these points. Figure 9-2 illustrates the use of two data points to achieve a response similar to (but simpler than) that described in Figure 9-1.

Figure 9-2: A two-point ALS Response Curve

This example lacks an explicit baseline and includes a min style='font-style:normal'> with an ambient light value above 0 lux. The baseline can easily be extrapolated by ALS Policy (e.g. 0% adjustment at ~300 lux). All ambient light brightness settings below min (20 lux) would be treated in a similar fashion by ALS policy (e.g. -30% adjustment). This two-point response curve would be modeled as:

    Name(_ALR, Package(3) {
       Package{70, 30},     // Min         ( -30% adjust at 30 lux)
       Package{150,1000}     // Max         (+50% adjust at 1000 lux)
    })

This model can be used to convey a wide range of ambient light to display brightness responses. For example, a transflective display – a technology where illumination of the display can be achieved by reflecting available ambient light, but also augmented in dimly-lit environments with a backlight – could be modeled as illustrated in Figure 9-3.

Figure 9-3: Example Response Curve for a Transflective Display

This three-point approximation would result in an ALS response that allows the backlight to increase as the ambient lighting decreases. In this example, no backlight adjustment is needed in bright environments (1000+ lux), maximum backlight may be needed in dim environments (~30 lux), but a lower backlight setting may be used in a very-dark room (~0 lux) – resulting in an elbow around 30 lux. This response would be modeled in _ALR as follows:

    Name(_ALR, Package(3) {
       Package{180, 0}                     ( +80% adjust at 0 lux)
       Package{200, 30},     // Max         (+100% adjust at 30 lux)
       Package{0, 1000},   // Min         ( 0% adjust at 1,000 lux)
    })

Note the ordering of package elements: monotonically increasing from the lowest ambient light value (0 lux) to the brightness (1000 lux).
The transflective display example also highlights the need for non-zero values for the user's display brightness preference – which we'll refer to as the reference display brightness value. This requirement is derived from the model's use of relative adjustments. For example, applying any adjustment to a 0% reference display brightness value always results in a 0% absolute display brightness setting. Likewise, using a very small reference display brightness (e.g. 5%) results in a muted response (e.g. +30% of 5% = 6.5% absolute). The solution is to apply a reasonably large value (e.g. 50%) as the reference display brightness setting – even in the case where no backlight is applied. This allows relative adjustments to be applied in a meaningful fashion while conveying to the user that the display is still usable (via reflected light) under typical ambient conditions.
The OS derives the user's display brightness preference (this reference value) either from the Brightness Control Levels (_BCL) object or another OS-specific mechanism. See section 9.2.8, "Relationship to Backlight Control Methods", for more information.
9.2.6   _ALP (Ambient Light Polling)
This optional object evaluates to a recommended polling frequency (in tenths of seconds) for this ambient light sensor. A value of zero – or the absence of this object when other ALS objects are defined – indicates that OSPM does not need to poll the sensor in order to detect meaningful changes in ambient light (the hardware is capable of generating asynchronous notifications).
The use of polling is allowed but strongly discouraged by this specification. OEMs should design systems that asynchronously notify OSPM whenever a meaningful change in the ambient light occurs—relieving the OS of the overhead associated with polling.
This value is specified as tenths of seconds. For example, a value of 10 would be used to indicate a 1 second polling frequency. As this is a recommended value, OSPM will consider other factors when determining the actual polling frequency to use.
Arguments:
None
Result Code:
Zero:                       Polling by the OS is not required.
All other values:        The recommended polling frequency, in tenths of seconds.
9.2.7   Ambient Light Sensor Events
To communicate meaningful changes in ALS illuminance to OSPM, AML code should issue a Notify(als_device style='font-family:"Courier New"'>, 0x80) whenever the lux reading changes more than 10% (from the last reading that resulted in a notification). OSPM receives this notification and evaluates the _ALI control method to determine the current ambient light status. The OS then adjusts the display brightness based upon its ALS policy (derived from _ALR).
The definition of what constitutes a meaningful change is left to the system integrator, but should be at a level of granularity that provides an appropriate response without overly taxing the system with unnecessary interrupts. For example, an ALS configuration may be tuned to generate events for all changes in ambient light illuminance that result in a minimum �5% display brightness response (as defined by _ALR).
To communicate meaningful changes in ALS color temperature to OSPM, AML code should issue a Notify(als_device style='font-family:"Courier New"'>, 0x81) whenever the lux reading changes more than 10% (from the last reading that resulted in a notification). OSPM receives this notification and evaluates the _ALT and _ALC control method to determine the current ambient light color temperature.
To communicate meaningful changes in ALS response to OSPM, AML code should issue a Notify(als_device style='font-family:"Courier New"'>, 0x82) whenever the set of points used to convey ambient light response has changed. OSPM receives this notification and evaluates the _ALR object to determine the current response points.
9.2.8   Relationship to Backlight Control Methods
The Brightness Control Levels (_BCL) method –described in section 0 – can be used to indicate user-selectable display brightness levels. The information provided by this method indicates the available display brightness settings, the recommended default brightness settings for AC and DC operation, and the absolute maximum and minimum brightness settings. These values indirectly influence the operation of the OSPM's ALS policy.
Display brightness adjustments produced by ALS policy are relative to the current user backlight setting, and the resulting absolute value must be mapped (rounded) to one of the levels specified in _BCL. This introduces the requirement for fine-grain display brightness control in order to achieve a responsive ALS system – which typically materializes as a need for additional entries in the _BCL list in order to provide reasonable resolution to the OS (e.g. 3-10% granularity). Note that user brightness controls (e.g. hotkeys) are not required to make use of all levels specified in _BCL.
9.3   Battery Device
A battery device is required to either have an ACPI Smart Battery Table or a Control Method Battery interface. In the case of an ACPI Smart Battery Table, the Definition Block needs to include a Bus/Device Package for the SMBus host controller. This will install an OS specific driver for the SMBus, which in turn will locate the Smart Battery System Manager or Smart Battery Selector and Smart Battery Charger SMBus devices.
The Control Method Battery interface is defined in section 10.2, "Control Method Batteries."
9.4   Control Method Lid Device
Platforms containing lids convey lid status (open / closed) to OSPM using a Control Method Lid Device.
To implement a control method lid device, AML code should issue a Notify(lid_device style='font-family:"Courier New"'>, 0x80) for the device whenever the lid status has changed. The _LID control method for the lid device must be implemented to report the current state of the lid as either opened or closed.
The lid device can support _PRW and _PSW methods to select the wake functions for the lid when the lid transitions from closed to opened.
The Plug and Play ID of an ACPI control method lid device is PNP0C0D.
Table 9-4   Control Method Lid Device

Object	Description
_LID	Returns the current status of the lid.

9.4.1   _LID
Evaluates to the current status of the lid.
Result Code:
Zero:                       The lid is closed
Non-zero:                 The lid is open
9.5   Control Method Power and Sleep Button Devices
The system's power or sleep button can either be implemented using the fixed register space as defined in section 4.7.2.2, "Buttons," or implemented in AML code as a control method power button device. In either case, the power button override function or similar unconditional system power or reset functionality is still implemented in external hardware.
To implement a control method power-button or sleep-button device, implement AML code that delivers two types of notifications concerning the device. The first is Notify(Object, 0x80) to signal that the button was pressed while the system was in the S0 state to indicate that the user wants the machine to transition from S0 to some sleeping state. The other notification is Notify(Object, 0x2) to signal that the button was pressed while the system was in an S1 to S4 state and to cause the system to wake. When the button is used to wake the system, the wake notification (Notify(Object, 0x2)) must occur after OSPM actually wakes, and a button-pressed notification (Notify(Object, 0x80)) must not occur.
The Wake Notification indicates that the system is awake because the user pressed the button and therefore a complete system resume should occur (for example, turn on the display immediately, and so on).
9.6   Embedded Controller Device
Operation of the embedded controller host controller register interface requires that the embedded controller driver has ACPI-specific knowledge. Specifically, the driver needs to provide an "operational region" of its embedded controller address space, and needs to use a general-purpose event (GPE) to service the host controller interface more information about an ACPI-compatible embedded controller device, see section 12, "ACPI Embedded Controller Interface Specification."
The embedded controller device object provides the _HID of an ACPI-integrated embedded controller device of PNP0C09 and the host controller register locations using the device standard methods. In addition, the embedded controller must be declared as a named device object that includes a set of control methods. For more information, see section 12.11, "Defining an Embedded Controller Device in ACPI Namespace").
9.7   Fan Device
A fan device is assumed to be in operation when it is in the D0 state. Thermal zones reference fan device(s) as being responsible primarily for cooling within that zone. Notice that multiple fan devices can be present for any one thermal zone. They might be actual different fans, or they might be used to implement one fan of multiple speeds (for example, by turning both "fans" on the one fan will run full speed).
The Plug and Play ID of a fan device is PNP0C0B. For more information about fan devices, see section 11, "Thermal Management."
9.8   Generic Container Device
A generic container device is a bridge that does not require a special OS driver because the bridge does not provide or require any features not described within the normal ACPI device functions. The resources the bridge requires are specified via normal ACPI resource mechanisms. Device enumeration for child devices is supported via ACPI namespace device enumeration and OS drivers require no other features of the bus. Such a bridge device is identified with the Plug and Play ID of PNP0A05 or PNP0A06.
A generic bus bridge device is typically used for integrated bridges that have no other means of controlling them and that have a set of well-known devices behind them. For example, a portable computer can have a "generic bus bridge" known as an EIO bus that bridges to some number of Super-I/O devices. The bridged resources are likely to be positively decoded as either a function of the bridge or the integrated devices. In this example, a generic bus bridge device would be used to declare the bridge then child devices would be declared below the bridge; representing the integrated Super-I/O devices.
9.9   ATA Controller Devices
There are two types of ATA Controllers: IDE controllers (also known as ATA controllers) and Serial ATA (SATA) controllers. IDE controllers are those using the traditional IDE programming interface, and may support Parallel ATA (P-ATA) or SATA connections. SATA controllers may be designed to operate in emulation mode only, native mode only, or they may be designed to support both native and non-native SATA modes. Regardless of the mode supported, SATA controllers are designed to work solely with drives supporting the Serial ATA physical interface. As described below, SATA controllers are treated similarly but not identically to traditional IDE controllers.
Platforms that contain controllers that support native and non-native SATA modes must take steps to ensure the proper objects are placed in the namespace for the mode in which they are operating.
Table 9-5   ATA Specific Objects

Object	Description	Controller Type
_GTF	Optional object that returns the ATA task file needed to re-initialize the drive to boot up defaults.	Both
_GTM	Optional object that returns the IDE controller timing information.	IDE-only
_STM	Optional control method that sets the IDE controller's transfer timing settings.	IDE-only
_SDD	Optional control method that informs the platform of the type of device attached to a port.	SATA-only

9.9.1 Objects for Both ATA and SATA Controllers

9.9.1.1   _GTF (Get Task File)
This optional object returns a buffer containing the ATA commands used to restore the drive to boot up defaults (that is, the state of the drive after POST). The returned buffer is an array with each element in the array consisting of seven 8-bit register values (56 bits) corresponding to ATA task registers 1F1 thru 1F7. Each entry in the array defines a command to the drive.
This object may appear under SATA port device objects or under IDE channel objects.
ATA task file array definition:
·       Seven register values for command 1
·       Reg values: (1F1, 1F2, 1F3, 1F4, 1F5, 1F6, 1F7)
·       Seven register values for command 2
·       Reg values: (1F1, 1F2, 1F3, 1F4, 1F5, 1F6, 1F7)
·       Seven register values for command 3
·       lang=NO-BOK>Reg values: (1F1, 1F2, 1F3, 1F4, 1F5, 1F6, 1F7)
Etc��
After powering up the drive, OSPM will send these commands to the drive, in the order specified. On SATA HBAs, OSPM evaluates _SDD before evaluating _GTF. The IDE driver may modify some of the feature commands or append its own to better tune the drive for OSPM features before sending the commands to the drive.
This Control Method is listed under each drive device object. _GTF must be called after calling _STM.
Arguments:
None
Result Code:
A buffer that is a byte stream of ATA commands to send to the drive.
Example of the return from _GTF:

Method(_GTF, 0x0, NotSerialized)
{
    Return(GTF0)
}
Name(GTF0, Buffer(0x1c)
{
    0x03, 0x00, 0x00, 0x00, 0x00, 0xa0, 0xef, 0x03, 0x00, 0x00, 0x00, 0x00,
    0xa0, 0xef, 0x00, 0x10, 0x00, 0x00, 0x00, 0xa0, 0xc6, 0x00, 0x00, 0x00,
    0x00, 0x00, 0xa0, 0x91
}

9.9.2   IDE Controller Device
Most device drivers can save and restore the registers of their device. For IDE controllers and drives, this is not true because there are several drive settings for which ATA does not provide mechanisms to read. Further, there is no industry standard for setting timing information for IDE controllers. Because of this, ACPI interface mechanisms are necessary to provide the operating system information about the current settings for the drive and channel, and for setting the timing for the channel.
OSPM and the IDE driver will follow these steps when powering off the IDE subsystem:
1.    The IDE driver will call the _GTM control method to get the current transfer timing settings for the IDE channel. This includes information about DMA and PIO modes.
2.    The IDE driver will call the standard OS services to power down the drives and channel.
3.    As a result, OSPM will execute the appropriate _PS3 methods and turn off unneeded power resources.
To power on the IDE subsystem, OSPM and the IDE driver will follow these steps:
1.     The IDE driver will call the standard OS services to turn on the drives and channel.
2.     As a result, OSPM will execute the appropriate _PS0 methods and turn on required power resources.
3.     The IDE driver will call the _STM control method passing in transfer timing settings for the channel, as well as the ATA drive ID block for each drive on the channel. The _STM control method will configure the IDE channel based on this information.
4.     For each drive on the IDE channel, the IDE driver will run the _GTF to determine the ATA commands required to reinitialize each drive to boot up defaults.
5.     The IDE driver will finish initializing the drives by sending these ATA commands to the drives, possibly modifying or adding commands to suit the features supported by the operating system.
The following shows the namespace for these objects:

\_SB                  // System bus
    PCI0                 // PCI bus
       IDE1                  // First IDE channel
           _ADR                 // Indicates address of the channel on the PCI bus
           _GTM                 // Control method to get current IDE channel settings
           _STM                 // Control method to set current IDE channel settings
           _PR0                 // Power resources needed for D0 power state
           DRV1                 // Drive 0
              _ADR                 // Indicates address of master IDE device
              _GTF                 // Control method to get task file
           DRV2                 // Drive 1
           _   _ADR                  // Indicates address of slave IDE device
           _   _GTF                 // Control method to get task file
       IDE2                  // Second IDE channel
           _ADR                 // Indicates address of the channel on the PCI bus
           _GTM                 // Control method to get current IDE channel settings
           _STM                 // Control method to set current IDE channel settings
       _   _PR0                  //Power resources needed for D0 power state
           DRV1                 // Drive 0
              _ADR                 // Indicates address of master IDE device
              _GTF                 // Control method to get task file
           DRV2                 // Drive 1
              _ADR                 // Indicates address of slave IDE device
              _GTF                 // Control method to get task file

The sequential order of operations is as follows:
Powering down:

· Call _GTM.
· Power down drive (calls _PS3 method and turns off power planes).
Powering up:

· Power up drive (calls _PS0 method if present and turns on power planes).
· Call _STM passing info from _GTM (possibly modified), with ID data from
· each drive.
· Initialize the channel.
· May modify the results of _GTF.
· For each drive:
                        Call _GTF.
                        Execute task file (possibly modified).
9.9.2.1   IDE Controller-specific Objects

9.9.2.1.1   _GTM (Get Timing Mode)
This Control Method returns the current settings for the IDE channel.
This control method is listed under each channel device object.
Arguments:
None
Result Code:
A buffer with the current settings for the IDE channel:

Buffer (){
    PIO Speed 0                     //DWORD
    DMA Speed 0                     //DWORD
    PIO Speed 1                     //DWORD
    DMA Speed 1                     //DWORD
    Flags                        //DWORD
}
Table 9-6   _GTM Method Result Codes

Field	Format	Description
PIO Speed 0	DWORD	The PIO bus-cycle timing for drive 0 in nanoseconds. 0xFFFFFFFF indicates that this mode is not supported by the channel. If the chipset cannot set timing parameters independently for each drive, this field represents the timing for both drives.
DMA Speed 0	DWORD	The DMA bus-cycle for drive 0 timing in nanoseconds. If Bit 0 of the Flags register is set, this DMA timing is for UltraDMA mode, otherwise the timing is for multi-word DMA mode. 0xFFFFFFFF indicates that this mode is not supported by the channel. If the chipset cannot set timing parameters independently for each drive, this field represents the timing for both drives.
PIO Speed 1	DWORD	The PIO bus-cycle timing for drive 1 in nanoseconds. 0xFFFFFFFF indicates that this mode is not supported by the channel. If the chipset cannot set timing parameters independently for each drive, this field must be 0xFFFFFFFF.
DMA Speed 1	DWORD	The DMA bus-cycle timing for drive 1 in nanoseconds. If Bit 0 of the Flags register is set, this DMA timing is for UltraDMA mode, otherwise the timing is for multi-word DMA mode. 0xFFFFFFFF indicates that this mode is not supported by the channel. If the chipset cannot set timing parameters independently for each drive, this field must be 0xFFFFFFFF.
Flags	DWORD	Mode flags Bit[0]: 1 indicates using UltraDMA on drive 0 Bit[1]: 1 indicates IOChannelReady is used on drive 0 Bit[2]: 1 indicates using UltraDMA on drive 1 Bit[3]: 1 indicates IOChannelReady is used on drive 1 Bit[4]: 1 indicates chipset can set timing independently for each drive Bits[5-31]: reserved (must be 0)

9.9.2.1.2   _STM (Set Timing Mode)
This Control Method sets the IDE channel's transfer timings to the setting requested. The AML code is required to convert and set the nanoseconds timing to the appropriate transfer mode settings for the IDE controller. _STM may also make adjustments so that _GTF control methods return the correct commands for the current channel settings.
This control method takes three arguments: Channel timing information (as described in Table 9-6), and the ATA drive ID block for each drive on the channel. The channel timing information is not guaranteed to be the same values as returned by _GTM; the OS may tune these values as needed.
The ATA drive ID block is the raw data returned by the Identify Drive, ATA command, which has the command code "0ech." The _STM control method is responsible for correcting for drives that misreport their timing information.
Arguments:
Arg0                       Buffer    Channel timing information (formatted as described in Table 9-6)
Arg1                       Buffer    ATA drive IDE block for drive 0
Arg2                       Buffer    ATA drive IDE block for drive 1
Result Code:
None
9.9.3   Serial ATA (SATA) Controller Device
9.9.3.1   Definitions
· HBA – Host Bus Adapter
· Native SATA aware –Refers to system software (BIOS, option ROM, operating system, etc) that comprehends a particular SATA HBA implementation and understands its programming interface and power management behavior.
· Non-native SATA aware - Refers to system software (BIOS, option ROM, operating system, etc) that does not comprehend a particular SATA HBA implementation and does not understand its programming interface or power management behavior. Typically, non-native SATA aware software will use a SATA HBA's emulation interface (e.g. task file registers) to control the HBA and access its devices.
· Emulation mode –Optional mode supported by a SATA HBA. Allows non-native SATA aware software to access SATA devices via traditional task file registers.
· Native mode –Optional mode supported by a SATA HBA. Allows native SATA aware software to access SATA devices via registers that are specific to the HBA.
· Hybrid Device – Refers to a SATA HBA that implements both an emulation and a native programming interface.
9.9.3.2   Overview
A SATA HBA differs from an IDE controller in a number of ways. First, it can save its complete device context. Second, it replaces IDE channels, which may support up to 2 attached devices, with ports, which support only a single attached device, unless a port multiplier is present. See the SATA spec (http://www.serialata.org/collateral/index.shtml) for more information. Finally, SATA does not require timing information from the platform, allowing a simplification in how SATA controllers are represented in ACPI. (_GTM and _STM are replaced by the simpler _SDD method.)
All ports, even those attached off a port multiplier, are represented as children directly under the SATA controller device. This is practical because the SATA specification does not allow a port multiplier to be attached to a port multiplier. Each port's _ADR indicates to which root port they are connected, as well as the port multiplier location, if applicable. (See Table 6-2 for _ADR format.)
Since this specification only covers the configuration of motherboard devices, it is also the case that the control methods defined in this section cannot be used to send taskfiles to devices attached via either an add-in SATA HBA, or attached via a motherboard SATA HBA, if used with a port multiplier that is not also on the motherboard.
The following shows an example SATA namespace:

\_SB              -System bus
    PCI0          -PCI bus
       SATA       -SATA Controller device
_          ADR        -Indicates address of the controller on the PCI bus
_          PR0 -      Power resources needed for D0 power state
           PRT0       - Port 0 device

              _ADR       -Indicates physical port and port multiplier topology
              _SDD       -Identify information for drive attached to this port
              _GTF       -Control method to get task file
           PRTn       - Port n device

              _ADR       -Indicates physical port and port multiplier topology
              _SDD       -Identify information for drive attached to this port
              _GTF       -Control method to get task file

9.9.3.3   SATA controller-specific control methods
In order to ensure proper interaction between OSPM, the firmware, and devices attached to the SATA controller, it is a requirement that OSPM execute the _SDD and _GTF control methods when certain events occur. OSPM's response to events must be as follows:

COMRESET, Initial OS load, device insertion, HBA D3 to D0 transition, asynchronous loss of signal:
1.    OSPM sends IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command to the attached device.
2.    OS executes _SDD. _SDD control method requires 1 argument that consists of the data block received from an attached device as a result of a host issued IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command.
3.    After the _SDD method completes, the OS executes the _GTF method. Using the task file information provided by _GTF, the OS then sends the _GTF taskfiles to the attached device.
Device removal and HBA D0 to D3 transition:
1.    No OSPM action required.
9.9.3.3.1   _SDD (Set Device Data)
This optional object is a control method that conveys to the platform the type of device connected to the port. The _SDD object may exist under a SATA port device object. The platform typically uses the information conveyed by the _SDD object to construct the values returned by the _GTF object.
OSPM conveys to the platform the ATA drive ID block, which is the raw data returned by the Identify (Packet) Device, ATA command (command code "0ech."). Please see the ATA/ATAPI-6 specification for more details.
Arguments:
Arg0                       Buffer    ATA drive identify block, contents described by the ATA specification
Result Code:
None

9.10   Floppy Controller Device Objects
9.10.1   _FDE (Floppy Disk Enumerate)
Enumerating devices attached to a floppy disk controller is a time-consuming function. In order to speed up the process of floppy enumeration, ACPI defines an optional enumeration object that is defined directly under the device object for the floppy disk controller. It returns a buffer of five 32-bit values. The first four values are Boolean values indicating the presence or absence of the four floppy drives that are potentially attached to the controller. A non-zero value indicates that the floppy device is present. The fifth value returned indicates the presence or absence of a tape controller. Definitions of the tape presence value can be found in Table 9-7.
Arguments:
None
Result Code:
A buffer containing values that indicate the presence or absence of floppy devices.

Buffer (){
    Floppy 0                     // Boolean DWORD
    Floppy 1                     // Boolean DWORD
    Floppy 2                     // Boolean DWORD
    Floppy 3                     // Boolean DWORD
    Tape                          // See table below
}
Table 9-7   Tape Presence

Value	Description
0	Unknown if device is present
1	Device is present
2	Device is never present
>2	Reserved

9.10.2   _FDI (Floppy Disk Information)
This object returns information about a floppy disk drive. This information is the same as that returned by the INT 13 Function 08H on IA-PCs.
Result Code:

Package {
    Drive Number                 //BYTE
    Device Type                     //BYTE
    Maximum Cylinder Number      //WORD
    Maximum Sector Number        //WORD
    Maximum Head Number          //WORD
    disk_specify_1               //BYTE
    disk_specify_2               //BYTE
    disk_motor_wait              //BYTE
    disk_sector_siz              //BYTE
    disk_eot                     //BYTE
    disk_rw_gap                     //BYTE
    disk_dtl                     //BYTE
    disk_formt_gap               //BYTE
    disk_fill                    //BYTE
    disk_head_sttl               //BYTE
    disk_motor_strt              //BYTE
}
Table 9-8   ACPI Floppy Drive Information

Field	Format	Definition
Drive Number	BYTE	As reported by _INT 13 Function 08H
Device Type	BYTE	As reported by _INT 13 Function 08H
Maximum Cylinder Number	WORD	As reported by _INT 13 Function 08H
Maximum Sector Number	WORD	As reported by _INT 13 Function 08H
Maximum Head Number	WORD	As reported by _INT 13 Function 08H
Disk_specify_1	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_specify_2	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_motor_wait	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_sector_siz	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_eot	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_rw_gap	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_dtl	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_formt_gap	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_fill	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_head_sttl	BYTE	As reported in ES:D1 from INT 13 Function 08H
Disk_motor_strt	BYTE	As reported in ES:D1 from INT 13 Function 08H

9.10.3   _FDM (Floppy Disk Drive Mode)
This control method switches the mode (300RPM/360RPM) of all floppy disk drives attached to this controller. If this control method is implemented, the platform must reset the mode of all drives to 300RPM mode after a Dx to D0 transition of the controller.
Arguments:
0 – Set the mode of all drives to 300RPM mode.
1 – Set the mode of all drives to 360RPM mode.
Result Code:
None
9.11   GPE Block Device
The GPE Block device is an optional device that allows a system designer to describe GPE blocks beyond the two that are described in the FADT. Control methods associated with the GPE pins of GPE block devices exist as children of the GPE Block device, not within the \_GPE namespace.
A GPE Block device consumes I/O or memory address space, as specified by its _PRS or _CRS child objects. The interrupt vector used by the GPE block does not need to be the same as the SCI_INT field. The interrupt used by the GPE block device is specified in the _CRS and _PRS methods associated with the GPE block. The _CRS of a GPE Block device may only specify a single register address range, either I/O or memory. This range contains two registers: the GPE status and enable registers. Each register's length is defined as half of the length of the _CRS-defined register address range.
A GPE Block device must have a _HID or a _CID of "ACPI0006."
Note: A system designer must describe the GPE block necessary to bootstrap the system in the FADT as a GPE0/GPE1 block. GPE Block devices cannot be used to implement these GPE inputs.
To represent the GPE block associated with the FADT, the system designer needs only to include the ACPI0006 device in the tree, and not have any _CRS, _PRS, _SRS, or other GPE-specific methods associated with that block. Any block that does not represent the GPE block of the FADT must contain the _Lxx, _Exx, _Wxx, _CRS, _PRS, or _SRS methods required to use/program that block. OSPM assumes the first ACPI0006 device without a _CRS is the GPE device that is associated with the FADT.

// ASL example of root GPE block
Device(\_SB.PCI0.GPE0) {
    Name(_HID,"ACPI0006")
    Name(_UID,1)
}

// ASL example of a non-root GPE block
Device(\_SB.PCI0.GPE1) {
    Name(_HID, "ACPI0006")
    Name(_UID, 2)
    Name(_CRS, Buffer () {
       IO(Decode16, FC00, FC03, 4, 4,)
       IRQ( Level, ActiveHigh, Shared,) { 5 }
    })

    Method(_L02) { � }
    Method(_E07) { � }
    Method(_W04) { � }

Notice that it is legal to replace the I/O descriptors with Memory descriptors if the register is memory mapped.
If the system must run any GPEs to bootstrap the system (for example, when Embedded Controller events are required), the associated block of GPEs must be described in the FADT. This register block is not relocatable and will always be available for the life of the operating system boot.
The GPE block associated with the ACPI0006 device can be stopped, ejected, reprogrammed, and so on. The system can also have multiple such GPE blocks.

9.11.1   Matching Control Methods for General-Purpose Events in a GPE Block Device
When a GPE Device raises an interrupt, OSPM executes a corresponding control method (as described in section 5.6.2.2.3, "Queuing the Matching Control Method for Execution"). These control methods (of the form _Lxx, _Exx, and _Wxx) for GPE Devices are not within the \_GPE namespace. They are children of the GPE Block device.
For example:

Device(GPE5) {
    Name(_HID, "ACPI0006")

    Method(_L02) { � }
    Method(_E07) { � }
    Method(_W04) { � }
}
9.12   Module Device
This optional device is a container object that acts as a bus node in a namespace. It may contain child objects that are devices or buses. The module device is declared using the ACPI0004 hardware identifier (HID).
If the module device contains a _CRS object, the "bus" described by this object is assumed to have these resources available for consumption by its child devices. If a _CRS object is present, any resources not produced in the module device's _CRS object may not be allocated to child devices.
Providing a _CRS object is undesirable in some module devices. For example, consider a module device used to describe an add-in board containing multiple host bridges without any shared resource decoding logic this case the resource ranges available to the host bridges are not controlled by any entity residing on the add-in board, implying that a _CRS object in the associated module device would not describe any real feature of the underlying hardware. A_CRS object must exist with a module device if the device contains PCI host bridge devices (See section 9.12.1 "Describing PCI Bus and Segment Group Numbers under Module Devices").
To account for cases like this, the system designer may optionally omit the module device's _CRS object. If no _CRS object is present, OSPM will assume that the module device is a simple container object that does not produce the resources consumed by its child devices. In this case, OSPM will assign resources to the child devices as if they were direct children of the module device's parent object.
For an example with a module device _CRS object present, consider a Module Device containing three child memory devices. If the _CRS object for the Module Device contains memory from 2 GB through 6 GB, then the child memory devices may only be assigned addresses within this range.
Example:

Device (\_SB.NOD0) {
    Name (_HID, "ACPI0004")                // Module device
    Name (_UID, 0)
    Name (_PRS, ResourceTemplate() {
       WordIO (
           ResourceProducer,
           MinFixed,            // _MIF
           MaxFixed,,,              // _MAF
           0x0000,                  // _GRA
           0x0000,                  // _MIN
           0x7FFF,                  // _MAX
           0x0,                 // _TRA
           0x8000)                  // _LEN
       DWordMemory (
           ResourceProducer,,        // For Main Memory + PCI
           MinNotFixed,          // _MIF
           MaxNotFixed,          // _MAF
           Cacheable,           // _MEM
           ReadWrite,           // _RW
           0x0FFFFFFF,              // _GRA
           0x40000000,              // _MIN
           0x7FFFFFFF,              // _MAX
           0x0,                 // _TRA
           0x00000000)              // _LEN
    })
    Method (_SRS, 1) { ... }
    Method (_CRS, 0) { ... }

    Device (MEM0) {                         // Main Memory (256MB module)
       Name (_HID, EISAID("PNP0C80"))
       Name (_UID, 0)
       Method (_STA, 0) {       // If memory not present --> Return(0x00)
                             // Else if memory is disabled --> Return(0x0D)
                             // Else --> Return(0x0F)
       }
        Name (_PRS, ResourceTemplate () {
           DWordMemory (,,,,
              Cacheable,        // _MEM
              ReadWrite,        // _RW
              0x0FFFFFFF,          // _GRA
              0x40000000,          // _MIN

              0x7FFFFFFF,          // _MAX
              0x0,              // _TRA
              0x10000000)           // _LEN
       })
       Method (_CRS, 0) { ... }
       Method (_SRS, 1) { ... }
       Method (_DIS, 0) { ... }
    }
    Device (MEM1) {                         // Main Memory (512MB module)
       Name (_HID, EISAID("PNP0C80"))
       Name (_UID, 1)
       Method (_STA, 0) {       // If memory not present --> Return(0x00)
                             // Else if memory is disabled --> Return(0x0D)
                             // Else --> Return(0x0F)
       }
       Name (_PRS, ResourceTemplate () {
           DWordMemory (,,,,
              Cacheable,        // _MEM
              ReadWrite,        // _RW
              0x1FFFFFFF,          // _GRA
              0x40000000,           // _MIN
              0x7FFFFFFF,          // _MAX
              0x0,              // _TRA
              0x20000000)          // _LEN
       })
       Method (_CRS, 0) { ... }
       Method (_SRS, 1) { ... }
       Method (_DIS, 0) { ... }
    }
    Device (PCI0) {                         // PCI Root Bridge
       Name (_HID, EISAID("PNP0A03"))
       Name (_UID, 0)
       Name (_BBN, 0x00)
       Name (_PRS, ResourceTemplate () {
           WordBusNumber (
              ResourceProducer,
              MinFixed,        // _MIF
              MaxFixed,,        // _MAF
              0x00,             // _GRA
              0x00,             // _MIN
              0x7F,             // _MAX
              0x0,              // _TRA
              0x80)             // _LEN
           WordIO (
              ResourceProducer,
              MinFixed,        // _MIF
              MaxFixed,,,           // _MAF
              0x0000,              // _GRA
              0x0000,              // _MIN
              0x0CF7,              // _MAX
              0x0,              // _TRA
              0x0CF8)              // _LEN
           WordIO (
              ResourceProducer,
              MinFixed,        // _MIF
              MaxFixed,,,          // _MAF

              0x0000,              // _GRA
              0x0D00,              // _MIN
              0x7FFF,              // _MAX
              0x0,              // _TRA
              0x7300)              // _LEN

           DWordMemory (
              ResourceProducer,,
              MinNotFixed,     // _MIF
              MaxNotFixed,     // _MAF
              NonCacheable,     // _MEM
              ReadWrite,        // _RW
              0x0FFFFFFF,          // _GRA

0x40000000, // _MIN

              0x7FFFFFFF,          // _MAX
              0x0,              // _TRA
              0x00000000)          // _LEN
       })
       Method (_CRS, 0) { ... }
       Method (_SRS, 1) { ... }
    }
}
9.12.1   Describing PCI Bus and Segment Group Numbers under Module Devices
If a module device exposes one or more PCI root busses, OSPM must be able to determine what PCI bus and segment group numbers are defined for the module device. A module device may be a container for root buses in multiple segment groups. Because the _SEG method can only return a single number, _SEG cannot adequately describe this case. To properly convey this information to OSPM, the PCI bus number resource descriptor in the module device must include both the bus and segment resources produced by the module device. To describe this in systems that implement multiple PCI segment groups, the segment group resources produced by a module device must be encoded in bits 8 and higher of the module device's WordBusNumber resource descriptor. For systems that do not expose multiple PCI segment groups, bits 8 and higher of the module device's WordBusNumber resource descriptor must be zero.
Note: The range of PCI segment groups reported in the _CRS of module devices cover both assigned and unassigned PCI root bridges. In the case of hot add of a PCI root bridge, OSPM does not re-evaluate the _CRS of its parent module device as its resources are not expected to change in this case.
For an example of a module device encoding PCI segment group ranges with PCI bus number resources, consider a module device that describes two PCI root bridges as child devices. The _CRS for the module device describes 2 PCI root bridges as child devices, where each PCI root bridge consumes its own PCI segment.
Example:

Device (\_SB.NOD0) {
    Name (_HID, "ACPI0004")                 // Module device
    Name (_UID, 0)
    Name (_CRS, ResourceTemplate() {
       WordIO (
           ResourceProducer,
           MinFixed,             // _MIF
           MaxFixed,,,              // _MAF
           0x0000,                  // _GRA
           0x0000,                  // _MIN
           0x7FFF,                  // _MAX
           0x0,                  // _TRA
           0x8000)                  // _LEN
       DWordMemory (
           ResourceProducer,,       // For Main Memory + PCI
           MinNotFixed,          // _MIF
           MaxNotFixed,          // _MAF
           Cacheable,            // _MEM
           ReadWrite,            // _RW
           0x0FFFFFFF,              // _GRA
           0x40000000,              // _MIN
           0x7FFFFFFF,              // _MAX
           0x0,                  // _TRA
           0x00000000)              // _LEN
       WordBusNumber (
           ResourceProducer,
           MinFixed,         // _MIF
           MaxFixed,,        // _MAF
           0x00,             // _GRA
           0x0000,              // _MIN (indicates minimum segment number 0)
           0x01FF,              // _MAX (indicates maximum segment of 1)
           0x0,              // _TRA
           0x80)             // _LEN

    })
    Device (PCI0) {                         // PCI Root Bridge
       Name (_HID, EISAID("PNP0A03"))
       Name (_UID, 0)
       Name (_BBN, 0x00)
       Name (_SEG, 0x00)     // assign segment 0 of module device to PCI0
       Name (_CRS, ResourceTemplate () {
           WordBusNumber (
              ResourceProducer,
              MinFixed,         // _MIF
              MaxFixed,,        // _MAF
              0x00,             // _GRA
              0x00,             // _MIN
              0xFF,             // _MAX
              0x0,              // _TRA
              0x80)             // _LEN
           WordIO (
              ResourceProducer,
              MinFixed,         // _MIF
              MaxFixed,,,           // _MAF
              0x0000,               // _GRA
              0x0000,              // _MIN
              0x0CF7,              // _MAX
              0x0,              // _TRA
              0x0CF8)               // _LEN
           DWordMemory (
              ResourceProducer,,
              MinNotFixed,      // _MIF
              MaxNotFixed,      // _MAF
              NonCacheable,     // _MEM
              ReadWrite,        // _RW
              0x0FFFFFFF,           // _GRA
              0x40000000,          // _MIN

              0x5FFFFFFF,          // _MAX
              0x0,              // _TRA
              0x00000000)           // _LEN
       })
    }
}
    Device (PCI1) {                         // PCI Root Bridge
       Name (_HID, EISAID("PNP0A03"))
       Name (_UID, 0)
       Name (_BBN, 0x00)
       Name (_SEG, 0x01)        // assign segment 1 of module device to PCI1
       Name (_CRS, ResourceTemplate () {
           WordBusNumber (
              ResourceProducer,
              MinFixed,         // _MIF
              MaxFixed,,        // _MAF
              0x00,             // _GRA
              0x00,             // _MIN
              0x7F,             // _MAX
              0x0,              // _TRA
              0x80)             // _LEN
           WordIO (
              ResourceProducer,
              MinFixed,         // _MIF
              MaxFixed,        // _MAF

              0x0000,              // _GRA
              0x0D00,              // _MIN
              0x7FFF,              // _MAX
              0x0,              // _TRA
              0x7300)               // _LEN

           DWordMemory (
              ResourceProducer,
              MinNotFixed,      // _MIF
              MaxNotFixed,      // _MAF
              NonCacheable,     // _MEM
              ReadWrite,        // _RW
              0x0FFFFFFF,           // _GRA
              0x60000000,          // _MIN

               0x7FFFFFFF,          // _MAX
              0x0,              // _TRA
              0x00000000)           // _LEN
       })
    }
}
9.13   Memory Devices
Memory devices allow a platform designer to optionally describe the dynamic properties of memory. If a platform cannot have memory added or removed while the system is active, then memory devices are not necessary. Memory devices may describe exactly the same physical memory that the System Address Map interfaces describe (see section 15, "System Address Map Interfaces"). They do not describe how that memory is, or has been, used. If a region of physical memory is marked in the System Address Map interface as AddressRangeReserved or AddressRangeNVS and it is also described in a memory device, then it is the responsibility of the OS to guarantee that the memory device is never disabled.
It is not necessary to describe all memory in the system with memory devices if there is some memory in the system that is static in nature. If, for instance, the memory that is used for the first 16 MB of system RAM cannot be ejected, inserted, or disabled, that memory may only be represented by the System Address Map interfaces. But if memory can be ejected, inserted, or disabled, it must be represented by a memory device.
9.13.1   Address Decoding
Memory devices must provide a _CRS object that describes the physical address space that the memory decodes. If the memory can decode alternative ranges in physical address space, the devices may also provide _PRS, _SRS and _DIS objects. Other device objects may also apply if the device can be ejected.
9.13.2   Example: Memory Device

Scope (\_SB){
    Device (MEM0) {
       Name (_HID, EISAID ("PNP0C80"))
       Name (_CRS, ResourceTemplate () {
           QwordMemory
              ResourceConsumer,
              ,
              MinFixed,
              MaxFixed,
              Cacheable,
              ReadWrite,
              0xFFFFFFF,
               0x10000000,
              0x30000000,
              0,
              ,,)
       }
    }
}
9.14   _UPC (USB Port Capabilities)
This optional object is a method that allows the platform to communicate to the operating system, certain USB port capabilities that are not provided for through current USB host bus adaptor specifications (e.g. UHCI, OHCI and EHCI). If implemented by the platform, this object will be present for each USB port (child) on a given USB host bus adaptor; operating system software can examine these characteristics at boot time in order to gain knowledge about the system's USB topology, available USB ports, etc. This method is applicable to USB root hub ports as well as ports that are implemented through integrated USB hubs.
Syntax
_UPC => UPCPackage
Return Value
UPCPackage: Package (PortIsConnectable, PortConnectorType, Reserved0, Reserved1)
Where:
PortIsConnectable:ByteConst
If this value is non-zero (0xFF), then the port is connectable. If this value is zero (0x00), then the port is not connectable.

Note: The definition of a 'connectable' port is dependent upon the implementation of the USB port within a particular platform. For example,

�       If a USB port is user visible (as indicated by the _PLD object) and connectable, then an end user can freely connect and disconnect USB devices to the USB port.

�       If a USB port is not user visible and is connectable, then an end user cannot freely connect and disconnect USB devices to the USB port. A USB device that is directly "hard-wired" to a USB port is an example of a USB port that is not user visible and is connectable.

�       If a USB port is not user visible and is not connectable, then the USB port is physically implemented by the USB host controller, but is not being used by the platform and therefore cannot be accessed by an end user.

It is illegal for a USB port to be specified as visible and not connectable.
PortConnectorType:ByteConst
This field is used to specify the host connector type. It is ignored by OSPM if the port is not user visible:
0x00:                Type 'A' connector
0x01:                Mini-AB connector
0x02:                ExpressCard
0x03 - 0xFE:      Reserved
0xFF:                Proprietary connector
Reserved0: Dword style='font-size:90%;font-family:"Courier New"'>Const
This value is reserved for future use and must be zero.
Reserved1: Dword style='font-size:90%;font-family:"Courier New"'>Const
This value is reserved for future use and must be zero.
EXAMPLE
The following is an example of a port characteristics object implemented for a USB host controller's root hub where:
�      3 Ports are implemented; Port 1 is not user visible/not connectable and Ports 2 and 3 are user visible and connectable.
�      Port 2 is located on the back panel
�      Port 3 has an integrated 2 port hub. Note that because this port hosts an integrated hub, it is therefore not sharable with another host controller (e.g. If the integrated hub is a USB2.0 hub, the port can never be shared with a USB1.1 companion controller).
�      The ports available through the embedded hub are located on the front panel and are adjacent to one another.

//
// Root hub device for this host controller. This controller implements 3 root hub ports.
//
Device( RHUB) {
    Name( _ADR, 0x00000000)      // root HUB always has a value of 0
    // Root hub, port 1
    Device( PRT1) {
// Address object for port 1. This value must be 1
       Name( _ADR, 0x00000001)
       // USB port capabilities object. This object returns the system
        // specific USB port configuration information for port number 1
       // Because this port is not connectable it is assumed to be not visible.
// Therefore a _PLD descriptor is not required.
Name( _UPC, Package(){
0x00,                    // Port is not connectable
0xFF,                    // Connector type (N/A for non-visible ports)
0x00000000,                  // Reserved 0 – must be zero
0x00000000})             // Reserved 1 – must be zero
    } // Device( PRT1)

    //
    // Root Hub, Port 2
    //
    Device( PRT2) {
       // Address object for port 2. This value must be 2
       Name(_ADR, 0x00000002)
Name( _UPC, Package(){
0xFF,                    // Port is connectable
0x00,                    // Connector type – Type 'A'
0x00000000,                  // Reserved 0 – must be zero
0x00000000})             // Reserved 1 – must be zero
// provide physical port location info
Name( _PLD, Buffer( 0x10) {
0x00000081,              // Revision 1, Ignore color
                      // Color (ignored), width and height not
0x00000000,              // required as this is a standard USB 'A' type
                      // connector

0x00000c69,              // User visible, Back panel, Vertical
                      // Center, shape = vert. rectangle
                  0x00000003})          // ejectable, requires OPSM eject assistance
} // Device( PRT2)

//
    // Root Hub, Port 3
    //
    Device( PRT3) {
       // Address object for port 3. This value must be 3
Name(_ADR, 0x00000003)
// Because this port is not connectable it is assumed to be not visible.
// Therefore a _PLD descriptor is not required.
Name( _UPC, Package(){
0x00,                    // Port is not connectable
0xFF,                    // Connector type (N/A for non-visible ports)
0x00000000,                  // Reserved 0 – must be zero
0x00000000})             // Reserved 1 - must be zero

       // Declare the integrated hub object
       Device( IHUB) {
           // Address object for the hub. This value must be 0
           Name(_ADR, 0x00000000)
// Integrated hub, port 1
           Device( PRT1) {
// Address object for the port. Because the port is implemented on
// integrated hub port #1, this value must be 1
              Name( _ADR, 0x00000001)
               // USB port characteristics object. This object returns the system
// specific USB port configuration information for integrated hub port
// number 1
Name( _UPC, Package(){
0xFF,                    // Port is connectable
0x00,                    // Connector type – Type 'A'
0x00000000,                  // Reserved 0 – must be zero
0x00000000})             // Reserved 1 – must be zero

// provide physical port location info
Name( _PLD, Buffer( 0x10) {
    0x00000081,           // Revision 1, Ignore color
                      // Color (ignored), width and height not
    0x00000000,           // required as this is a standard USB 'A' type
                      // connector

    0x000010a1,           // User visible, front panel, Vertical
                      // lower, horz. Left, shape = horz. rectangle
    0x00000003})      // ejectable, requires OPSM eject assistance
           } // Device( PRT1)

//
// Integrated hub, port 2
//
Device( PRT2) {
// Address object for the port. Because the port is implemented on
// integrated hub port #2, this value must be 2
Name( _ADR, 0x00000002)
// USB port characteristics object. This object returns the system
// specific USB port configuration information for integrated hub port
// number 2
Name( _UPC, Package(){
0xFF,                    // Port is connectable
0x00,                    // Connector type – Type 'A'
0x00000000,                  // Reserved 0 – must be zero
0x00000000})             // Reserved 1 – must be zero
Name( _PLD, Buffer( 0x10) {
    0x00000081,           // Revision 1, Ignore color
                      // Color (ignored), width and height not
    0x00000000,           // required as this is a standard USB 'A' type
                      // connector

    0x000012a1,           // User visible, front panel, Vertical
                      // lower, horz. right, shape = horz. rectangle
    0x00000003})      // ejectable, requires OPSM eject assistance
           } // Device( PRT2)

} // Device( IHUB)
} // Device( PRT3)
} // Device( RHUB)
9.14.1   USB 2.0 Host Controllers and _UPC and _PLD
Platforms implementing USB2.0 host controllers that consist of one or more USB1.1 compliant companion controllers (e.g. UHCI or OHCI) must implement a _UPC and a _PLD object for each port USB port that can be routed between the EHCI host controller and its associated companion controller. This is required because a USB Port Capabilities object implemented for a port that is a child of an EHCI host controller may not be available if the OSPM disables the parent host controller. For example, if root port 1 on an EHCI host controller is routable to root port 1 on its companion controller, then the namespace must provide a _UPC and a _PLD object under each host controller's associated port 1 child object.
EXAMPLE

Scope( \_SB) {
�
Device(PCI0) {
�
// Host controller (EHCI)
Device( USB0) {
// PCI device#/Function# for this HC. Encoded as specified in the ACPI
// specification
Name(_ADR, 0xyyyyzzzz)
// Root hub device for this HC #1.
Device(RHUB) {
Name(_ADR, 0x00000000)       // must be zero for USB root hub
// Root hub, port 1
Device(PRT1) {
Name(_ADR, 0x00000001)

                              // USB port configuration object. This object returns the system
// specific USB port configuration information for port number 1
// Must match the _UPC declaration for USB1.RHUB.PRT1 as it is this
// host controller's companion
Name( _UPC, Package(){
0xFF,                    // Port is connectable
0x00,                    // Connector type – Type 'A'
0x00000000,                  // Reserved 0 – must be zero
0x00000000})             // Reserved 1 – must be zero
// provide physical port location info for port 1
// Must match the _UPC declaration for USB1.RHUB.PRT1 as it is this
// host controller's companion
Name( _PLD, Buffer( 0x10) {
    0x00000081,           // Revision 1, Ignore color
                      // Color (ignored), width and height not
    0x00000000,           // required as this is a standard USB 'A' type
                      // connector

    0x000010a1,           // User visible, front panel, Vertical
                      // lower, horz. Left, shape = horz. rectangle
    0x00000003})      // ejectable, requires OPSM eject assistance
} // Device( PRT1)
//
// Define other ports, control methods, etc
�
�
} // Device( RHUB)
} // Device( USB0)

// Companion Host controller (OHCI or UHCI)
Device( USB1) {
// PCI device#/Function# for this HC. Encoded as specified in the ACPI
// specification
Name(_ADR, 0xyyyyzzzz)
// Root hub device for this HC #1.
Device(RHUB) {
Name(_ADR, 0x00000000)       // must be zero for USB root hub
// Root hub, port 1
Device(PRT1) {
Name(_ADR, 0x00000001)
// USB port configuration object. This object returns the system
// specific USB port configuration information for port number 1
// Must match the _UPC declaration for USB0.RHUB.PRT1 as this host
// controller is a companion to the EHCI host controller
// provide physical port location info for port 1
Name( _UPC, Package(){
0xFF,                    // Port is connectable
0x00,                    // Connector type – Type 'A'
0x00000000,                  // Reserved 0 – must be zero
0x00000000})             // Reserved 1 – must be zero

// Must match the _PLD declaration for USB0.RHUB.PRT1 as this host
// controller is a companion to the EHCI host controller
Name( _PLD, Buffer( 0x10) {
    0x00000081,           // Revision 1, Ignore color
                      // Color (ignored), width and height not
    0x00000000,           // required as this is a standard USB 'A' type
                      // connector

    0x000010a1,           // User visible, front panel, Vertical
                      // lower, horz. Left, shape = horz. rectangle
    0x00000003})      // ejectable, requires OPSM eject assistance
} // Device( PRT1)
//
// Define other ports, control methods, etc
�
�
} // Device( RHUB)
} // Device( USB1)
} // Device( PCI0)
} // Scope( _\SB)
9.15   Device Object Name Collision
Devices containing both _HID and _CID may have device specific control methods pertaining to both the device ID in the _HID and the device ID in the _CID. These device specific control methods are defined by the device owner (a standard body or a vendor or a group of vendor partners). Since these object names are not controlled by a central authority, there is a likelihood that the names of objects will conflict between two defining parties. The _DSM object described in the next section solves this conflict.
9.15.1   _DSM (Device Specific Method)
This optional object is a control method that enables devices to provide device specific control functions that are consumed by the device driver.
Arguments:
Arg0 (Buffer):                 UUID
Arg1 (Integer):                Revision ID
Arg2 (Integer):             Function Index
Arg3 (Package):             Arguments

UUID –Universal Unique Identifier (16 Byte Buffer)
Revision ID – the function's revision. This revision is specific to the UUID.
Function Index – Represents a specific function whose meaning is specific to the UUID and Revision ID. Function indices should start with 1. Function number zero is a query function (see the special return code defined below).
Arguments – a package containing the parameters for the function specified by the UUID, Revision ID and Function Index. Successive revisions of Function Arguments must be backward compatible with earlier revisions. See section 9, "ACPI Devices and Device Specific Objects", for any _DSM definitions for ACPI devices. New UUIDs may also be created by OEMs and IHVs for custom devices and other interface or device governing bodies (e.g. the PCI SIG), as long as the UUID is different from other published UUIDs. Only the issuer of a UUID can authorize a new Function Index, Revision ID or Function Argument for that UUID.

Result Code:
Return – If Function Index is zero, the return is a buffer, with one bit for each function index, starting with zero. Bit 0 indicates support for at least one function for the specified UUID and Revision ID. If set to zero, no functions are supported for the specified UUID and Revision ID. If set to one, at least one function is supported. For all other bits in the buffer, a bit is set to zero to indicate if the function index is not supported for the specific UUID and Revision ID. If the bit representing a particular function index would lie outside of the buffer, it should be assumed to be 0 (that is, not supported).
If Function index is non-zero, the return is any data object. The type and meaning of the returned data object depends on the UUID and Revision ID.
Implementation Note
Since the purpose of the _DSM method is to avoid the name space collision, the implementation of this method shall not use any other method or data object which is not defined in this specification unless its driver and usage is completely under the control of the platform vendor.
Example:

// _DSM – Device Specific Method
//
// Arg0:   UUID       Unique function identifier
// Arg1: Integer       Revision Level
// Arg2: Integer       Function Index (0 = Return Supported Functions)
// Arg3: Package       Parameters
Function(_DSM,{IntObj,BuffObj},{BuffObj, IntObj, IntObj, PkgObj})
{
    //
    // Switch based on which unique function identifier was passed in
    //
    switch(Arg0)
    {
       //
       // First function identifier
       //
       case(ToUUID("893f00a6-660c-494e-bcfd-3043f4fb67c0"))
       {
           switch(Arg2)
           {
              //
              // Function 0: Return supported functions, based on revision
              //
              case(0)
              {
                  switch(Arg1)
                  {
                      // revision 0: functions 1-4 are supported
                      case(0) {return (Buffer() {0x1F})}
                      // revision 1: functions 1-5 are supported
                      case(1) {return (Buffer() {0x3F})}
                  }
                  // revision 2+: functions 1-7 are supported
                  return (Buffer() {0x7F})
              }
              //
              // Function 1:
              //
              case(1)
              {
                  � function 1 code �
                  Return(Zero)
              }
              //
              // Function 2:
              //
              case(2)
              {
                  � function 2 code �
                  Return(Buffer(){0x00})
              }
              case(3) { � function 3 code �}
              case(4) { � function 4 code �}
              case(5) { if (LLess(Arg1,1) BreakPoint; � function 5 code � }
              case(6) { if (LLess(Arg1,2) BreakPoint; � function 6 code � )
              case(7) { if (LLess(Arg1,3) BreakPoint; � function 7 code � )
              default {BreakPoint }
           }
       }
       //
       // Second function identifier
       //
       case(ToUUID("107ededd-d381-4fd7-8da9-08e9a6c79644"))
       {
           //
           // Function 0: Return supported functions (there is only one revision)
           //
           if (LEqual(Arg2,Zero))
              return (Buffer() {0x3}) // only one function supported
           //
           // Function 1
           //
           if (LEqual(Arg2,One))
           {
              � function 1 code �
              Return(Unicode("text"))
           }
           //
           // Function 2+: Runtime Error
           //
           else
              BreakPoint;
        }
    }
    //
    // If not one of the function identifiers we recognize, then return a buffer
    // with bit 0 set to 0 indicating no functions supported.
    //
    return(Buffer(){0})
}
9.16 PC/AT RTC/CMOS Devices
Most computers contain an RTC device which also contains battery-backed RAM represented as a linear array of bytes. There is a standard mechanism for accessing the first 64 bytes of non-volatile RAM in devices that are compatible with the Motorola RTC/CMOS device that was in the IBM PC/AT. Newer devices usually contain at least 128 bytes of battery-backed RAM. New PNP IDs were assigned for these devices.
Certain bytes within the battery-backed RAM have pre-defined values. In particular, the time, date, month, year, century, alarm time and RTC periodic interrupt are read-only.
9.16.1 PC/AT-compatible RTC/CMOS Devices (PNP0B00)
The standard PC/AT-compatible RTC/CMOS device is denoted by the PnP ID PNP0B00 an ACPI platform uses a device that is compatible with this device, it may describe this in its ACPI namespace. ASL may then read and write this as a linear 64-byte array. If PNP0B00 is used, ASL and ACPI operating systems may not assume that any extensions to the CMOS exist.
Note: This means that the CENTURY field in the Fixed ACPI Description Table may only contain values between 0 and 63.
This is an example of how this device could be described:
Device (RTC0) {
    Name(_HID, EISAID("PNP0B00"))

Name   (_FIX, Package(1) {
EISAID("PNP0B00") }
)
Name(_CRS, ResourceTemplate() {
   IO(Decode16, 0x70, 0x70, 0x1, 0x2)
}

    OperationRegion(CMS1, CMOS, 0, 0x40)

    Field(CMS1, ByteAcc, NoLock, Preserve) {
        AccessAs(ByteAcc, 0),
        CM00, 8,
        ,256,
        CM01, 8,
        CM02, 16,
        , 216,
        CM03, 8
    }
9.16.2 Intel PIIX4-compatible RTC/CMOS Devices (PNP0B01)
The Intel PIIX4 contains an RTC/CMOS device that is compatible with the one in the PC/AT. But it contains 256 bytes of non-volatile RAM. The first 64 bytes are accessed via the same mechanism as the 64 bytes in the PC/AT. The upper 192 bytes are accessed through an interface that is only used on Intel chips. (See 82371AB PCI-TO-ISA / IDEXCELERATOR (PIIX4) for details.)
Any platform containing this device or one that is compatible with it may use the PNP ID PNP0B01. This will allow an ACPI-compatible OS to recognize the RTC/CMOS device as using the programming interface of the PIIX4. Thus, the array of bytes that ASL can read and write with this device is 256 bytes long.
Note: This also means that the CENTURY field in the Fixed ACPI Description Table may contain values between 0 and 255.
This is an example of how this device could be described:

Device (RTC0) {
    Name(_HID, EISAID("PNP0B01"))

Name   (_FIX, Package(1) {
EISAID("PNP0B01") }
)
    Name(_CRS, ResourceTemplate() {
        IO(Decode16, 0x70, 0x70, 0x1, 0x2)
        IO(Decode16, 0x72, 0x72, 0x1, 0x2)
    }

    OperationRegion(CMS1, CMOS, 0, 0x100)

    Field(CMS1, ByteAcc, NoLock, Preserve) {
        AccessAs(ByteAcc, 0),
        CM00, 8,
        ,256,
        CM01, 8,
        CM02, 16,
        , 224,
        CM03, 8,
        , 184,
        CENT, 8
    }
9.16.3 Dallas Semiconductor-compatible RTC/CMOS Devices (PNP0B02)
Dallas Semiconductor RTC/CMOS devices are compatible with the one in the PC/AT, but they contain 256 bytes of non-volatile RAM or more. The first 64 bytes are accessed via the same mechanism as the 64 bytes in the PC/AT. The upper bytes are accessed through an interface that is only used on Dallas Semiconductor chips.
Any platform containing this device or one that is compatible with it may use the PNP ID PNP0B02. This will allow an ACPI-compatible OS to recognize the RTC/CMOS device as using the Dallas Semiconductor programming interface. Thus, the array of bytes that ASL can read and write with this device is 256 bytes long.
Description of these devices is similar to the PIIX4 example above, and the CENTURY field of the FADT may also contain values between 0 and 255.
9.17   Control Method User Presence Detection Device
The following section illustrates the operation and definition of the Control Method User Presence Detection (UPD) device.
The user presence detection device can optionally support power management objects (e.g. _PS0, _PS3) to allow the OS to manage the device's power consumption.
The Plug and Play ID of an ACPI control method user presence detection device is ACPI0009.

Table 9-9: Control Method User Presence Detection Device

Object	Description
_UPD	The current user presence detection reading. [Required]
_UPP	User presence detection polling frequency in tenths of seconds. [Optional]

9.17.1 _UPD (User Presence Detect)

This control method returns the user presence detection reading, indicating whether or not the user is currently present from the perspective of this sensor. Three states are currently defined for UPD sensor readings: absent, present, and unknown, represented by the values 0x00, 0x01, and 0xFF respectively. The unknown state is used to convey that the sensor is currently unable to determine user presence due to some environmental or other transient factor. All other values are reserved.
Arguments:
None
Result Code:
0x00: Absent:A user is not currently detected by this sensor.

0x01:          Present:A user is currently detected by this sensor.
0xFF:          Unknown: The sensor is currently unable to determine if a user is present or absent.
9.17.2   _UPP (User Presence Polling)
This optional object evaluates to a recommended polling frequency (in tenths of seconds) for this user presence sensor. A value of zero – or the absence of this object when other UPD objects are defined – indicates that the OS does not need to poll the sensor in order to detect meaningful changes in user presence (the hardware is capable of generating asynchronous notifications).
The use of polling is allowed but strongly discouraged by this specification. OEMs should design systems that asynchronously notify OSPM whenever a meaningful change in user presence occurs—relieving the OS of the overhead associated with polling.
This value is specified as tenths of seconds. For example, a value of 10 would be used to indicate a 1 second polling frequency. As this is a recommended value, OSPM will consider other factors when determining the actual polling frequency to use.
Arguments:
None
Result Code:
Zero:                       Polling by the OS is not required.
All other values:        The recommended polling frequency, in tenths of seconds.
9.17.3 User Presence Sensor Events

To communicate changes in user presence to OSPM, AML code should issue a Notify style=';font-family:"Courier New"'>(upd_device, 0x80) > whenever a change in user presence has occurred. The OS receives this notification and calls the _UPD control method to determine the current user presence status.
UPD notifications should be generated whenever a transition occurs between one of the user presence states (absent, present, or unknown) – but at a level of granularity that provides an appropriate response without overly taxing the system with unnecessary interrupts.
9.18 I/O APIC Device
This optional device describes a discrete I/O APIC device that is not bus enumerated (e.g., as a PCI device). Describing such a device in the ACPI name space is only necessary if hot plug of this device is supported. If hot plug of this device is not supported, an MADT I/O APIC (section 5.2.11.6,"I/O APIC") entry or I/O SAPIC (section 5.2.11.12, "I/O SAPIC Structure") entry is sufficient to describe this device.
An I/O APIC device is an I/O unit that complies with either of the APIC interrupt models supported by ACPI. These interrupt models are described Section 5.2.11.6,"I/O APIC" and Section 5.2.11.12,"I/O SAPIC Structure". If the device is an I/O unit that complies with the APIC interrupt model, it is declared using the ACPI000A identifier. If this device is an I/O unit that complies with the SAPIC interrupt model, it is declared using the ACPI000B identifier. If this device complies with both the APIC and SAPIC interrupt models (I/OxAPIC), it is declared using the ACPI0009 identifier.
An I/O APIC device declared using any of the above identifiers must contain a _GSB object as defined in Section 6.2.5, "_GSB (Global System Interrupt Base)" to report its Global System Interrupt Base. It must also contain a _CRS object that reports the base address of the I/O APIC device. The _CRS object is required to contain only one resource, a memory resource pointing to the I/O APIC register base.
Note: because the _CRS and _GSB methods provide sufficient information, it is not necessary to provide _MAT under an I/O APIC device.
For an I/O APIC device that is described both in the MADT and in the name space, the base address described in the MADT entry must be the same as the base address in the IO APIC device _CRS at boot time. OSPM must use the information from the MADT until such a time as the _CRS and _GSB methods in the name space device can be processed. At this point OSPM must ignore the MADT entry.

10   Power Source Devices
This section specifies the battery and AC adapter device objects OSPM uses to manage power resources.
A battery device is required to either have a Smart Battery subsystem or a Control Method Battery interface as described in this section. OSPM is required to be able to connect and manage a battery on either of these interfaces. This section describes these interfaces.
In the case of a compatible ACPI Smart Battery Table, the Definition Block needs to include a Bus/Device package for the SMB-HC. This will install an OS-specific driver for the SMBus, which in turn will locate the components of the Smart Battery subsystem. In addition to the battery or batteries, the Smart Battery subsystem includes a charger and a manager device to handle subsystems with multiple batteries.
The Smart Battery System Manager is one implementation of a manager device that is capable of arbitrating among the available power sources (AC power and batteries) for a system. It provides a superset of the Smart Battery Selector functionality, such as safely responding to power events (AC versus battery power), inserting and removing batteries and notifying the OS of all such changes. Additionally, the Smart Battery System Manager is capable of handling configurations including simultaneous charging and discharging of multiple batteries. Unlike the Smart Battery Selector that shares responsibility for configuring the battery system with OSPM, the Smart Battery System Manager alone controls the safe configuration of the battery system and simply issues status changes to OSPM when the configuration changes. Smart Battery System Manager is the recommended solution for handling multiple-battery systems.
10.1   Smart Battery Subsystems
The Smart Battery subsystem is defined by the:
·       System Management Bus Specification (SMBS)
·       Smart Battery Data Specification (SBDS)
·       Smart Battery Charger Specification (SBCS)
·       Smart Battery System Manager Specification (SBSM)
·       Smart Battery Selector Specification (SBSS)
An ACPI-compatible Smart Battery subsystem consists of:
·       An SMB-HC (CPU to SMB-HC) interface
·       At least one Smart Battery
·       A Smart Battery Charger
·       Either a Smart Battery System Manager or a Smart Battery Selector if more than one Smart Battery is supported
In such a subsystem, a standard way of communicating with a Smart Battery and Smart Battery Charger is through the SMBus physical protocols. The Smart Battery System Manager or Smart Battery Selector provides event notification (battery insertion/removal, and so on) and charger SMBus routing capability for any Smart Battery subsystem. A typical Smart Battery subsystem is illustrated below:

Figure 10-1 Typical Smart Battery Subsystem (SBS)
SMBus defines a fixed 7-bit slave address per device. This means that all batteries in the system have the same address (defined to be 0xB). The slave addresses associated with Smart Battery subsystem components are shown in the following table.
Table 10-1 Example SMBus Device Slave Addresses

SMBus Device Description	SMBus Slave Address (A0-A6)
SMBus Host Slave Interface	0x8
Smart Battery Charger/Charger Selector or Charger System Manager	0x9
Smart Battery System Manager or Smart Battery Selector	0xA
Smart Battery	0xB

Each SMBus device has up to 256 registers that are addressed through the SMBus protocol's Command value. SMBus devices are addressed by providing the slave address with the desired register's Command value. Each SMBus register can have non-linear registers; that is, command register 1 can have a 32-byte string, while command register 2 can have a byte, and command register 3 can have a word.
The SMBus host slave interface provides a standard mechanism for the host CPU to generate SMBus protocol commands that are required to communicate with SMBus devices (in other words, the Smart Battery components). ACPI defines such an SMB-HC that resides in embedded controller address space; however, an OS can support any SMB-HC that has a native SMB-HC device driver.

The Smart Battery System Manager provides a standard programming model to control multiple Smart Batteries in a Smart Battery subsystem. A Smart Battery System Manager provides the following types of battery management functions:
·       Event notification for battery insertion and removal
·       Event notification for AC power connected or disconnected
·       Status of which Smart Battery is communicating with the SMB-HC
·       Status of which Smart Battery(s) are powering the system
·       Status of which Smart Battery(s) are connected to the charger
·       Status of which Smart Batteries are present in the system
·       Event notification when the Smart Battery System Manager switches from one power source to another
·       Hardware-switching to an alternate Smart Battery when the Smart Battery supplying power runs low
·       Hardware switching between battery-powered and AC-powered powered operation
The Smart Battery System Manager function can reside in a standalone SMBus slave device (Smart Battery System Manager that responds to the 0xA slave address), may be present within a smart charger device (Smart Battery Charger that responds to the 0x9 slave address), or may be combined within the embedded controller (that responds to the 0xA slave address) both a Smart Battery Charger and a standalone Smart Battery System Manager are present in the same Smart Battery subsystem, then the driver assumes that the standalone Smart Battery System Manager is wired to the batteries.
The Smart Battery charger is an SMBus device that provides a standard programming model to control the charging of Smart Batteries present in a Smart Battery subsystem. For single battery systems, the Smart Battery Charger is also responsible for notifying the system of the battery and AC status.
The Smart Battery provides intelligent chemistry-independent power to the system. The Smart Battery is capable of informing the Smart Battery charger of its charging requirements (which provides chemistry independence) and providing battery status and alarm features needed for platform battery management.
10.1.1   ACPI Smart Battery Status Change Notification Requirements
The Smart Battery System Manager, the Smart Battery Selector, and the Smart Battery Charger each have an optional mechanism for notifying the system that the battery configuration or AC status has changed. ACPI requires that this interrupt mechanism be through the SMBus Alarm Notify mechanism.
For systems using an embedded controller as the SMBus host, a battery system device issues a status change notification by either mastering the SMBus to send the notification directly to the SMBus host, or by emulating it in the embedded controller. In either case, the process is the same. After the notification is received or emulated, the embedded controller asserts an SCI. The source of the SCI is identified by a GPE that indicates the SCI was caused by the embedded controller. The embedded controller's status register alarm bit is set, indicating that the SMBus host received an alarm message Alarm Address Register contains the address of the SMBus device that originated the alarm and the Alarm Data Registers contain the contents of that device's status register.

10.1.1.1   Smart Battery Charger
This requires a Smart Battery Charger, on a battery or AC status change, to generate an SMBus Alarm Notify. The contents of the Smart Battery Charger's ChargerStatus() command register (0x13) is placed in the embedded controller's Alarm Data Registers, the Smart Battery Charger's slave address[14] (0x09) is placed in the embedded controller's Alarm Address Register and the EC's Status Register's Alarm bit is set. The embedded controller then asserts an SCI.
10.1.1.2   Smart Battery Charger with optional System Manager or Selector
A Smart Battery Charger that contains the optional System Manager or Selector function (as indicated by the ChargerSpecInfo() command register, 0x11, bit 4) is required to generate an SMBus Alarm Notify on a battery or AC status change. The content of the Smart Battery Charger with an optional System Manager, the BatterySystemState() command register (0x21) (or in the case of an optional Selector, the SelectorState() (0x01) ), is placed in the EC's Alarm Data Registers, the Smart Battery Charger's slave address (0x09) is placed in the embedded controller's Alarm Address Register, and the embedded controller's Status Register's Alarm bit is set. The embedded controller then asserts an SCI.
10.1.1.3   Smart Battery System Manager
The Smart Battery System Manager is required to generate an SMBus Alarm Notify on a battery or AC status change. The content of the Smart Battery System Manager's BatterySystemState() command register (0x01) is placed in the EC's Alarm Data Registers, the Smart Battery System Manager's slave address (0x0A) is placed in the EC's Alarm Address Register, and the embedded controller's Status Register's Alarm bit is set. The embedded controller then asserts an SCI.
10.1.1.4   Smart Battery Selector
The requirements for the Smart Battery Selector are the same as the requirements for the Smart Battery System Manager, with the exception that the contents of the SelectorState() command register (0x01) are used instead of BatterySystemState(). The Smart Battery Selector is a subset of the Smart Battery System Manager and does not have the added support for simultaneous charge/discharge of multiple batteries. The System Manager is the preferred implementation.

10.1.2 Smart Battery Objects
The Smart Battery subsystem requires a number of objects to define its interface. These are summarized below:
Table 10-2 Smart Battery Objects

Object

Description

_HID

This is the hardware ID named object that contains a string. For Smart Battery subsystems, this object returns the value of "ACPI0002." This identifies the Smart Battery subsystem to the Smart Battery driver.

_SBS

This is the Smart Battery named object that contains a DWORD. This named object returns the configuration of the Smart Battery subsystem and is encoded as follows:

0 – Maximum of one Smart Battery and no Smart Battery System Manager or Smart Battery Selector.

1 – Maximum of one Smart Battery and a Smart Battery System Manager or Smart Battery Selector.

2 – Maximum of two Smart Batteries and a Smart Battery System Manager or Smart Battery Selector.

3 – Maximum of three Smart Batteries and a Smart Battery System Manager or Smart Battery Selector.

4 – Maximum of four Smart Batteries and a Smart Battery System Manager or Smart Battery Selector.

The maximum number of batteries is for the system. Therefore, if the platform is capable of supporting four batteries, but only two are normally present in the system, then this field should return 4. Notice that a value of 0 indicates a maximum support of one battery and there is no Smart Battery System Manager or Smart Battery Selector present in the system.

10.1.3 Smart Battery Subsystem Control Methods
As the SMBus is not an enumerable bus, all devices on the bus must be declared in the ACPI name space. As the Smart Battery driver understands Smart Battery, Smart Battery Charger, and Smart Battery System Manager or Smart Battery Selector; only a single device needs to be declared per Smart Battery subsystem. The driver gets information about the subsystem through the hardware ID (which defines a Smart Battery subsystem) and the number of Smart Batteries supported on this subsystem (_SBS named object) ACPI Smart Battery table indicates the energy levels of the platform at which the system should warn the user and then enter a sleeping state. The Smart Battery driver then reflects these as threshold alarms for the Smart Batteries.
The _SBS control method returns the configuration of the Smart Battery subsystem. This named object returns a DWORD value with a number from 0 to 4. If the number of batteries is greater than 0, then the Smart Battery driver assumes that a Smart Battery System Manager or Smart Battery Selector is present. If 0, then the Smart Battery driver assumes a single Smart Battery and neither a Smart Battery System Manager nor Smart Battery Selector is present.
A Smart Battery device declaration in the ACPI name space requires the _GLK object if potentially contentious accesses to device resources are performed by non-OS code. See section 6.5.7, "_GLK (Global Lock)," for details about the _GLK object.
10.1.3.1 Example: Single Smart Battery Subsystem
This section illustrates how to define a Smart Battery subsystem containing a single Smart Battery and charger. The platform implementation is illustrated below:

Figure 10-2   Single Smart Battery Subsystem
In this example, the platform is using an SMB-HC that resides within the embedded controller and meets the ACPI standard for an embedded controller interface and SMB-HC interface. The embedded controller interface sits at system I/O port addresses 0x62 and 0x66. The SMB-HC is at base address 0x80 within embedded controller address space (as defined by the ACPI embedded controller specification) and responds to events on query value 0x30.
In this example the Smart Battery subsystem only supports a single Smart Battery. The ASL code for describing this interface is shown below:

Device (EC0) {
    Name (_HID, EISAID("PNP0C09"))
    Name (_CRS,
       ResourceTemplate () {               // port 0x62 and 0x66
           IO (Decode16, 0x62, 0x62, 0, 1),
           IO (Decode16, 0x66, 0x66, 0, 1)

       }
    )
    Name (_GPE, 0)
    Device (SMB0) {
       Name (_HID, "ACPI0001")         // Smart Battery Host Controller
       Name (_EC, 0x8030)                  // EC offset (0x80), Query (0x30)
       Device (SBS0){                  // Smart Battery Subsystem
           Name (_HID, "ACPI0002")     // Smart Battery Subsystem ID
           Name(_SBS, 0x1)              // Indicates support for one battery
       } // end of SBS0
    } // end of SMB0
} // end of EC
10.1.3.2   Multiple Smart Battery Subsystem: Example
This section illustrates how to define a Smart Battery subsystem that contains three Smart Batteries, a Smart Battery System Manager, and a Smart Battery Charger. The platform implementation is illustrated below:

Figure 10-3   Smart Battery Subsystem
In this example, the platform is using an SMB-HC that resides within the embedded controller and meets the ACPI standard for an embedded controller interface and SMB-HC interface. The embedded controller interface sits at system I/O port addresses 0x100 and 0x101. The SMB-HC resides at base address 0x90 within embedded controller address space (as defined by the ACPI embedded controller specification) and responds to events on query value 0x31.
In this example the Smart Battery subsystem supports three Smart Batteries. The Smart Battery Charger and Smart Battery System Manager reside within the embedded controller, meet the Smart Battery System Manager and Smart Battery Charger interface specification, and respond to their 7-bit addresses (0xA and 0x9 respectively). The ASL code for describing this interface is shown below:
Device (EC1) {
    Name (_HID, EISAID("PNP0C09"))
    Name (_CRS,
       ResourceTemplate () {               // port 0x100 and 0x101
           IO(Decode16, 0x100, 0x100, 0, 2)
       }
    )
    Name (_GPE, 1)
    Device (SMB1) {
       Name (_HID, "ACPI0001")          // Smart Battery Host Controller
       Name (_EC, 0x9031)                  // EC offset (0x90), Query (0x31)
       Device (SBS1){                  // Smart Battery Subsystem
           Name (_HID, "ACPI0002")     // Smart Battery Subsystem ID
           Name (_SBS, 0x3)             // Indicates support for three batteries
       } // end of SBS1
    } // end of SMB1
} // end of EC
10.2   Control Method Batteries
The following section illustrates the operation and definition of the Control Method Battery.
10.2.1   Battery Events
The AML code handling an SCI for a battery event notifies the system of which battery's status may have changed. The OS uses the _BST control method to determine the current status of the batteries and what action, if any, should be taken (for more information about the _BST control method, see section 10.2.2, "Battery Control Methods"). The typical action is to notify applications monitoring the battery status to provide the user with an up-to-date display of the system battery state. But in some cases, the action may involve generating an alert or even forcing a system into a sleeping state. In any case, any changes in battery status should generate an SCI in a timely manner to keep the system power state UI consistent with the actual state of the system battery (or batteries).
Unlike most other devices, when a battery is inserted or removed from the system, the device itself (the battery bay) is still considered to be present in the system. For most systems, the _STA for this device will always return a value with bits 0-3 set and will toggle bit 4 to indicate the actual presence of a battery (see section 6.3.7, "_STA [Status]"). When this insertion or removal occurs, the AML code handler for this event should issue a Notify(battery_device, 0x81) to indicate that the static battery information has changed. For systems that have battery slots in a docking station or batteries that cannot be surprise-removed, it may be beneficial or necessary to indicate that the entire device has been removed. In this case, the standard methods and notifications described in section 6.3, "Device Insertion, Removal, and Status Objects," should be used.
When the present state of the battery has changed or when the trip point set by the _BTP control method is reached or crossed, the hardware will assert a general purpose event. The AML code handler for this event issues a Notify(battery_device, 0x80) on the battery device. This notification is also sent when the Status Flags returned from _BMD change.
In the case where the remaining battery capacity becomes critically low, the AML code handler issues a Notify(battery_device, 0x80) and reports the battery critical flag in the _BST object. The OS performs an emergency shutdown. For a full description of the critical battery state, see section 3.9.4, "Low Battery Levels."
Sometimes the value to be returned from _BST or _BIF will be temporarily unknown. In this case, the method may return the value 0xFFFFFFFF as a placeholder. When the value becomes known, the appropriate notification (0x80 for _BST or 0x81 for BIF) should be issued, in like manner to any other change in the data returned by these methods. This will cause OSPM to re-evaluate the method—obtaining the correct data value.
When one or more of the status flags returned by the _BMD control method change, AML code issues a Notify(battery_device, 0x82) on the battery device unless this change occurs during a call to _BMC and the value of the status flags in _BMD match the value passed in to _BMC. If the value of the status bits cannot be set to reflect the action requested by the executing _BMC, the AML code will issue this notification. For example, calling _BMC with bit 0 set to initiate a calibration cycle while AC power is not available will cause AML to issue a Notify(battery_device, 0x82).

10.2.2 Battery Control Methods
The Control Method Battery is a battery with an AML code interface between the battery and the host PC. The battery interface is completely accessed by AML code control methods, allowing the OEM to use any type of battery and any kind of communication interface supported by ACPI. OSPM requires accurate battery data to perform optimal power management policy and to provide the end user with a meaningful estimation of remaining battery life. As such, control methods that return battery information should calculate this information rather than return hard coded data.
A Control Method Battery is described as a device object. Each device object supporting the Control Method Battery interface contains the following additional control methods. When there are two or more batteries in the system, each battery will have an independent device object in the name space.
Table 10-3 Battery Control Methods

Object	Description
_BIF	Returns static information about a battery (in other words, model number, serial number, design voltage, and so on).
_OSC	OSPM Capabilities conveyance for batteries.
_BST	Returns the current battery status (in other words, dynamic information about the battery, such as whether the battery is currently charging or discharging, an estimate of the remaining battery capacity, and so on).
_BTP	Sets the Battery Trip point, which generates an SCI when batterycapacity reaches the specified point.
_PCL	List of pointers to the device objects representing devices powered by the battery.
_STA	Returns general status of the battery (for a description of the _STA control method, see section 6.3.7, "_STA (Status]").
_BTM	Returns estimated runtime at the present average rate of drain, or the runtime at a specified rate.
_BMD	Returns battery information related to battery recalibration and charging control.
_BMC	Control calibration and charging

A Control Method Battery device declaration in the ACPI name space requires the _GLK object if potentially contentious accesses to device resources are performed by non-OS code. See section 6.5.7, "_GLK (Global Lock)," for details about the _GLK object.
10.2.2.1   _BIF (Battery Information)
This object returns the static portion of the Control Method Battery information. This information remains constant until the battery is changed.
Arguments:
None
Result Code:

Package {
    // ASCIIZ is ASCII character string terminated with a 0x00.
    Power Unit                      //DWORD
    Design Capacity                 //DWORD
    Last Full Charge Capacity           //DWORD
    Battery Technology                  //DWORD
    Design Voltage                  //DWORD
    Design Capacity of Warning          //DWORD
    Design Capacity of Low              //DWORD
    Battery Capacity Granularity 1 //DWORD
    Battery Capacity Granularity 2 //DWORD
    Model Number                    //ASCIIZ
    Serial Number                   //ASCIIZ
    Battery Type                    //ASCIIZ
    OEM Information                 //ASCIIZ
}

Table 10-4 _BIF Method Result Codes

Field	Format	Description
Power Unit	DWORD	Indicates the units used by the battery to report its capacity and charge/discharge rate information to the OS. 0x00000000 – Capacity information is reported in [mWh] and charge/discharge rate information in [mW]. 0x00000001 – Capacity information is reported in [mAh] and charge/discharge rate information in [mA].
Design Capacity	DWORD	Battery's design capacity. Design Capacity is the nominal capacity of a new battery. The Design Capacity value is expressed as power [mWh] or current [mAh] depending on the Power Unit value. 0x000000000 – 0x7FFFFFFF (in [mWh] or [mAh] ) 0xFFFFFFFF – Unknown design capacity
Last Full Charge Capacity	DWORD	Predicted battery capacity when fully charged. The Last Full Charge Capacity value is expressed as power (mWh) or current (mAh) depending on the Power Unit value. 0x000000000h – 0x7FFFFFFF (in [mWh] or [mAh] ) 0xFFFFFFFF – Unknown last full charge capacity
Battery Technology	DWORD	0x00000000 – Primary (for example, non-rechargeable) 0x00000001 – Secondary (for example, rechargeable)
Design Voltage	DWORD	Nominal voltage of a new battery. 0x000000000 – 0x7FFFFFFF in [mV] 0xFFFFFFFF – Unknown design voltage
Design capacity of Warning	DWORD	OEM-designed battery warning capacity. See section 3.9.4, "Low Battery Levels." 0x000000000 – 0x7FFFFFFF in [mWh] or [mAh]
Design Capacity of Low	DWORD	OEM-designed low battery capacity. See section 3.9.4, "Low Battery Levels." 0x000000000 – 0x7FFFFFFF in [mWh] or [mAh]
Battery Capacity Granularity 1	DWORD	Battery capacity granularity between low and warning in [mAh] or [mWh]. That is, this is the smallest increment in capacity that the battery is capable of measuring. See note below for more details
Battery Capacity Granularity 2	DWORD	Battery capacity granularity between warning and Full in [mAh] or [mWh]. That is, this is the smallest increment in capacity that the battery is capable of measuring. This may be a different value than Battery Capacity Granularity 1 to accommodate systems where the granularity accuracy may change depending on the battery level. See note below for more details.
Model Number	ASCIIZ	OEM-specific Control Method Battery model number
Serial Number	ASCIIZ	OEM-specific Control Method Battery serial number
Battery Type	ASCIIZ	The OEM-specific Control Method Battery type
OEM Information	ASCIIZ	OEM-specific information for the battery that the UI uses to display the OEM information about the Battery. If the OEM does not support this information, this should be reserved as 0x00.

Notes:

·         A secondary-type battery should report the corresponding capacity (except for Unknown).
·         On a multiple-battery system, all batteries in the system should return the same granularity.
·         Operating systems prefer these control methods to report data in terms of power (watts).
·         On a multiple-battery system, all batteries in the system must use the same power unit.
·         The definition of battery capacity granularity has been clarified. For OSPM to determine if systems support the clarified definition of battery capacity granularity, OSPM may evaluate an _OSC method at the battery scope to indicate support for this capability, and for the platform to indicate if it supports these extended capabilities.

10.2.2.2 _OSC Definition for Control Method Battery
_OSC for control method battery is uniquely identified by the UUID: f18fc78b-0f15-4978-b793-53f833a1d35b
The Revision 1 capabilities described under this _OSC are defined in Table 10-5.
Table 10-5   Control Method Battery _OSC Capabilities DWORD2 Bit Definitions

Capabilities DWORD2 bits	Interpretation
0	0 - OS does not support revised battery granularity definition. 1 - OS supports revised battery granularity definition.
1	0 - OS does not support specifying wake on low battery user preference. 1 - OS supports specifying wake on low battery user preference, See section 9.1.3, "_BLT Battery Level Threshold) for more information.
2-31	Reserved

Bits defined in Capabilities DWORD2 provide information regarding OS supported features. Contents in DWORD2 are passed one-way; the OS will disregard the corresponding bits of DWORD2 in the Return Code.
10.2.2.3   _BST (Battery Status)
This object returns the present battery status. Whenever the Battery State value changes, the system will generate an SCI to notify the OS.
Arguments:
None
Result Code:

Package {
    Battery State                //DWORD
    Battery Present Rate         //DWORD
    Battery Remaining Capacity      //DWORD
    Battery Present Voltage      //DWORD
}
Table 10-6   _BST Method Result Codes

Field	Format	Description
Battery State	DWORD	Bit values. Notice that the Charging bit and the Discharging style='font-style:normal'> bit are mutually exclusive and must not both be set at the same time. Even in critical state, hardware should report the corresponding charging/discharging state. Bit0 – 1 indicates the battery is discharging. Bit1 – 1 indicates the battery is charging. Bit2 – 1 indicates the battery is in the critical energy state (see section 3.9.4, "Low Battery Levels"). This does not mean battery failure.
Battery Present Rate	DWORD	Returns the power or current being supplied or accepted through the battery's terminals (direction depends on the Battery State value). The Battery Present Rate style='font-style:normal'> value is expressed as power [mWh] or current [mAh] depending on the Power Unit value. Batteries that are rechargeable and are in the discharging state are required to return a valid Battery Present Rate value. 0x00000000 – 0x7FFFFFFF in [mW] or [mA] 0xFFFFFFFF – Unknown rate
Battery Remaining Capacity	DWORD	Returns the estimated remaining battery capacity. The Battery Remaining Capacity value is expressed as power [mWh] or current [mAh] depending on the Power Unit value. Batteries that are rechargeable are required to return a valid Battery Remaining Capacity value. 0x00000000 – 0x7FFFFFFF in [mWh] or [mAh] 0xFFFFFFFF – Unknown capacity
Battery Present Voltage	DWORD	Returns the voltage across the battery's terminals. Batteries that are rechargeable must report Battery Present Voltage. 0x000000000 – 0x7FFFFFFF in [mV] 0xFFFFFFFF – Unknown voltage Note: Only a primary battery can report unknown voltage.

Notice that when the battery is a primary battery (a non-rechargeable battery such as an Alkaline-Manganese battery) and cannot provide accurate information about the battery to use in the calculation of the remaining battery life, the Control Method Battery can report the percentage directly to OS. It does so by reporting the Last Full Charged Capacity =100 and BatteryPresentRate=0xFFFFFFFF. This means that Battery Remaining Capacity directly reports the battery's remaining capacity [%] as a value in the range 0 through 100 as follows:

10.2.2.4 _BTP (Battery Trip Point)
This object is used to set a trip point to generate an SCI whenever the Battery Remaining Capacity reaches or crosses the value specified in the _BTP object. Specifically, if Battery Remaining Capacity is less than the last argument passed to _BTP, a notification must be issued when the value of Battery Remaining Capacity rises to be greater than or equal to this trip-point value. Similarly, if Battery Remaining Capacity is greater than the last argument passed to _BTP, a notification must be issued when the value of Battery Remaining Capacity falls to be less than or equal to this trip-point value. The last argument passed to _BTP will be kept by the system.

If the battery does not support this function, the _BTP control method is not located in the name space. In this case, the OS must poll the Battery Remaining Capacity value.
Arguments:
Level at which to set the trip point:
0x00000001 – 0x7FFFFFFF (in units of mWh or mAh, depending on the Power Units value)
0x00000000 – Clear the trip point
Result Code:
None
10.2.2.5   _BTM (Battery Time)
This optional object returns the estimated runtime of the battery while it is discharging.
Arguments:
Rate at which the battery is expected to discharge:
0x00000000 – indicates that the battery will continue discharging at the current rate. The rate should be based on the average rate of drain, not the current rate of drain.
0x00000001 – 0x7FFFFFFF – the rate (in mA or mW).
Result Code:
0x00000000 – Specified rate is too large for batteries to supply. If the argument was 0x00000000, _BTM should only return 0x00000000 if the battery is critical.
0x00000001 – 0xFFFFFFFE – Estimated runtime in seconds.
0xFFFFFFFF – Runtime is unknown.
10.2.2.6   _BMD (Battery Maintenance Data)
This optional object returns information about the battery's capabilities and current state in relation to battery calibration and charger control features. If the _BMC object (defined below) is present under a battery device, this object must also be present. Whenever the Status Flags value changes, AML code will issue a Notify(battery_device, 0x82). In addition, AML will issue a Notify(battery_device style='font-style:normal'>, 0x82) if evaluating _BMC did not result in causing the Status Flags to be set as indicated in that argument to _BMC. AML is not required to issue Notify(battery_device, 0x82) if the Status Flags style='font-style:normal'> change while evaluating _BMC unless the change does not correspond to the argument passed to _BMC..
Arguments:
None
Result Code:

Package {Status Flags               //DWORD
        Capability Flags             //DWORD
        Recalibrate Count            //DWORD
        Quick Recalibrate Time          //DWORD
        Slow Recalibrate Time        //DWORD}

Table 10-7   _BMD Method Result Codes

Field	Format	Description
Status Flags	DWORD	Bit values. Bit0 is mutually exclusive with Bit1 and Bit2. If the charger is being manually controlled, there cannot be an AML controlled calibration cycle. Bit0 – 1 indicates the battery is running an AML controlled calibration cycle Bit1 – 1 indicates that charging has been disabled. Bit2 – 1 indicates the battery is configured to discharge while AC power is available. Bit3 – 1 indicates that the battery should be recalibrated. Bit4 – 1 indicates that the OS should put the system into standby to speed charging during a calibration cycle. This is optional (based on user preference) if "Slow Recalibrate Time" is not equal to 0x00000000. Bit5 – Bit31 – reserved.
Capability Flags	DWORD	Bit values that describe the capabilities of the battery system. These bits allows a battery system with more limited capabilities to still be calibrated by OSPM. Bit0 – 1 indicates that an AML controlled calibration cycle is supported. Bit1 – 1 indicates that disabling the charger is supported. Bit2 – 1 indicates that discharging while running on AC is supported. Bit3 – 1 indicates that calling _BMC for one battery will affect the state of all batteries in the system. This is for battery systems that cannot control batteries individually. Bit4 – 1 indicates that calibration should be done by first fully charging the battery and then discharging it. Not setting this bit will indicate that calibration can be done by simply discharging the battery. Bit4 – Bit31 – reserved.
Recalibrate Count	DWORD	This is used by battery systems that can't detect when calibration is required, but wish to recommend that the battery should be calibrated after a certain number of cycles. Counting the number of cycles and partial cycles is done by the OS. 0x00000000 – Only calibrate when Status Flag bit 3 is set. 0x00000000 – 0xFFFFFFFF – calibrate battery after detecting this many battery cycles.
Quick Recalibrate Time	DWORD	Returns the estimated time it will take to calibrate the battery if the system is put into standby whenever Status Flags Bit4 is set. While the AML controlled calibration cycle is in progress, this returns the remaining time in the calibration cycle. 0x000000000 – indicates that standby while calibrating the battery is not supported. The system should remain in S0 until calibration is completed. 0x00000001 – 0xFFFFFFFE – estimated recalibration time in seconds. 0xFFFFFFFF – indicates that the estimated time to recalibrate the battery is unknown.
Slow Recalibrate Time	DWORD	Returns the estimated time it will take to calibrate the battery if Status Flag Bit4 is ignored. While the AML controlled calibration cycle is in progress, this returns the remaining time in the calibration cycle. 0x000000000 – indicates that battery calibration may not be successful if Status Flags Bit4 is ignored. 0x00000001 – 0xFFFFFFFE – estimated recalibration time in seconds. 0xFFFFFFFF – indicates that the estimated time to recalibrate the battery is unknown.

See section 3.9.5, "Battery Calibration" for an overview of Battery Calibration.
The Capability Flags and Recalibration Count are used to indicate what functions are controlled by AML and what functions are controlled by OSPM as described in section 3.9.5, "Battery Calibration" the system does not implement an AML controlled calibration cycle (bit 0), it may indicate using bit 1 and bit 2 that the OS can control a generic calibration cycle without prompting the user to remove the power cord. Recalibration Count may be used to indicate that the BIOS cannot determine when calibration should be preformed so bit 3 of the Status Flags will never be set. In that case, OSPM will attempt to count the number of cycles.
Bit3 is used by systems that do not have individual control over the batteries and can only perform calibration on all batteries in the system at once. On such a system, if one battery requests calibration and another battery does not, the OS may suggest that the user remove the battery that doesn't need calibration, before initiating the calibration cycle. When this bit is set, reading the Recalibrate Time from either battery should give the time to recalibrate all batteries present in the system.
10.2.2.7 _BMC (Battery Maintenance Control)
This object is used to initiate calibration cycles or to control the charger and whether or not a battery is powering the system. This object is only present under a battery device if the _BMD Capabilities Flags have bit 0, 1, or 2 set.

Arguments:
Flags indicating which features to enable:
Bit0 – Set to initiate an AML controlled calibration cycle. Clear to end the calibration cycle.
Bit1 – Set to disable charging. Clear to enable charging.
Bit2 – Set to allow the battery to discharge while AC power is available. Clear to prevent discharging while AC power is available.
Result Code:
None
See section 3.9.5 for an overview of Battery Calibration.
Evaluating this object with bit0 set will initiate an AML controlled recalibration cycle if _BMD indicates that this is supported. The calibration cycle is controlled by the platform and will typically include disabling the AC adapter and discharging the battery, then charging the battery. While the battery is charging, the BIOS should set Bit4 of the Status flags returned by _BMD if it is possible to put the system into standby during calibration to speed up charging. Evaluating this with Bit0 equal to 0 will abort the calibration cycle if one is in process. If the BIOS determines that the calibration cycle must be aborted (for example AC power is lost), or the calibration completes successfully, the BIOS will end the cycle automatically, clear the _BMD Status Flag Bit0, and send a notify 0x82. While the calibration cycle is in process, the battery will report data normally, so the OS must disable battery alarms.
Bit1 and Bit2 may not be used in conjunction with the AML controlled calibration cycle. Having Bit0 set will override Bit1 and Bit2. Bit1 will prevent the battery from charging even though AC power is connected. Bit2 will allow the system to draw its power from the battery even though AC power is available. When the battery is no longer capable of delivering current, this setting is automatically cleared, and the system will continue running off AC power without interruption. In addition, if AC power is lost this bit will be cleared. When AC power comes back, the OS must set the bit again if the user wants to continue discharging. When the system clears this bit automatically, it will result in a change in the Status Flags returned by _BMD. This will cause a notify 0x82. Bit1 is only cleared automatically if an AML controlled calibration cycle is initiated.
When a battery is discharging because Bit2 is set, the _PSR method of the AC adapter device will report that AC is offline because the system is not running off of the AC adapter. If the batteries are controlled individually (Bit3 of the _BMD Capabilities Flags), setting either battery to discharge will cause _PSR to report AC offline. If more than one battery in the system has Bit2 set to discharge the battery, it is up to the system to decide which battery to discharge, so only on a system that discharges the batteries one at a time, a battery with Bit2 set may not be discharging if another battery in the system is being discharged.
If Batteries are not controlled individually, calling _BMC will initiate calibration, disable charge, and/or allow discharge on all batteries in the system. The state of these batteries will be reflected in the _BMD Status Flags for all batteries.
10.3 AC Adapters and Power Source Objects
The Power Source objects describe the power source used to run the system.
Table 10-8 Power Source Control Methods

Object	Description
_PSR	Returns present power source device.
_PCL	List of pointers to powered devices.

10.3.1 _PSR (Power Source)
Returns the current power source devices. Used for the AC adapter and is located under the AC adapter object in name space. Used to determine if system is running off the AC adapter. This will report that the system is not running on the AC adapter if any of the batteries in the system is being forced to discharge through _BMC.
Arguments:
None
Result Code:
0x00000000 – Off-line
0x00000001 – On-line

10.3.2 _PCL (Power Consumer List)
This object evaluates to a list of pointers, each pointing to a device or a bus powered by the power source device. Pointing to a bus indicates that all devices under the bus are powered by the power source device.

10.4 Example: Power Source Name Space
The ACPI name space for a computer with an AC adapter and two batteries associated with a docking station that has an AC adapter and a battery is shown in Figure 10-4.

Figure 10-4 Power Source Name Space Example that Includes a Docking Station

11 Thermal Management
This section describes the ACPI thermal model and specifies the ACPI Namespace objects OSPM uses for thermal management of the platform.
11.1 Thermal Control
ACPI defines interfaces that allow OSPM to be proactive in its system cooling policies. With OSPM in control of the operating environment, cooling decisions can be made based on the system's application load, the user's preference towards performance or energy conservation, and thermal heuristics. Graceful shutdown of devices or the entire system at critical heat levels becomes possible as well. The following sections describe the ACPI thermal model and the ACPI Namespace objects available to OSPM to apply platform thermal management policy.
The ACPI thermal model is based around conceptual platform regions called thermal zones that physically contain devices, thermal sensors, and cooling controls. Generally speaking, the entire platform is one large thermal zone, but the platform can be partitioned into several ACPI thermal zones if necessary to enable optimal thermal management.
ACPI Thermal zones are a logical collection of interfaces to temperature sensors, trip points, thermal property information, and thermal controls. Thermal zone interfaces apply either thermal zone wide or to specific devices, including processors, contained within the thermal zone. ACPI defines namespace objects that provide the thermal zone-wide interfaces in section 11.3, "Thermal Objects". A subset of these objects may also be defined under devices. OS implementations compatible with the ACPI 3.0 thermal model, interface with these objects but also support OS native device driver interfaces that perform similar functions at the device level. This allows the integration of devices with embedded thermal sensors and controls, perhaps not accessible by AML, to participate in the ACPI thermal model through their inclusion in the ACPI thermal zone. OSPM is responsible for applying an appropriate thermal policy when a thermal zone contains both thermal objects and native OS device driver interfaces for thermal control.
Some devices in a thermal zone may be comparatively large producers of thermal load in relation to other devices in the thermal zone. Devices may also have varying degrees of thermal sensitivity. For example, some devices may tolerate operation at a significantly higher temperature than other devices. As such, the platform can provide OSPM with information about the platform's device topology and the resulting influence of one device's thermal load generation on another device. This information must be comprehended by OSPM for it to achieve optimal thermal management through the application of cooling controls.
ACPI expects all temperatures to be represented in tenths of degrees. This resolution is deemed sufficient to enable OSPM to perform robust platform thermal management.

Figure 11-1 ACPI Thermal Zone
11.1.1 Active, Passive, and Critical Policies
There are three cooling policies that OSPM uses to control the thermal state of the hardware. The policies are active, passive and critical.
· Active Cooling. OSPM takes a direct action such as turning on a fan. Applying active cooling controls typically consume power and produce some amount of noise, but are able to cool a thermal zone without limiting system performance. Active cooling temperature trip points declare the temperature thresholds OSPM uses to decide when to start or stop different active cooling devices.
· Passive Cooling. OSPM reduces the power consumption of devices to reduce the temperature of a thermal zone, such as slowing (throttling) the processor clock. Applying passive cooling controls typically produces no user-noticeable noise. Passive cooling temperature trip points specify the temperature thresholds where OSPM will start or stop passive cooling.
· Critical Trip Points. These are threshold temperatures at which OSPM performs an orderly, but critical, shutdown of a device or the entire system. The _HOT object declares the critical temperature at which OSPM may choose to transition the system into the S4 sleeping state, if supported, The _CRT object declares the critical temperature at which OSPM must perform a critical shutdown.
When a thermal zone appears in the ACPI Namespace or when a new device becomes a member of a thermal zone, OSPM retrieves the temperature thresholds (trip points) at which it executes a cooling policy. When OSPM receives a temperature change notification, it evaluates the thermal zone's temperature interfaces to retrieve current temperature values. OSPM compares the current temperature values against the temperature thresholds. If any temperature is greater than or equal to a corresponding active trip point then OSPM will turn on the associated active cooling device(s). If any temperature is greater than or equal to a corresponding passive trip point then OSPM will perform passive cooling. If the _TMP object returns a value greater than or equal to the value returned by the _HOT object then OSPM may choose to transition the system into the S4 sleeping state, if supported. If the _TMP object returns a value greater than or equal to the value returned by the _CRT object then OSPM must shut the system down. Embedded Hot and Critical trip points may also be exposed by individual devices within a thermal zone. Upon passing of these trip points, OSPM must decide whether to shut down the device or the entire system based upon device criticality to system operation. OSPM must also evaluate the thermal zone's temperature interfaces when any thermal zone appears in the namespace (for example, during system initialization) and must initiate a cooling policy as warranted independent of receipt of a temperature change notification. This allows OSPM to cool systems containing a thermal zone whose temperature has already exceeded temperature thresholds at initialization time.
An optimally designed system that uses several thresholds can notify OSPM of thermal increase or decrease by raising an event every several degrees. This enables OSPM to anticipate thermal trends and incorporate heuristics to better manage the system's temperature.
To implement a preference towards performance or energy conservation, OSPM can request that the platform change the priority of active cooling (performance) versus passive cooling (energy conservation/silence) by evaluating the _SCP (Set Cooling Policy) object for the thermal zone or a corresponding OS-specific interface to individual devices within a thermal zone.

11.1.2   Dynamically Changing Cooling Temperature Trip Points
The platform or its devices can change the active and passive cooling temperature trip points and notify OSPM to reevaluate the trip point interfaces to establish the new policy threshold settings. The following are the primary uses for this type of thermal notification:
· When OSPM changes the platform's cooling policy from one cooling mode to another.
· When a swappable bay device is inserted or removed. A swappable bay is a slot that can accommodate several different devices that have identical form factors, such as a CD-ROM drive, disk drive, and so on. Many mobile PCs have this concept already in place.
· After the crossing of an active or passive trip point is signaled to implement hysteresis.
In each situation, OSPM must be notified to re-evaluate the thermal zone's trip points via the AML code execution of a Notify(thermal_zone, 0x81) statement or via an OS specific interface invoked by device drivers for zone devices participating in the thermal model.
11.1.2.1   OSPM Change of Cooling Policy
When OSPM changes the platform's cooling policy from one cooling mode to the other, the following occurs:
1.    OSPM notifies the platform of the new cooling mode by running the Set Cooling Policy (_SCP) control method in all thermal zones and invoking the OS-specific Set Cooling Policy interface to all participating devices in each thermal zone.
2.    Thresholds are updated in the hardware and OSPM is notified of the change.
3.    OSPM re-evaluates the active and passive cooling temperature trip points for the zone and all devices in the zone to obtain the new temperature thresholds.
11.1.2.2   Resetting Cooling Temperatures to Adjust to Bay Device Insertion or Removal
The platform can adjust the thermal zone temperature to accommodate the maximum operating temperature of a bay device as necessary example:
1.    Hardware detects that a device was inserted into or removed from the bay, updates the temperature thresholds, and then notifies OSPM of the thermal policy change and device insertion events.
2.    OSPM re-enumerates the devices and re-evaluates the active and passive cooling temperature trip points.
11.1.2.3   Resetting Cooling Temperatures to Implement Hysteresis
An OEM can build hysteresis into platform thermal design by dynamically resetting cooling temperature thresholds. For example:
1.     When the temperature increases to the designated threshold, OSPM will turn on the associated active cooling device or perform passive cooling.
2.    The platform resets the threshold value to a lower temperature (to implement hysteresis) and notifies OSPM of the change. Because of this new threshold value, the fan will be turned off at a lower temperature than when it was turned on (therefore implementing a negative hysteresis).
3.    When the temperature hits the lower threshold value, OSPM will turn off the associated active cooling device or cease passive cooling. The hardware will reset _ACx to its original value and notify OSPM that the trip points have once again been altered.
11.1.3   Detecting Temperature Changes
The ability of the platform and its devices to asynchronously notify an ACPI-compatible OS of meaningful changes in the thermal zone's temperature is a highly desirable capability that relieves OSPM from implementing a poll-based policy and generally results in a much more responsive and optimal thermal policy implementation. Each notification instructs OSPM to evaluate whether a trip point has been crossed and allows OSPM to anticipate temperature trends for the thermal zone.

It is recognized that much of the hardware used to implement thermal zone functionality today is not capable of generating ACPI-visible notifications (SCIs) or only can do so with wide granularity (for example, only when the temperature crosses the critical threshold). In these environments, OSPM must poll the thermal zone's temperature periodically to implement an effective policy.
While ACPI specifies a mechanism that enables OSPM to poll thermal zone temperature, platform reliance on thermal zone polling is strongly discouraged by this specification. OEMs should design systems that asynchronously notify OSPM whenever a meaningful change in the zone's temperature occurs – relieving OSPM of the overhead associated with polling. In some cases, embedded controller firmware can overcome limitations of existing thermal sensor capabilities to provide the desired asynchronous notification.
Notice that the _TZP (thermal zone polling) object is used to indicate whether a thermal zone must be polled by OSPM, and if so, a recommended polling frequency. See section 11.3.18, "_TZP," for more information.
11.1.3.1 Temperature Change Notifications
Thermal zone-wide temperature sensor hardware that supports asynchronous temperature change notifications does so using an SCI. The AML code that responds to this SCI must execute a Notify(thermal_zone, 0x80) statement to inform OSPM that a meaningful change in temperature has occurred. Alternatively, devices with embedded temperature sensors may signal their associated device drivers and the drivers may use an OS-specific interface to signal OSPM's thermal policy driver. A device driver may also invoke a device specific control method that executes a Notify(thermal_zone, 0x80) statement. When OSPM receives this thermal notification, it will evaluate the thermal zone's temperature interfaces to evaluate the current temperature values. OSPM will then compare the values to the corresponding cooling policy trip point values (either zone-wide or device-specific). If the temperature has crossed over any of the policy thresholds, then OSPM will actively or passively cool (or stop cooling) the system, or shut the system down entirely.
Both the number and granularity of thermal zone trip points are OEM-specific. However, it is important to notice that since OSPM can use heuristic knowledge to help cool the system, the more events OSPM receives the better understanding it will have of the system's thermal characteristic.

Figure 11-2 Thermal Events
For example, the simple thermal zone illustrated above includes hardware that will generate a temperature change notification using a 5� Celsius granularity. All thresholds (_PSV, _AC1, _AC0, and _CRT) exist within the monitored range and fall on 5� boundaries. This granularity is appropriate for this system as it provides sufficient opportunity for OSPM to detect when a threshold is crossed as well as to understand the thermal zone's basic characteristics (temperature trends).
Note: The ACPI specification defines Kelvin as the standard unit for absolute temperature values. All thermal zone objects must report temperatures in Kelvin when reporting absolute temperature values. All figures and examples in this section of the specification use Celsius for reasons of clarity. ACPI allows Kelvin to be declared in precision of 1/10^th of a degree (for example, 310.5). Kelvin is expressed as q/K = T/�C + 273.2.

11.1.3.2   Polling
Temperature sensor hardware that is incapable of generating thermal change events, or that can do so for only a few thresholds should inform OSPM to implement a poll-based policy. OSPM does this to ensure that temperature changes across threshold boundaries are always detectable.
Polling can be done in conjunction with hardware notifications. For example, thermal zone hardware that only supports a single threshold might be configured to use this threshold as the critical temperature trip point. Assuming that hardware monitors the temperature at a finer granularity than OSPM would, this environment has the benefit of being more responsive when the system is overheating.
A thermal zone advertises the need to be polled by OSPM via the _TZP object. The absence of this control method informs OSPM to implement polling using an OS-provided default frequency. See section 11.3.18, "_TZP," for more information.
11.1.4   Active Cooling
Active cooling devices typically consume power and produce some amount of noise when enabled. These devices attempt to cool a thermal zone through the removal of heat rather than limiting the performance of a device to address an adverse thermal condition.
The active cooling interfaces in conjunction with the active cooling lists allow the platform to use an active device that offers varying degrees of cooling capability or multiple cooling devices. The active cooling temperature trip points designate the temperature where Active cooling is engaged or disengaged (depending upon the direction in which the temperature is changing). For thermal zone-wide active cooling controls, the _ALx object evaluates to a list of devices that actively cool the zone. For example:
· If a standard single-speed fan is the Active cooling device, then _AC0 evaluates to the temperature where active cooling is engaged and the fan is listed in _AL0.
· If the zone uses two independently controlled single-speed fans to regulate the temperature, then _AC0 will evaluate to the maximum cooling temperature using two fans, and _AC1 will evaluate to the standard cooling temperature using one fan.
· If a zone has a single fan with a low speed and a high speed, the _AC0 will evaluate to the temperature associated with running the fan at high-speed, and _AC1 will evaluate to the temperature associated with running the fan at low speed. _AL0 and _AL1 will both point to different device objects associated with the same physical fan, but control the fan at different speeds.
For ASL coding examples that illustrate these points, see sections 11.5, "Thermal Zone Interface Requirements," and 11.6, "Thermal Zone Examples."
11.1.5   Passive Cooling
Passive cooling controls are able to cool a thermal zone without creating noise and without consuming additional power (actually saving power), but do so by decreasing the performance of the devices in the zone .
11.1.5.1   Processor Clock Throttling
The processor passive cooling threshold (_PSV) in conjunction with the processor list (_PSL) allows the platform to indicate the temperature at which a passive control, for example clock throttling, will be applied to the processor(s) residing in a given thermal zone. Unlike other cooling policies, during passive cooling of processors OSPM may take the initiative to actively monitor the temperature in order to cool the platform.
On an ACPI-compatible platform that properly implements CPU throttling, the temperature transitions will be similar to the following figure, in a coolable environment, running a coolable workload:

Figure 11-3   Temperature and CPU Performance Versus Time
The following equation should be used by OSPM to assess the optimum CPU performance change necessary to lower the thermal zone's temperature:
Equation #1: DP [%] = _TC1 * ( Tn - Tn-1 ) + _TC2 * (Tn - Tt)
Where:
Tn = current temperature
Tt = target temperature (_PSV)
The two coefficients _TC1 and _TC2 and the sampling period _TSP are hardware-dependent constants the OEM must supply to OSPM (for more information, see section 11.3, "Thermal Objects"). The _TSP object contains a time interval that OSPM uses to poll the hardware to sample the temperature. Whenever the time value returned by _TSP has elapsed, OSPM will evaluate _TMP to sample the current temperature (shown as Tn in the above equation). Then OSPM will use the sampled temperature and the passive cooling temperature trip point (_PSV) (which is the target temperature Tt) to evaluate the equation for DP. The granularity of style='font-family:Symbol'>DP is determined by the CPU duty width of the system.
Note: Equation #1 has an implied formula.
Equation #2: Pn = Pn-1 + HW[- DP ] where 0% <= Pn <= 100%
For Equation #2, whenever Pn-1 + DP lies outside the range 0-100%, then Pn will be truncated to 0-100%. For hardware that cannot assume all possible values of Pn between 0 and 100%, a hardware-specific mapping function HW is used.
In addition, the hardware mapping function in Equation #2 should be interpreted as follows:
For absolute temperatures:
1.    If the right hand side of Equation #1 is negative, HW[ DP] is rounded to the next available higher setting of frequency.
2.    If the right hand side of Equation #1 is positive, HW[DP] is rounded to the next available lower setting of frequency.

For relative temperatures:
1.    If the right hand side of Equation #1 is positive, HW[ DP] is rounded to the next available higher setting of frequency.
2.    If the right hand side of Equation #1 is negative, HW[DP] is rounded to the next available lower setting of frequency.
The calculated Pn becomes Pn-1 during the next sampling period.
For more information about CPU throttling, see section 8.1.1, Processor Power State C0." A detailed explanation of this thermal feedback equation is beyond the scope of this specification.
11.1.6   Critical Shutdown
When the thermal zone-wide temperature sensor value reaches the threshold indicated by _CRT, OSPM must immediately shut the system down. The system must disable the power either after the temperature reaches some hardware-determined level above _CRT or after a predetermined time has passed. Before disabling power, platform designers should incorporate some time that allows OSPM to run its critical shutdown operation. There is no requirement for a minimum shutdown operation window that commences immediately after the temperature reaches _CRT. This is because:
·      Temperature might rise rapidly in some systems and slowly on others, depending on casing design and environmental factors.
·      Shutdown can take several minutes on a server and only a few seconds on a hand-held device.
Because of this indistinct discrepancy and the fact that a critical heat situation is a remarkably rare occurrence, ACPI does not specify a target window for a safe shutdown. It is entirely up to the OEM to build in a safe buffer that it sees fit for the target platform.

11.2   Cooling Preferences
A robust OSPM implementation provides the means for the end user to convey a preference (or a level of preference) for either performance or energy conservation to OSPM. Allowing the end user to choose this preference is most critical to mobile system users where maximizing system run-time on a battery charge often has higher priority over realizing maximum system performance. For example, if a user is taking notes on her PC in a quiet environment, such as a library or a corporate meeting, she may want the system to emphasize passive cooling so that the system operates quietly, even at the cost of system performance.
A user preference towards performance corresponds to the Active cooling mode while a user's preference towards energy conservation or quiet corresponds to the Passive cooling mode. ACPI defines an interface to convey the cooling mode to the platform. Active cooling can be performed with minimal OSPM thermal policy intervention example, the platform indicates through thermal zone parameters that crossing a thermal trip point requires a fan to be turned on. Passive cooling requires OSPM thermal policy to manipulate device interfaces that reduce performance to reduce thermal zone temperature.
Either cooling mode will be activated only when the thermal condition requires it. When the thermal zone is at an optimal temperature level where it does not warrant any cooling, both modes result in a system operating at its maximum potential with all fans turned off.
Thermal zones supporting the Set Cooling Policy interface allow the user to switch the system's cooling mode emphasis. See section 11.3.7, "_SCP," for more information.

Figure 11-4 Active and Passive Threshold Values

As illustrated in Figure 11-4, the platform must convey the value for each threshold to instruct OSPM to initiate the cooling policies at the desired target temperatures. The platform can emphasize active or passive cooling modes by assigning different threshold values. Generally, if _ACx is set lower than _PSV, then the system emphasizes active cooling. Conversely, if _PSV is set lower than _ACx, then the emphasis is placed on passive cooling.
For example, a thermal zone that includes a processor and one single-speed fan may use _PSV to indicate the temperature value at which OSPM would enable passive cooling and _AC0 to indicate the temperature at which the fan would be turned on. If the value of _PSV is less than _AC0 then the system will favor passive cooling (for example, CPU clock throttling). On the other hand, if _AC0 is less than _PSV the system will favor active cooling (in other words, using the fan). See Figure 11-5 below.

Figure 11-5   Cooling Preferences
The example on the left enables active cooling (for example, turn on a fan) when OSPM detects the temperature has risen above 50�. If for some reason the fan does not reduce the system temperature, then at 75� OSPM will initiate passive cooling (for example, CPU throttling) while still running the fan. If the temperature continues to climb, OSPM will quickly shut the system down when the temperature reaches 90�C. The example on the right is similar but the _AC0 and _PSV threshold values have been swapped to emphasize passive cooling.
The ACPI thermal model allows flexibility in the thermal zone design. An OEM that needs a less elaborate thermal implementation may consider using only a single threshold (for example, _CRT). Complex thermal implementations can be modeled using multiple active cooling thresholds and devices, or through the use of additional thermal zones.
11.2.1   Evaluating Thermal Device Lists
The Notify(thermal_zone, 0x82) statement is used to inform OSPM that a change has been made to the thermal zone device lists. This thermal event instructs OSPM to re-evaluate the _ALx, _PSL, and _TZD objects.
For example, a system that supports the dynamic insertions of processors might issue this notification to inform OSPM of changes to _PSL following the insertion or removal of a processor. OSPM would re-evaluate all thermal device lists and adjust its policy accordingly.
Notice that this notification can be used with the Notify(thermal_zone, 0x81) statement to inform OSPM to both re-evaluate all device lists and all thresholds.
Alternatively, devices may include the _TZM (Thermal Zone Member) object their device scope to convey their thermal zone association to OSPM. Section 11.3.17, "_TZM (Thermal Zone Member)", for more information.
11.2.2   Evaluating Device Thermal Relationship Information
The Notify(thermal_zone, 0x83) statement is used to inform OSPM that a change has been made to the thermal influence information. This thermal event instructs OSPM to re-evaluate the _TRT object. The thermal influence between devices may change when active cooling moves air across device packages as compared to when only passive cooling controls are applied.

11.3 Thermal Objects
Objects related to thermal management are listed in Table 11-1.

Table 11-1 Thermal Objects

Object		Description
	_ACx	Returns active cooling policy threshold values in tenths of degrees.
	_ALx	List of active cooling device objects.
	_CRT	Returns critical trip point in tenths of degrees where OSPM must perform a critical shutdown.
	_HOT	Returns critical trip point in tenths of degrees where OSPM may choose to transition the system into S4.
	_PSL	List of processor device objects for clock throttling.
	_PSV	Returns the passive cooling policy threshold value in tenths of degrees.
	_RTV	Conveys whether temperatures are expressed in terms of absolute or relative values.
	_SCP	Sets platform cooling policy (active or passive).
	_TC1	Thermal constant for passive cooling.
	_TC2	Thermal constant for passive cooling.
	_TMP	Returns the thermal zone's current temperature in tenths of degrees.
	_TPT	Conveys the temperature of a devices internal temperature sensor to the platform when a temperature trip point is crossed.
	_TRT	Table of values that convey the Thermal Relationship between devices
	_TSP	Thermal sampling period for Passive cooling in tenths of seconds.
	_TST	Conveys the minimum separation for a devices' programmable temperature trip points.
	_TZD	List of devices whose temperature is measured by this thermal zone.
	_TZM	Returns the thermal zone for which a device is a member.
	_TZP	Thermal zone polling frequency in tenths of seconds.

With the exception of _TPT, _TST, and the _TZM objects, the objects described in the following sections may exist under a thermal zone. Devices with embedded thermal sensors and controls may contain static cooling temperature trip points or dynamic cooling temperature trip points that must be programmed by the device's driver. In this case, thermal objects defined under a device serve to convey the platform specific values for these settings to the devices driver.
11.3.1 _ACx (Active Cooling)
This optional object, if present under a thermal zone, returns the temperature trip point at which OSPM must start or stop Active cooling, where x is a value between 0 and 9 that designates multiple active cooling levels of the thermal zone. If the Active cooling device has one cooling level (that is, "on") then that cooling level must be defined as _AC0. If the cooling device has two levels of capability, such as a high fan speed and a low fan speed, then they must be defined as _AC0 and _AC1 respectively. The smaller the value of x, the greater the cooling strength _ACx style='font-style:normal'> represents. In the above example, _AC0 represents the greater level of cooling (the faster fan speed) and _AC1 represents the lesser level of cooling (the slower fan speed). For every _ACx method, there must be a matching _ALx style='font-style:normal'> object.
If this object it present under a device, the device's driver evaluates this object to determine the device's corresponding active cooling temperature trip point. This value may then be used by the device's driver to program an internal device temperature sensor trip point. When this object is present under a device, either the device must contain a native OS device driver interface supporting a corresponding active cooling control or there must be a matching _ALx object under the thermal zone of which the device is a member.
Arguments:
None
Result Code:
Active cooling temperature threshold in tenths of degrees.
The result code is an integer value that represents tenths of degrees. For example, 300.0K is represented by the integer 3000.

11.3.2   _ALx style='font-style:normal'> (Active List)
This object is defined under a thermal zone and evaluates to a list of Active cooling devices to be turned on when the corresponding _ACx temperature threshold is exceeded. For example, these devices could be fans.
Arguments:
None
Result Code:
A package consisting of references to all active cooling devices that should be engaged when the associated active cooling threshold (_ACx) is exceeded.
11.3.3   _CRT (Critical Temperature)
This object, when defined under a thermal zone, returns the critical temperature at which OSPM must shutdown the system. If this object it present under a device, the device's driver evaluates this object to determine the device's critical cooling temperature trip point. This value may then be used by the device's driver to program an internal device temperature sensor trip point.
Arguments:
None
Result Code:
Critical temperature threshold in tenths of degrees.
The result is an integer value that represents tenths of degrees. For example, 300.0K is represented by the integer 3000.
11.3.4   _HOT (Hot Temperature)
This object, when defined under a thermal zone, returns the critical temperature at which OSPM may choose to transition the system into the S4 sleeping state. The platform vendor should define _HOT to be far enough below _CRT so as to allow OSPM enough time to transition the system into the S4 sleeping state. While dependent on the amount of installed memory, on typical platforms OSPM implementations can transition the system into the S4 sleeping state in tens of seconds. If this object it present under a device, the device's driver evaluates this object to determine the device's hot cooling temperature trip point. This value may then be used by the device's driver to program an internal device temperature sensor trip point.
Arguments:
None
Result Code:
Critical temperature threshold in tenths of degrees.
The result is an integer value that represents tenths of degrees. For example, 300.0K is represented by the integer 3000.
11.3.5   _PSL (Passive List)
This object is defined under a thermal zone and evaluates to a list of processor objects to be used for passive cooling.
Arguments:
None
Result Code:
A package consisting of references to all processor objects that will be used for passive cooling when the zone's passive cooling threshold (_PSV) is exceeded.

11.3.6 _PSV (Passive)
This optional object, if present under a thermal zone, evaluates to the temperature at which OSPM must activate passive cooling policy.
If this object it present under a device, the device's driver evaluates this object to determine the device's corresponding passive cooling temperature trip point. This value may then be used by the device's driver to program an internal device temperature sensor trip point. When this object is present under a device, the device must contain a native OS device driver interface supporting a passive cooling control.
Arguments:
None
Result Code:
Passive cooling temperature threshold in tenths of degrees.
The result code is an integer value that represents tenths of degrees. For example, 300.0 Kelvin is represented by 3000.
11.3.7 _RTV (Relative Temperature Values)
This optional object may be present under a device or a thermal zone and is evaluated by OSPM to determine whether the values returned by temperature trip point and current operating temperature interfaces under the corresponding device or thermal zone represent absolute or relative temperature values.
If the _RTV object is not present or is present and evaluates to zero then OSPM assumes that all values returned by temperature trip point and current operating temperature interfaces under the device or thermal zone represent absolute temperature values expressed in tenths of degrees Kelvin.
If the _RTV object is present and evaluates to a non zero value then all values returned by temperature trip point and current operating temperature interfaces under the corresponding device or thermal zone represent temperature values relative to a zero point that is defined as the maximum value of the device's or thermal zone's critical cooling temperature trip point. In this case, temperature trip point and current operating temperature interfaces return values in units that are tenths of degrees below the zero point.

OSPM evaluates the _RTV object before evaluating any other temperature trip point or current operating temperature interfaces.
Arguments:
None
Result Code:
Integer indicating whether values returned by temperature trip point and current operating temperature interfaces represent absolute of relative temperature values.

11.3.8 _SCP (Set Cooling Policy)
This optional object is a control method that OSPM invokes to set the platform's cooling mode policy setting. The platform may use the evaluation of _SCP to reassign _ACx and _PSV temperature trip points according to the mode or limits conveyed by OSPM. OSPM will automatically evaluate _ACx and _PSV objects after executing _SCP. This object may exist under a thermal zone or a device.
Arguments:
Arg0 (Integer):          Mode
Arg1 (Integer):          Acoustic Limit
Arg2 (Integer):          Power Limit
Where:
Mode – 0 = Active, 1 = Passive
Acoustic Limit – Specifies the maximum acceptable acoustic level that active cooling devices may generate. Values are 1 to 5 where 1 means no acoustic tolerance and 5 means maximum acoustic tolerance.
Power Limit – Specifies the maximum acceptable power level that active cooling devices may consume. Values are from 1 to 5 where 1 means no power may be used to cool and 5 means maximum power may be used to cool.
Result Code:
None
Example:

// Fan Control is defined as follows:
// Speed 1 (Fan is Off): Acoustic Limit 1, Power Limit 1, <= 64C
// Speed 2:      Acoustic Limit 2, Power Limit 2, 65C - 74C
// Speed 3:      Acoustic Limit 3, Power Limit 3, 75C - 84C
// Speed 4:      Acoustic Limit 4, Power Limit 4, 85C - 94C
// Speed 5:      Acoustic Limit 5, Power Limit 5, >= 95C

// _SCP Notifies the platform the current cooling mode.
// Arg0 = Mode
//     0 - Active cooling
//     1 - Passive cooling
// Arg1 = Acoustic Limit
//     1 = No acoustic tolerance
//     ...
//     5 = maximum acoustic tolerance
// Arg2 = Power Limit
//     1 = No power may be used to cool
//     ...
//     5 = maximum power may be used to cool

Method(_SCP,3,Serialized)
{
    // Store the Cooling Mode in NVS and use as needed in
    // the rest of the ASL Code.
    Store(Arg0, CTYP)

    // Set PSVT to account for a Legacy OS that does not pass
    // in either the acoustic limit or Power Limit.
    If(Arg0)
    {
       Store(60,PSVT)
    }
    Else
    {
       Store(97,PSVT)
    }
    If (CondRefOf (_OSI,Local0))
    {
    If (\_OSI ("3.0 _SCP Extensions"))
    {
       // Determine Power Limit.
       //
       // NOTE1: PSVT = Passive Cooling Trip Point stored
       // in NVS in Celsius.
       //
       // NOTE2: 4 Active Cooling Trips Points correspond to 5
       // unique Power Limit regions and 5 unique acoustic limit
       // regions.
       //
       // NOTE3: This code will define Passive cooling so that
       // CPU throttling will be initiated within the Power Limit
       // Region passed in such that the next higher Power Limit
       // Region will not be reached.
       Switch(Arg2)
       {
           Case(1)           // Power Limit = 1.
           {
              // Stay in Acoustic Limit 1.
              Store(60,PSVT) // Passive = 60C.
           }
           Case(2)           // Power Limit = 2.
           {
              // Store Highest supported Acoustic Level
              // at this Power Limit (1 or 2).
              Store(70,PSVT)
              If(Lequal(Arg1,1))
              {
                  // Stay in Acoustic Level 1.
                  Store(60,PSVT)
              }
           }
           Case(3)           // Power Limit = 3.
           {
              // Store Highest supported Acoustic Level
              // at this Power Limit (1, 2, or 3).
              Store(80,PSVT)
              If(Lequal(Arg1,2))
              {
                  // Stay in Acoustic Level 1 or 2.
                  Store(70,PSVT)
              }
              If(Lequal(Arg1,1))
              {
                  // Stay in Acoustic Level 1.
                  Store(60,PSVT)
              }
           }
           Case(4)           // Power Limit = 4.
           {
              // Store Highest supported Acoustic Level
              // at this Power Limit (1, 2, 3, or 4).
              Store(90,PSVT)
              If(Lequal(Arg1,3))
              {
                  // Stay in Acoustic Level 1 or 2.
                  Store(80,PSVT)
              }
              If(Lequal(Arg1,2))
              {
                  // Stay in Acoustic Level 1 or 2.
                  Store(70,PSVT)
              }
              If(Lequal(Arg1,1))
              {
                  // Stay in Acoustic Level 1.
                  Store(60,PSVT)
              }
           }
           Case(5)           // Power Limit = 5.
           {
              // Store Highest supported Acoustic Level
              // at this Power Limit (1, 2, 3, 4, or 5).
              Store(97,PSVT)
              If(Lequal(Arg1,4))
              {
                  // Stay in Acoustic Level 1 or 2.
                  Store(90,PSVT)
              }
              If(Lequal(Arg1,3))
              {
                  // Stay in Acoustic Level 1 or 2.
                  Store(80,PSVT)
              }
              If(Lequal(Arg1,2))
              {
                  // Stay in Acoustic Level 1 or 2.
                  Store(70,PSVT)
              }
              If(Lequal(Arg1,1))
              {
                  // Stay in Acoustic Level 1.
                  Store(60,PSVT)
              }
           } // Case 5
       } // Switch Arg 2
    } // _OSI - Extended _SCP
} // CondRefOf _OSI
} // Method _SCP

11.3.9   _TC1 (Thermal Constant 1)
This object evaluates to the constant _TC1 for use in the Passive cooling formula:
DPerformance [%]= _TC1 * ( Tn - Tn-1 ) + _TC2 * (Tn. - Tt)
Arguments:
None
Result Code:
Integer value of thermal constant #1.
11.3.10   _TC2 (Thermal Constant 2)
This object evaluates to the constant _TC2 for use in the Passive cooling formula:
DPerformance [%]= _TC1 * ( Tn - Tn-1 ) + _TC2 *(Tn - Tt)

Arguments:
None
Result Code:
Integer value of thermal constant #2.

11.3.11   _TMP (Temperature)
This control method returns the thermal zone's current operating temperature.
Arguments:
None
Result Code:
The current temperature of the thermal zone in tenths of degrees. For example, 300.0K is represented by the integer 3000.
11.3.12 _TPT (Trip Point Temperature)
This optional object may be present under a device and is invoked by OSPM to indicate to the platform that the devices' embedded temperature sensor has crossed a cooling temperature trip point. After invocation, OSPM immediately evaluates the devices' Active and Passive cooling temperature trip point values. This enables the platform to implement hysteresis.
Arguments:
Current value of device's embedded temperature sensor in tenths of degrees.
Result Code:
None
11.3.13   _TRT (Thermal Relationship Table)
This object evaluates to a package of packages each of which describes the thermal relationship between devices within a thermal zone. OSPM uses the combined information about the thermal relationships of all devices in the thermal zone to make thermal policy decisions.

Name (_TRT, Package()
{      // Field Name      Field Type

    Package ()    // First Thermal Relationship Package Data
    {
       SourceDevice,                   // ObjectReference to a Device Object
       TargetDevice,                   // ObjectReference to a Device Object
       ThermalInfluence,               // Integer
       ThermalSamplingPeriod,              // Integer
       Reserved1,                       // Integer
       Reserved2,                       // Integer
       Reserved3,                       // Integer
       Reserved4                       // Integer
    },
    .
    .
    .
    Package ()    // Last Thermal Relationship Package Data
    {
       SourceDevice,                   // ObjectReference to a Device Object
       TargetDevice,                   // ObjectReference to a Device Object
       ThermalInfluence,               // Integer
       ThermalSamplingPeriod,              // Integer
       Reserved1,                       // Integer
       Reserved2,                       // Integer
       Reserved3,                       // Integer
       Reserved4                       // Integer
    }
}) // End of _TRT object

Each Thermal Relationship Table entry contains eight data fields as follows:
· SourceDevice. The device that is influencing the device indicated by TargetDevice.

· TargetDevice. The device that is influenced by the device indicated by SourceDevice

· ThermalInfluence. Indicates the thermal influence of SourceDevice on TargetDevice represented as tenths of degrees Kelvin that the device indicated by SourceDevice raises the temperature of the device indicated by TargetDevice style='font-style:normal'> per Watt of thermal load that SourceDevice generates.

·      ThermalSamplingPeriod. The minimum period of time in tenths of seconds that OSPM should wait after applying a passive control to the device indicated by SourceDevice to detect its impact on the device indicated by TargetDevice style='font-style:normal'>.
·      Reserved1. Reserved for future use.
·      Reserved2. Reserved for future use.
·      Reserved3. Reserved for future use.
·      Reserved4. Reserved for future use.
11.3.14   _TSP (Thermal Sampling Period)
This object evaluates to a thermal sampling period (in tenths of seconds) used by OSPM to implement the Passive cooling equation. This value, along with _TC1 and _TC2, will enable OSPM to provide the proper hysteresis required by the system to accomplish an effective passive cooling policy. The granularity of the sampling period is 0.1 seconds. For example, if the sampling period is 30.0 seconds, then _TSP needs to report 300; if the sampling period is 0.5 seconds, then it will report 5. OSPM can normalize the sampling over a longer period if necessary.
Arguments:
None
Result Code:
Thermal sampling period for passive cooling, in tenths of seconds.
11.3.15 _TST (Temperature Sensor Threshold)
This optional object may be present under a device and is evaluated by OSPM to determine the minimum separation for a devices'programmable temperature trip points. When a device contains multiple programmable temperature trip points, it may not be necessary for OSPM to poll the device's temperature after crossing a temperature trip point when performing passive cooling control policy. To eliminate polling, the device can program intermediate trip points of interest (higher or lower than the current temperature) and signal the crossing of the intermediate trip points to OSPM. The distance between the current temperature and these intermediate trip points may be platform specific and must be set far enough away from the current temperature so as to not to miss the crossing of a meaningful temperature point. The _TST object conveys the recommended minimum separation between the current temperature and an intermediate temperature trip point to OSPM.
Arguments:
None
Result Code:
Temperature sensor threshold in tenths of degrees.
11.3.16   _TZD (Thermal Zone Devices)
This optional object evaluates to a package of device names. Each name corresponds to a device in the ACPI namespace that is associated with the thermal zone. The temperature reported by the thermal zone is roughly correspondent to that of each of the devices.
The list of devices returned by the control method need not be a complete and absolute list of devices affected by the thermal zone. However, the package should at least contain the devices that would uniquely identify where this thermal zone is located in the machine. For example, a thermal zone in a docking station should include a device in the docking station, a thermal zone for the CD-ROM bay, should include the CD-ROM.
Arguments:
None
Result Code:
A package consisting of references to devices associated with the thermal zone.
11.3.17   _TZM (Thermal Zone Member)
This optional object may exist under any device definition and evaluates to a reference to the thermal zone of which the device is a member.
Arguments:
None
Result Code:
A reference to the thermal zone of which the device is a member.
11.3.18   _TZP (Thermal Zone Polling)
This optional object evaluates to a recommended polling frequency (in tenths of seconds) for this thermal zone. A value of zero indicates that OSPM does not need to poll the temperature of this thermal zone in order to detect temperature changes (the hardware is capable of generating asynchronous notifications). Notice that the absence of _TZP informs OSPM to implement polling using an OS-provided default frequency.
The use of polling is allowed but strongly discouraged by this specification. OEMs should design systems that asynchronously notify OSPM whenever a meaningful change in the zone's temperature occurs—relieving the OS of the overhead associated with polling. See section 11.1.3, "Detecting Temperature Changes," for more information.

This value is specified as tenths of seconds with a 1 second granularity. A minimum value of 30 seconds (_TZP evaluates to 300) and a maximum value of 300 seconds (in other words, 5 minutes) (_TZP evaluates to 3000) may be specified. As this is a recommended value, OSPM will consider other factors when determining the actual polling frequency to use.
Arguments:
None
Result Code:
The recommended polling frequency, in tenths of seconds. A value of zero indicates that polling is not necessary.
11.4   Native OS Device Driver Thermal Interfaces
OS implementations compatible with the ACPI 3.0 thermal model, interface with the thermal objects of a thermal zone but also comprehend the thermal zone devices' OS native device driver interfaces that perform similar functions to the thermal objects at the device level.
The recommended native OS device driver thermal interfaces that enable OSPM to perform optimal performance / thermal management include:
· Reading a value from a device's embedded thermal sensor
· Reading a value that indicates whether temperature and trip point values are reported in absolute or relative temperatures
· Setting the platform's cooling mode policy setting
· Reading the embedded thermal sensor's threshold
· Reading the device's active and passive cooling temperature trip points
· Reading the device's association to a thermal zone
· Signaling the crossing of a thermal trip point
· Reading the desired polling frequency at which to check the devices temperature if the device cannot signal OSPM or signal OSPM optimally (both before and after a temperature trip point is crossed)
· Setting / limiting a device's performance / throttling states
· Engaging / disengaging a device's active cooling controls
These interfaces are OS specific and as such the OS vendor defines the exact interface definition for each target operating system.
11.5   Thermal Zone Interface Requirements
While not all thermal zone interfaces are required to be present in each thermal zone, OSPM levies conditional requirements for the presence of specific thermal zone interfaces based on the existence of other related thermal zone interfaces. These interfaces may be implemented by thermal zone-wide objects or by OS-specific device driver exposed thermal interfaces. The requirements are outlined below:
·      A thermal zone must contain at least one temperature interface;either the _TMP object or a member device temperature interface.
·      A thermal zone must contain at least one trip point (critical, near critical, active, or passive)..
·      If _ACx is defined then an associated _ALx must be defined (e.g. defining _AC0 requires _AL0 also be defined).
·      If _PSV is defined then either the _PSL or _TZD objects must exist. The _PSL and _TZD objects may both exist.
·      If _PSL is defined then:
·       If a linear performance control register is defined (via either P_BLK or the _PTC, _TSS, _TPC objects) for a processor defined in _PSL or for a processor device in the zone as indicated by _TZM then the _TC1, _TC2, and objects must exist _TSP object must also be defined if the device requires polling.
·       If a linear performance control register is not defined (via either P_BLK or the _PTC, _TSS, _TPC objects) for a processor defined in _PSL or for a processor device in the zone as indicated by _TZM then the processor must support processor performance states (in other words, the processor's processor object must include _PCT, _PSS, and _PPC).
·      If _PSV is defined and _PSL is not defined then at least one device in thermal zone, as indicated by either the _TZD device list or devices'_TZM objects, must support device performance states.
·      _SCP is optional.
·      _TZD is optional outside of the _PSV requirement outlined above.
·      If _HOT is defined then the system must support the S4 sleeping state.
11.6   Thermal Zone Examples
11.6.1   Example: The Basic Thermal Zone
The following ASL describes a basic configuration where the entire system is treated as a single thermal zone. Cooling devices for this thermal zone consist of a processor and one single-speed fan. This is an example only.
Notice that this thermal zone object (TZ0) is defined in the \_SB scope. Thermal zone objects should appear in the namespace under the portion of the system that comprises the thermal zone. For example, a thermal zone that is isolated to a docking station should be defined within the scope of the docking station device. Besides providing for a well-organized namespace, this configuration allows OSPM to dynamically adjust its thermal policy as devices are added or removed from the system.

Scope(\_SB) {
    Processor(
       CPU0,
       1,    // unique number for this processor
       0x110,    // system IO address of Pblk Registers
       0x06    // length in bytes of PBlk
    ) {}

Scope(\_SB.PCI0.ISA0) {
    Device(EC0) {
       Name(_HID, EISAID("PNP0C09"))       // ID for this EC
       // current resource description for this EC
       Name(_CRS, ResourceTemplate() {
           IO(Decode16,0x62,0x62,0,1)
           IO(Decode16,0x66,0x66,0,1)
       })
       Name(_GPE, 0)                    // GPE index for this EC

       // create EC's region and field for thermal support
       OperationRegion(EC0, EmbeddedControl, 0, 0xFF)
       Field(EC0, ByteAcc, Lock, Preserve) {
           MODE, 1,                   // thermal policy (quiet/perform)
           FAN,   1,                   // fan power (on/off)
           ,      6,                   // reserved
           TMP,   16,                  // current temp
           AC0,   16,                  // active cooling temp (fan high)
           ,      16,                  // reserved
           PSV,   16,                  // passive cooling temp
           HOT    16,                  // critical S4 temp
           CRT,   16                   // critical temp
       }

       // following is a method that OSPM will schedule after
       // it receives an SCI and queries the EC to receive value 7
       Method(_Q07) {
           Notify (\_SB.PCI0.ISA0.EC0.TZ0, 0x80)
       }   // end of Notify method

    // fan cooling on/off - engaged at AC0 temp
    PowerResource(PFAN, 0, 0) {
       Method(_STA) { Return (\_SB.PCI0.ISA0.EC0.FAN) }          // check power state
       Method(_ON) { Store (One, \_SB.PCI0.ISA0.EC0.FAN) }          // turn on fan
       Method(_OFF) { Store ( Zero, \_SB.PCI0.ISA0.EC0.FAN) }    // turn off fan
    }

    // Create FAN device object
    Device (FAN) {
       // Device ID for the FAN
       Name(_HID, EISAID("PNP0C0B"))
       // list power resource for the fan
       Name(_PR0, Package(){PFAN})
    }

    // create a thermal zone
    ThermalZone (TZ0) {
       Method(_TMP) { Return (\_SB.PCI0.ISA0.EC0.TMP )} // get current temp
       Method(_AC0) { Return (\_SB.PCI0.ISA0.EC0.AC0) } // fan high temp
       Name(_AL0, Package(){\_SB.PCI0.ISA0.EC0.FAN}) // fan is act cool dev
       Method(_PSV) { Return (\_SB.PCI0.ISA0.EC0.PSV) } // passive cooling temp
       Name(_PSL, Package (){\_SB.CPU0})                 // passive cooling devices
       Method(_HOT) { Return (\_SB.PCI0.ISA0.EC0.HOT) } // get critical S4 temp
       Method(_CRT) { Return (\_SB.PCI0.ISA0.EC0.CRT) } // get critical temp
       Method(_SCP, 1) { Store (Arg1, \_SB.PCI0.ISA0.EC0.MODE) } // set cooling mode
       Name(_TC1, 4)                                  // bogus example constant
       Name(_TC2, 3)                                  // bogus example constant
       Name(_TSP, 150)                                // passive sampling = 15 sec
       Name(_TZP, 0)                                  // polling not required
       } // end of TZ0

    } // end of ECO
} // end of \_SB.PCI0.ISA0 scope-

} // end of \_SB scope
11.6.2   Example: Multiple-Speed Fans
The following ASL describes a thermal zone consisting of a processor and one dual-speed fan. As with the previous example, this thermal zone object (TZ0) is defined in the \_SB scope and represents the entire system. This is an example only.

Scope(\_SB) {
    Processor(
       CPU0,
       1,    // unique number for this processor
       0x110,    // system IO address of Pblk Registers
       0x06    // length in bytes of PBlk
    ) {}

Scope(\_SB.PCI0.ISA0) {
    Device(EC0) {
       Name(_HID, EISAID("PNP0C09"))       // ID for this EC
       // current resource description for this EC
       Name(_CRS, ResourceTemplate() {
           IO(Decode16,0x62,0x62,0,1)
           IO(Decode16,0x66,0x66,0,1)
       })
       Name(_GPE, 0)     // GPE index for this EC

       // create EC's region and field for thermal support
       OperationRegion(EC0, EmbeddedControl, 0, 0xFF)
       Field(EC0, ByteAcc, Lock, Preserve) {
           MODE, 1,     // thermal policy (quiet/perform)
           FAN0, 1,     // fan strength high/off
           FAN1, 1,     // fan strength low/off
           ,      5,     // reserved
           TMP,   16,    // current temp
           AC0,   16,    // active cooling temp (high)
           AC1,   16,    // active cooling temp (low)
           PSV,   16,    // passive cooling temp
           HOT    18,    // critical S4 temp
           CRT,   16     // critical temp
       }

       // following is a method that OSPM will schedule after it
       // receives an SCI and queries the EC to receive value 7
       Method(_Q07) {
           Notify (\_SB.PCI0.ISA0.EC0.TZ0, 0x80)
       } end of Notify method

        // fan cooling mode high/off - engaged at AC0 temp
        PowerResource(FN10, 0, 0) {
           Method(_STA) { Return (\_SB.PCI0.ISA0.EC0.FAN0) } // check power state
           Method(_ON) { Store (One, \_SB.PCI0.ISA0.EC0.FAN0) }      // turn on fan at high
           Method(_OFF) { Store (Zero, \_SB.PCI0.ISA0.EC0.FAN0) }// turn off fan
        }

        // fan cooling mode low/off -engaged at AC1 temp
        PowerResource(FN11, 0, 0) {
           Method(_STA) { Return (\_SB.PCI0.ISA0.EC0.FAN1) } // check power state
           Method(_ON) { Store (One, \_SB.PCI0.ISA0.EC0.FAN1) }      // turn on fan at low
           Method(_OFF) { Store (Zero, \_SB.PCI0.ISA0.EC0.FAN1) }// turn off fan
        }

    // Following is a single fan with two speeds. This is represented
    // by creating two logical fan devices. When FN2 is turned on then
    // the fan is at a low speed. When FN1 and FN2 are both on then
    // the fan is at high speed.
    //
    // Create FAN device object FN1
    Device (FN1) {
       // Device ID for the FAN
       Name(_HID, EISAID("PNP0C0B"))
       Name(_UID, 0)
       Name(_PR0, Package(){FN10, FN11})
    }

    // Create FAN device object FN2
    Device (FN2) {
       // Device ID for the FAN
       Name(_HID, EISAID("PNP0C0B"))
       Name(_UID, 1)
       Name(_PR0, Package(){FN10})
    }

    // create a thermal zone
    ThermalZone (TZ0) {
       Method(_TMP) { Return (\_SB.PCI0.ISA0.EC0.TMP )} // get current temp
       Method(_AC0) { Return (\_SB.PCI0.ISA0.EC0.AC0) } // fan high temp
       Method(_AC1) { Return (\_SB.PCI0.ISA0.EC0.AC1) } // fan low temp
       Name(_AL0, Package() {\_SB.PCI0.ISA0.EC0.FN1}) // active cooling (high)
       Name(_AL1, Package() {\_SB.PCI0.ISA0.EC0.FN2}) // active cooling (low)
       Method(_PSV) { Return (\_SB.PCI0.ISA0.EC0.PSV) } // passive cooling temp
       Name(_PSL, Package() {\_SB.CPU0})                 // passive cooling devices
       Method(_HOT) { Return (\_SB.PCI0.ISA0.EC0.HOT) } // get critical S4 temp
       Method(_CRT) { Return (\_SB.PCI0.ISA0.EC0.CRT) } // get crit. temp
       Method(_SCP, 1) { Store (Arg1, \_SB.PCI0.ISA0.EC0.MODE) } // set cooling mode
       Name(_TC1, 4)                                  // bogus example constant
       Name(_TC2, 3)                                  // bogus example constant
       Name(_TSP, 150)                                // passive sampling = 15 sec
       Name(_TZP, 0)                                  // polling not required
       } // end of TZ0

    } // end of ECO
}   // end of \_SB.PCI0.ISA0 scope

} // end of \_SB scope
11.6.3   Example:Thermal Zone with Multiple Devices

Scope(\_SB) {
    Device(CPU0) {

       Name(_HID, "ACPI0007")
       Name(_UID, 0)

       //
       // Load additional objects if 3.0 Thermal model support is available
       //
       Method(_INI, 0) {
           If (\_OSI("3.0 Thermal Model")) {
              LoadTable("OEM1", "PmRef", "Cpu0", "\\_SB.CPU0") // 3.0 Thermal Model
           }
       }

       // For brevity, most processor objects have been excluded
       // from this example (such as _PSS, _CST, _PCT, _PPC, etc.)

       // Processor Throttle Control object
       Name(_PTC, ResourceTemplate() {
           Register(SystemIO, 32, 0, 0x120) // Processor Control
           Register(SystemIO, 32, 0, 0x120) // Processor Status
       })

       // Throttling Supported States
       // The values shown are for exemplary purposes only
       Name(_TSS, Package() {
       // Read: freq percentage, power, latency, control, status
           Package() {0x64, 1000, 0x0, 0x7, 0x0}, // Throttle off (100%)
           Package() {0x58, 800, 0x0, 0xF, 0x0},      // 87.5%
           Package() {0x4B, 600, 0x0, 0xE, 0x0},      // 75%
           Package() {0x3F, 400, 0x0, 0xD, 0x0}       // 62.5%
       })

       // Throttling Present Capabilities
       // The values shown are for exemplary purposes only
       Method(_TPC) {
           If(\_SB.AC) {
               Return(0) // All throttle states available
           } Else {
              Return(2) // Throttle states >= 2 are available
           }
       }
    } // end of CPU0 scope

    Device(CPU1) {

       Name(_HID, "ACPI0007")
       Name(_UID, 1)

       //
       // Load additional objects if 3.0 Thermal model support is available
       //
       Method(_INI, 0) {
           If (\_OSI("3.0 Thermal Model")) {
              LoadTable("OEM1", "PmRef", "Cpu1", "\\_SB.CPU1") // 3.0 Thermal Model
           }
       }

       // For brevity, most processor objects have been excluded
       // from this example (such as _PSS, _CST, _PCT, _PPC, _PTC, etc.)

       // Processor Throttle Control object
       Name(_PTC, ResourceTemplate() {
           Register(SystemIO, 32, 0, 0x120) // Processor Control
           Register(SystemIO, 32, 0, 0x120) // Processor Status
       })

       // Throttling Supported States
       // The values shown are for exemplary purposes only
       Name(_TSS, Package() {
       // Read: freq percentage, power, latency, control, status
           Package() {0x64, 1000, 0x0, 0x7, 0x0}, // Throttle off (100%)
           Package() {0x58, 800, 0x0, 0xF, 0x0},      // 87.5%
           Package() {0x4B, 600, 0x0, 0xE, 0x0},      // 75%
           Package() {0x3F, 400, 0x0, 0xD, 0x0}       // 62.5%
       })

       // Throttling Present Capabilities
       // The values shown are for exemplary purposes only
       Method(_TPC) {
           If(\_SB.AC) {
              Return(0) // All throttle states available
           } Else {
              Return(2) // Throttle states >= 2 are available
           }
       }
    } // end of CPU1 scope

Scope(\_SB.PCI0.ISA0) {
    Device(EC0) {
       Name(_HID, EISAID("PNP0C09"))       // ID for this EC

       //
       // Load additional objects if 3.0 Thermal model support is available
       //
       Method(_INI, 0) {
           If (\_OSI("3.0 Thermal Model")) {
              LoadTable("OEM1", "PmRef", "Tz3", "\\_SB.PCI0.ISA0.EC0") // 3.0 Tz
           }
       }

       // Current resource description for this EC
       Name(_CRS,
              ResourceTemplate() {
                  IO(Decode16,0x62,0x62,0,1)
                  IO(Decode16,0x66,0x66,0,1)
           })

       Name(_GPE, 0)     // GPE index for this EC

       // Create EC's region and field for thermal support
       OperationRegion(EC0, EmbeddedControl, 0, 0xFF)
       Field(EC0, ByteAcc, Lock, Preserve) {
           MODE, 1,     // thermal policy (quiet/perform)
           FAN0, 1,     // fan strength high/off
           ,      6,     // reserved
           TMP,   16,    // current temp
           AC0,   16,    // active cooling temp
           PSV,   16,    // passive cooling temp
           HOT,   16,    // critical S4 temp
           CRT,   16     // critical temp
       }

       // Following is a method that OSPM will schedule after it
    // fan cooling mode high/off - engaged at AC0 temp
    PowerResource(FN10, 0, 0) {
       Method(_STA) { Return (\_SB.PCI0.ISA0.EC0.FAN0) } // check power state
        Method(_ON) { Store (One, \_SB.PCI0.ISA0.EC0.FAN0) }      // turn on fan at high
       Method(_OFF) { Store (Zero, \_SB.PCI0.ISA0.EC0.FAN0) }// turn off fan
    }

    // Following is a single fan with one speed.
    // Create FAN device object FN1
    Device (FN1) {
       // Device ID for the FAN
       Name(_HID, EISAID("PNP0C0B"))
       Name(_UID, 0)
       Name(_PR0, Package(){FN10})
    }

       // Receives an SCI and queries the EC to receive value 7
       Method(_Q07) {
           Notify (\_SB.PCI0.ISA0.EC0.TZ0, 0x80)
       } // end of Notify method

    // Create standard specific thermal zone
    ThermalZone (TZ0) {
       Method(_TMP) { Return (\_SB.PCI0.ISA0.EC0.TMP )} // get current temp
       Name(_PSL, Package() {\_SB.CPU0, \_SB.CPU1})      // passive cooling devices
       Name(_AL0, Package() {\_SB.PCI0.ISA0.EC0.FN1}) // active cooling
       Method(_AC0) { Return (\_SB.PCI0.ISA0.EC0.AC0) } // fan temp (high)
       Method(_AC1) { Return (\_SB.PCI0.ISA0.EC0.AC1) } // fan temp (low)
       Method(_PSV) { Return (\_SB.PCI0.ISA0.EC0.PSV) } // passive cooling temp
       Method(_HOT) { Return (\_SB.PCI0.ISA0.EC0.HOT) } // get critical S4 temp
       Method(_CRT) { Return (\_SB.PCI0.ISA0.EC0.CRT) } // get crit. temp
       Name(_TC1, 4)                                  // bogus example constant
       Name(_TC2, 3)                                  // bogus example constant
       Method(_SCP, 1) { Store (Arg0, \_SB.PCI0.ISA0.EC0.MODE) } // set cooling mode
       Name(_TSP, 150)                                // passive sampling = 15 sec
       } // end of TZ0

    } // end of ECO
}   // end of \_SB.PCI0.ISA0 scope
} // end of \_SB scope

//
// ACPI 3.0 Thermal Model SSDT
//
DefinitionBlock (
    "TZASSDT.aml",
    "OEM1",
    0x01,
    "PmRef",
    "Tz3",
    0x3000
    )
{
    External(\_SB.PCI0.ISA0.EC0, DeviceObj)
    External(\_SB.CPU0, DeviceObj)
    External(\_SB.CPU1, DeviceObj)

    Scope(\_SB.PCI0.ISA0.EC0)
    {
    // Create an ACPI 3.0 specific thermal zone
    ThermalZone (TZ0) {
       // This TRT is for exemplary purposes only
       Name(_TRT, Package() {
           // Thermal relationship package data. A package is generated for
           // each permutation of device sets. 2 devices = 4 entries.
           // Read: source, target, thermal influence, sampling period, 4 reserved
           Package () {\_SB.CPU0,   \_SB.CPU0, 20, 1, 0, 0, 0, 0},
           Package () {\_SB.CPU0,   \_SB.CPU1, 10, 15, 0, 0, 0, 0},
           Package () {\_SB.CPU1,   \_SB.CPU0, 10, 15, 0, 0, 0, 0},
           Package () {\_SB.CPU1,   \_SB.CPU1, 20, 1, 0, 0, 0, 0}
       }) // end of TRT
    } // end of TZ0
    } // end of EC0 Scope
} // end of SSDT

//
// CPU0 3.0 Thermal Model SSDT
//
DefinitionBlock (
    "CPU0SSDT.aml",
    "OEM1",
    0x01,
    "PmRef",
    "CPU0",
    0x3000
    )
{
    External(\_SB.CPU0, DeviceObj)
    External(\_SB.PCI0.ISA0.TZ0, ThermalZoneObj)

    Scope(\_SB.CPU0)
    {
       //
       // Add the objects required for 3.0 extended thermal support
       //
       // Create a region and fields for thermal support; the platform
       // fills in the values and traps on writes to enable hysteresis.
       // The Operation Region location is invalid
       OperationRegion(CP00, SystemMemory, 0x00000000, 0xA)
       Field(CP00, ByteAcc, Lock, Preserve) {
           SCP,   1,     // thermal policy (passive/active)
           RTV,   1,     // absolute or relative temperature
           ,      6,     // reserved
           AC0,   16,    // active cooling temp
           PSV,   16,    // passive cooling temp
           CRT,   16,    // critical temp
           TPT,   16,    // Temp trip point crossed
           TST,   8      // Temp sensor threshold
       }

       Method(_TZM, 0) { Return(\_SB.PCI0.ISA0.TZ0) } // thermal zone member

       // Some thermal zone methods are now located under the
       // thermal device participating in the 3.0 thermal model.
       // These methods provide device specific thermal information
    Method(_SCP, 1) { Store (Arg0, \_SB.CPU0.SCP) }   // set cooling mode
    Method(_RTV) { Return (\_SB.CPU0.RTV) }        // absolute or relative temp
    Method(_AC0) { Return (\_SB.CPU0.AC0) }        // active cooling (fan) temp
    Method(_PSV) { Return (\_SB.CPU0.PSV) }        // passive cooling temp
    Method(_CRT) { Return (\_SB.CPU0.CRT) }        // critical temp
    Name(_TC1, 4)                                  // thermal constant 1 (INVALID)
    Name(_TC2, 3)                                  // thermal constant 2 (INVALID)
    Method(_TPT, 1) { Store (Arg0, \_SB.CPU0.TPT)} // trip point temp
    Method(_TST) { Return (\_SB.CPU0.TST) }        // temp sensor threshold

    } // end of CPU0 scope
} // end of SSDT
//
// CPU1 3.0 Thermal Model SSDT
//
DefinitionBlock (
    "CPU1SSDT.aml",
    "OEM1",
    0x01,
    "PmRef",
    "CPU1",
    0x3000
    )
{
    External(\_SB.CPU1, DeviceObj)
    External(\_SB.PCI0.ISA0.TZ0, ThermalZoneObj)

    Scope(\_SB.CPU1)
    {
       //
       // Add the objects required for 3.0 extended thermal support
       //
       // Create a region and fields for thermal support; the platform
       // fills in the values and traps on writes to enable hysteresis.
       // The Operation Region location is invalid
        OperationRegion(CP01, SystemIO, 0x00000008, 0xA)
       Field(CP01, ByteAcc, Lock, Preserve) {
           SCP,   1,     // thermal policy (passive/active)
           RTV,   1,     // absolute or relative temperature
           ,      6,     // reserved
           AC0,   16,    // active cooling temp
           PSV,   16,     // passive cooling temp
           CRT,   16,    // critical temp
           TPT,   16,    // Temp trip point crossed
           TST,   8      // Temp sensor threshold
       }

       Method(_TZM, 0) { Return(\_SB.PCI0.ISA0.TZ0) } // thermal zone member

       // Some thermal zone methods are now located under the
       // thermal device participating in the 3.0 thermal model.
       // These methods provide device specific thermal information
    Method(_SCP, 1) { Store (Arg0, \_SB.CPU1.SCP) }   // set cooling mode
    Method(_RTV) { Return (\_SB.CPU1.RTV) }        // absolute or relative temp
    Method(_AC0) { Return (\_SB.CPU1.AC0) }        // active cooling (fan) temp
    Method(_PSV) { Return (\_SB.CPU1.PSV) }        // passive cooling temp
    Method(_CRT) { Return (\_SB.CPU1.CRT) }        // critical temp
    Name(_TC1, 4)                                  // thermal constant 1 (INVALID)
    Name(_TC2, 3)                                  // thermal constant 2 (INVALID)
    Method(_TPT, 1) { Store (Arg0, \_SB.CPU1.TPT)} // trip point temp
    Method(_TST) { Return (\_SB.CPU1.TST) }        // temp sensor threshold

    } // end of CPU1 scope
} // end of SSDT

12 ACPI Embedded Controller Interface Specification
ACPI defines a standard hardware and software communications interface between an OS driver and an embedded controller. This allows any OS to provide a standard driver that can directly communicate with an embedded controller in the system, thus allowing other drivers within the system to communicate with and use the resources of system embedded controllers. This in turn enables the OEM to provide platform features that the OS OSPM and applications can take advantage of.
ACPI also defines a standard hardware and software communications interface between an OS driver and an Embedded Controller-based SMB-HC (EC-SMB-HC).
The ACPI standard supports multiple embedded controllers in a system, each with its own resources. Each embedded controller has a flat byte-addressable I/O space, currently defined as 256 bytes. Features implemented in the embedded controller have an event "query" mechanism that allows feature hardware implemented by the embedded controller to gain the attention of an OS driver or ASL/AML code handler. The interface has been specified to work on the most popular embedded controllers on the market today, only requiring changes in the way the embedded controller is "wired" to the host interface.
Two interfaces are specified:
· A private interface, exclusively owned by the embedded controller driver.
· A shared interface, used by the embedded controller driver and some other driver.
This interface is separate from the traditional PC keyboard controller. Some OEMs might choose to implement the ACPI Embedded Controller Interface (ECI) within the same embedded controller as the keyboard controller function, but the ECI requires its own unique host resources (interrupt event and access registers).
This interface does support sharing the ECI with an inter-environment interface (such as SMI) and relies on the ACPI-defined "Global Lock" protocol. For information about the Global Lock interface, see section 5.2.10.1, "Global Lock." Both the shared and private EC interfaces are described in the following sections.
The ECI has been designed such that a platform can use it in either the legacy or ACPI modes with minimal changes between the two operating environments. This is to encourage standardization for this interface to enable faster development of platforms as well as opening up features within these controllers to higher levels of software.
12.1 Embedded Controller Interface Description
Embedded controllers are the general class of microcontrollers used to support OEM-specific implementations. The ACPI specification supports embedded controllers in any platform design, as long as the microcontroller conforms to one of the models described in this section. The embedded controller is a unique feature in that it can perform complex low-level functions through a simple interface to the host microprocessor(s).
Although there is a large variety of microcontrollers in the market today, the most commonly used embedded controllers include a host interface that connects the embedded controller to the host data bus, allowing bi-directional communications. A bi-directional interrupt scheme reduces the host processor latency in communicating with the embedded controller.

Currently, the most common host interface architecture incorporated into microcontrollers is modeled after the standard IA-PC architecture keyboard controller. This keyboard controller is accessed at 0x60 and 0x64 in system I/O space. Port 0x60 is termed the data register, and allows bi-directional data transfers to and from the host and embedded controller. Port 0x64 is termed the command/status register; it returns port status information upon a read, and generates a command sequence to the embedded controller upon a write. This same class of controllers also includes a second decode range that shares the same properties as the keyboard interface by having a command/status register and a data register. The following diagram graphically depicts this interface.

Figure 12-1 Shared Interface
The diagram above depicts the general register model supported by the ACPI Embedded Controller Interface.

The first method uses an embedded controller interface shared between OSPM and the system management code, which requires the Global Lock semaphore overhead to arbitrate ownership. The second method is a dedicated embedded controller decode range for sole use by OSPM driver following diagram illustrates the embedded controller architecture that includes a dedicated ACPI interface.

Figure 12-2 Private Interface

The private interface allows OSPM to communicate with the embedded controller without the additional software overhead associated with using the Global Lock. Several common system configurations can provide the additional embedded controller interfaces:
·      Non-shared embedded controller. This will be the most common case where there is no need for the system management handler to communicate with the embedded controller when the system transitions to ACPI mode. OSPM processes all normal types of system management events, and the system management handler does not need to take any actions.
·      Integrated keyboard controller and embedded controller. This provides three host interfaces as described earlier by including the standard keyboard controller in an existing component (chip set, I/O controller) and adding a discrete, standard embedded controller with two interfaces for system management activities.
·      Standard keyboard controller and embedded controller. This provides three host interfaces by providing a keyboard controller as a distinct component, and two host interfaces are provided in the embedded controller for system management activities.
·      Two embedded controllers. This provides up to four host interfaces by using two embedded controllers; one controller for system management activities providing up to two host interfaces, and one controller for keyboard controller functions providing up to two host interfaces.
·      Embedded controller and no keyboard controller. Future platforms might provide keyboard functionality through an entirely different mechanism, which would allow for two host interfaces in an embedded controller for system management activities.
To handle the general embedded controller interface (as opposed to a dedicated interface) model, a method is available to make the embedded controller a shareable resource between multiple tasks running under the operating system's control and the system management interrupt handler. This method, as described in this section, requires several changes:
·      Additional external hardware
·      Embedded controller firmware changes
·      System management interrupt handler firmware changes
·      Operating software changes
Access to the shared embedded controller interface requires additional software to arbitrate between the operating system's use of the interface and the system management handler's use of the interface. This is done using the Global Lock as described in section 5.2.10.1, "Global Lock."
This interface sharing protocol also requires embedded controller firmware changes, in order to ensure that collisions do not occur at the interface. A collision could occur if a byte is placed in the system output buffer and an interrupt is then generated. There is a small window of time when the incorrect recipient could receive the data. This problem is resolved by ensuring that the firmware in the embedded controller does not place any data in the output buffer until it is requested by OSPM or the system management handler.
More detailed algorithms and descriptions are provided in the following sections.
12.2   Embedded Controller Register Descriptions
The embedded controller contains three registers at two address locations: EC_SC and EC_DATA. The EC_SC, or Embedded Controller Status/Command register, acts as two registers: a status register for reads to this port and a command register for writes to this port. The EC_DATA (Embedded Controller Data register) acts as a port for transferring data between the host CPU and the embedded controller.

12.2.1 Embedded Controller Status, EC_SC (R)
This is a read-only register that indicates the current status of the embedded controller interface.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
IGN	SMI_EVT	SCI_EVT	BURST	CMD	IGN	IBF	OBF

Where:

IGN:	Ignored
SMI_EVT:	1 – Indicates SMI event is pending (requesting SMI query).
	0 – No SMI events are pending.
SCI_EVT:	1 – Indicates SCI event is pending (requesting SCI query).
	0 – No SCI events are pending.
BURST:	1 – Controller is in burst mode for polled command processing.
	0 – Controller is in normal mode for interrupt-driven command processing.
CMD:	1 – Byte in data register is a command byte (only used by controller).
	0 – Byte in data register is a data byte (only used by controller).
IBF:	1 – Input buffer is full (data ready for embedded controller).
	0 – Input buffer is empty.
OBF:	1 – Output buffer is full (data ready for host).
	0 – Output buffer is empty.

The Output Buffer Full (OBF) flag is set when the embedded controller has written a byte of data into the command or data port but the host has not yet read it. After the host reads the status byte and sees the OBF flag set, the host reads the data port to get the byte of data that the embedded controller has written. After the host reads the data byte, the OBF flag is cleared automatically by hardware. This signals the embedded controller that the data has been read by the host and the embedded controller is free to write more data to the host.
The Input Buffer Full (IBF) flag is set when the host has written a byte of data to the command or data port, but the embedded controller has not yet read it. After the embedded controller reads the status byte and sees the IBF flag set, the embedded controller reads the data port to get the byte of data that the host has written. After the embedded controller reads the data byte, the IBF flag is automatically cleared by hardware. This is the signal to the host that the data has been read by the embedded controller and that the host is free to write more data to the embedded controller.
The SCI event (SCI_EVT) flag is set when the embedded controller has detected an internal event that requires the operating system's attention. The embedded controller sets this bit in the status register, and generates an SCI to OSPM. OSPM needs this bit to differentiate command-complete SCIs from notification SCIs. OSPM uses the query command to request the cause of the SCI_EVT and take action. For more information, see section 13.3, "Embedded Controller Command Set.")

The SMI event (SMI_EVT) flag is set when the embedded controller has detected an internal event that requires the system management interrupt handler's attention. The embedded controller sets this bit in the status register before generating an SMI.
The Burst (BURST) flag indicates that the embedded controller has received the burst enable command from the host, has halted normal processing, and is waiting for a series of commands to be sent from the host. This allows OSPM or system management handler to quickly read and write several bytes of data at a time without the overhead of SCIs between the commands.
12.2.2   Embedded Controller Command, EC_SC (W)
This is a write-only register that allows commands to be issued to the embedded controller. Writes to this port are latched in the input data register and the input buffer full flag is set in the status register. Writes to this location also cause the command bit to be set in the status register. This allows the embedded controller to differentiate the start of a command sequence from a data byte write operation.
12.2.3   Embedded Controller Data, EC_DATA (R/W)
This is a read/write register that allows additional command bytes to be issued to the embedded controller, and allows OSPM to read data returned by the embedded controller. Writes to this port by the host are latched in the input data register, and the input buffer full flag is set in the status register. Reads from this register return data from the output data register and clear the output buffer full flag in the status register.
12.3   Embedded Controller Command Set
The embedded controller command set allows OSPM to communicate with the embedded controllers. ACPI defines the commands and their byte encodings for use with the embedded controller that are shown in the following table.
Table 12-1   Embedded Controller Commands

Embedded Controller Command	Command Byte Encoding
Read Embedded Controller (RD_EC)	0x80
Write Embedded Controller (WR_EC)	0x81
Burst Enable Embedded Controller (BE_EC)	0x82
Burst Disable Embedded Controller (BD_EC)	0x83
Query Embedded Controller (QR_EC)	0x84

12.3.1 Read Embedded Controller, RD_EC (0x80)
This command byte allows OSPM to read a byte in the address space of the embedded controller. This command byte is reserved for exclusive use by OSPM, and it indicates to the embedded controller to generate SCIs in response to related transactions (that is, IBF=0 or OBF=1 in the EC Status Register), rather than SMIs. This command consists of a command byte written to the Embedded Controller Command register (EC_SC), followed by an address byte written to the Embedded Controller Data register (EC_DATA). The embedded controller then returns the byte at the addressed location. The data is read at the data port after the OBF flag is set.

12.3.2   Write Embedded Controller, WR_EC (0x81)
This command byte allows OSPM to write a byte in the address space of the embedded controller. This command byte is reserved for exclusive use by OSPM, and it indicates to the embedded controller to generate SCIs in response to related transactions (that is, IBF=0 or OBF=1 in the EC Status Register), rather than SMIs. This command allows OSPM to write a byte in the address space of the embedded controller. It consists of a command byte written to the Embedded Controller Command register (EC_SC), followed by an address byte written to the Embedded Controller Data register (EC_DATA), followed by a data byte written to the Embedded Controller Data Register (EC_DATA); this is the data byte written at the addressed location.
12.3.3   Burst Enable Embedded Controller, BE_EC (0x82)
This command byte allows OSPM to request dedicated attention from the embedded controller and (except for critical events) prevents the embedded controller from doing tasks other than receiving command and data from the host processor (either the system management interrupt handler or OSPM). This command is an optimization that allows the host processor to issue several commands back to back, in order to reduce latency at the embedded controller interface. When the controller is in the burst mode, it should transition to the burst disable state if the host does not issue a command within the following guidelines:
·      First Access – 400 microseconds
·      Subsequent Accesses – 50 microseconds each
·      Total Burst Time – 1 millisecond
In addition, the embedded controller can disengage the burst mode at any time to process a critical event. If the embedded controller disables burst mode for any reason other than the burst disable command, it should generate an SCI to OSPM to indicate the change.
While in burst mode, the embedded controller follows these guidelines for OSPM driver:
SCIs are generated as normal, including IBF=0 and OBF=1.
Accesses should be responded to within 50 microseconds.
Burst mode is entered in the following manner:
OSPM driver writes the Burst Enable Embedded Controller, BE_EC (0x82) command byte and then the Embedded Controller will prepare to enter the Burst mode. This includes processing any routine activities such that it should be able to remain dedicated to OSPM interface for ~ 1 microsecond.
The Embedded Controller sets the Burst bit of the Embedded Controller Status Register, puts the Burst Acknowledge byte (0x90) into the SCI output buffer, sets the OBF bit, and generates an SCI to signal OSPM that it is in Burst mode.
Burst mode is exited the following manner:
OSPM driver writes the Burst Disable Embedded Controller, BD_EC (0x83) command byte and then the Embedded Controller will exit Burst mode by clearing the Burst bit in the Embedded Controller Status register and generating an SCI signal (due to IBF=0).
The Embedded Controller clears the Burst bit of the Embedded Controller Status Register.
12.3.4   Burst Disable Embedded Controller, BD_EC (0x83)
This command byte releases the embedded controller from a previous burst enable command and allows it to resume normal processing. This command is sent by OSPM or system management interrupt handler after it has completed its entire queued command sequence to the embedded controller.

12.3.5   Query Embedded Controller, QR_EC (0x84)
OSPM driver sends this command when the SCI_EVT flag in the EC_SC register is set. When the embedded controller has detected a system event that must be communicated to OSPM, it first sets the SCI_EVT flag in the EC_SC register, generates an SCI, and then waits for OSPM to send the query (QR_EC) command. OSPM detects the embedded controller SCI, sees the SCI_EVT flag set, and sends the query command to the embedded controller. Upon receipt of the QR_EC command byte, the embedded controller places a notification byte with a value between 0-255, indicating the cause of the notification. The notification byte indicates which interrupt handler operation should be executed by OSPM to process the embedded controller SCI. The query value of zero is reserved for a spurious query result and indicates "no outstanding event."
12.4   SMBus Host Controller Notification Header (Optional), OS_SMB_EVT
This query command notification header is the special return code that indicates events with an SMBus controller implemented within an embedded controller. These events include:
·      Command completion
·      Command error
·      Alarm reception
The actual notification value is declared in the EC-SMB-HC device object in the ACPI Namespace.
12.5   Embedded Controller Firmware
The embedded controller firmware must obey the following rules in order to be ACPI-compatible:
· SMI Processing. Although it is not explicitly stated in the command specification section, a shared embedded controller interface has a separate command set for communicating with each environment it plans to support. In other words, the embedded controller knows which environment is generating the command request, as well as which environment is to be notified upon event detection, and can then generate the correct interrupts and notification values. This implies that a system management handler uses commands that parallel the functionality of all the commands for ACPI including query, read, write, and any other implemented specific commands.
· SCI/SMI Task Queuing. If the system design is sharing the interface between both a system management interrupt handler and OSPM, the embedded controller should always be prepared to queue a notification if it receives a command. The embedded controller only sets the appropriate event flag in the status (EC_SC) register if the controller has detected an event that should be communicated to the OS or system management handler embedded controller must be able to field commands from either environment without loss of the notification event. At some later time, the OS or system management handler issues a query command to the embedded controller to request the cause of the notification event.
· Notification Management. The use of the embedded controller means using the query (QR_EC) command to notify OSPM of system events requiring action. If the embedded controller is shared with the operating system, the SMI handler uses the SMI_EVT flag and an SMI query command (not defined in this document) to receive the event notifications. The embedded controller doesn't place event notifications into the output buffer of a shared interface unless it receives a query command from OSPM or the system management interrupt handler.

12.6 Interrupt Model
The EC Interrupt Model uses pulsed interrupts to speed the clearing process. The Interrupt is firmware generated using an EC general-purpose output and has the waveform shown in Figure 12-3. The embedded controller SCI is always wired directly to a GPE input, and OSPM driver treats this as an edge event (the EC SCI GPE cannot be shared).

Figure 12-3   EC Interrupt Waveform
12.6.1   Event Interrupt Model
The embedded controller must generate SCIs for the events listed in the following table.
Table 12-2   Events for Which Embedded Controller Must Generate SCIs

Event	Description
IBF=0	Signals that the embedded controller has read the last command or data from the input buffer and the host is free to send more data.
OBF=1	Signals that the embedded controller has written a byte of data into the output buffer and the host is free to read the returned data.
SCI_EVT=1	Signals that the embedded controller has detected an event that requires OS attention. OSPM should issue a query (QR_EC) command to find the cause of the event.

12.6.2 Command Interrupt Model
The embedded controller must generate SCIs for commands as follows:

· Read Command (3 Bytes)

Byte #1	(Command byte Header)	Interrupt on IBF=0
Byte #2	(Address byte to read)	No Interrupt
Byte #3	(Data read to host)	Interrupt on OBF=1

· Write Command (3 Bytes)

Byte #1	(Command byte Header)	Interrupt on IBF=0
Byte #2	(Address byte to write)	Interrupt on IBF=0
Byte #3	(Data to read )	Interrupt on IBF=0

· Query Command (2 Bytes)

Byte #1	(Command byte Header)	No Interrupt
Byte #2	(Query value to host)	Interrupt on OBF=1

· Burst Enable Command (2 Bytes)

Byte #1	(Command byte Header)	No Interrupt
Byte #2	(Burst acknowledge byte)	Interrupt on OBF=1

· Burst Disable Command (1 Byte)

Byte #1

(Command byte Header)

Interrupt on IBF=0

12.7   Embedded Controller Interfacing Algorithms
To initiate communications with the embedded controller, OSPM or system management handler acquires ownership of the interface. This ownership is acquired through the use of the Global Lock (described in section 5.2.10.1, "Global Lock"), or is owned by default by OSPM as a non-shared resource (and the Global Lock is not required for accessibility).
After ownership is acquired, the protocol always consists of the passing of a command byte. The command byte will indicate the type of action to be taken. Following the command byte, zero or more data bytes can be exchanged in either direction. The data bytes are defined according to the command byte that is transferred.
The embedded controller also has two status bits that indicate whether the registers have been read. This is used to ensure that the host or embedded controller has received data from the embedded controller or host. When the host writes data to the command or data register of the embedded controller, the input buffer flag (IBF) in the status register is set within 1 microsecond. When the embedded controller reads this data from the input buffer, the input buffer flag is reset. When the embedded controller writes data into the output buffer, the output buffer flag (OBF) in the status register is set. When the host processor reads this data from the output buffer, the output buffer flag is reset.
12.8   Embedded Controller Description Information
Certain aspects of the embedded controller's operation have OEM-definable values associated with them. The following is a list of values that are defined in the software layers of the ACPI specification:
·      Status flag indicating whether the interface requires the use of the Global Lock.
·      Bit position of embedded controller interrupt in general-purpose status register.
·      Decode address for command/status register.
·      Decode address for data register.
·      Base address and query value of any EC-SMBus controller.
For implementation details of the above listed information, see sections 12.11, "Defining an Embedded Controller Device in ACPI Namespace," and 12.12, "Defining an EC SMBus Host Controller in ACPI Namespace."
An embedded controller will require the inclusion of the GLK method in its ACPI namespace if potentially contentious accesses to device resources are performed by non-OS code. See section 6.5.7, "_GLK (Global Lock)" for details about the _GLK method.

12.9   SMBus Host Controller Interface via Embedded Controller
This section specifies a standard interface that an ACPI-compatible OS can use to communicate with embedded controller-based SMBus host controllers (EC-SMB-HC). This interface allows the host processor (under control of OSPM) to manage devices on the SMBus. Typical devices residing on the SMBus include Smart Batteries, Smart Battery Chargers, contrast/backlight control, and temperature sensors.
The EC-SMB-HC interface consists of a block of registers that reside in embedded controller space. These registers are used by software to initiate SMBus transactions and receive SMBus notifications. By using a well-defined register set, OS software can be written to operate with any vendor's embedded controller hardware.
Certain SMBus segments have special requirements that the host controller filters certain SMBus commands (for example, to prevent an errant application or virus from potentially damaging the battery subsystem). This is most easily accomplished by implementing the host interface controller through an embedded controller—as embedded controller can easily filter out potentially problematic commands.
Notice that an EC-SMB-HC interface will require the inclusion of the GLK method in its ACPI namespace if potentially contentious accesses to device resources are performed by non-OS code. See section 6.5.7, "_GLK (Global Lock)" for details on using the _GLK method.
12.9.1   Register Description
The EC-SMBus host interface is a flat array of registers that are arranged sequentially in the embedded controller address space.
12.9.1.1   Status Register, SMB_STS
This register indicates general status on the SMBus. This includes SMB-HC command completion status, alarm received status, and error detection status (the error codes are defined later in this section). This register is cleared to zeroes (except for the ALRM bit) whenever a new command is issued using a write to the protocol (SMB_PRTCL) register. This register is always written with the error code before clearing the protocol register SMB-HC query event (that is, an SMB-HC interrupt) is raised after the clearing of the protocol register.
Note: OSPM must ensure the ALRM bit is cleared after it has been serviced by writing '00' to the SMB_STS register.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
DONE	ALRM	RES			STATUS

Where:

DONE:	Indicates the last command has completed and no error.
ALRM:	Indicates an SMBus alarm message has been received.
RES:	Reserved
STATUS:	Indicates SMBus communication status for one of the reasons listed in the following table.

Table 12-3 SMBus Status Codes

Status Code	Name	Description
00h	SMBus OK	Indicates the transaction has been successfully completed.
07h	SMBus Unknown Failure	Indicates failure because of an unknown SMBus error.
10h	SMBus Device Address Not Acknowledged	Indicates the transaction failed because the slave device address was not acknowledged.
11h	SMBus Device Error Detected	Indicates the transaction failed because the slave device signaled an error condition.
12h	SMBus Device Command Access Denied	Indicates the transaction failed because the SMBus host does not allow the specific command for the device being addressed. For example, the SMBus host might not allow a caller to adjust the Smart Battery Charger's output.
13h	SMBus Unknown Error	Indicates the transaction failed because the SMBus host encountered an unknown error.
17h	SMBus Device Access Denied	Indicates the transaction failed because the SMBus host does not allow access to the device addressed. For example, the SMBus host might not allow a caller to directly communicate with an SMBus device that controls the system's power planes.
18h	SMBus Timeout	Indicates the transaction failed because the SMBus host detected a timeout on the bus.
19h	SMBus Host Unsupported Protocol	Indicates the transaction failed because the SMBus host does not support the requested protocol.
1Ah	SMBus Busy	Indicates that the transaction failed because the SMBus host reports that the SMBus is presently busy with some other transaction example, the Smart Battery might be sending charging information to the Smart Battery Charger.
1Fh	SMBus PEC (CRC-8) Error	Indicates that a Packet Error Checking (PEC) error occurred during the last transaction.

All other error codes are reserved.
12.9.1.2 Protocol Register, SMB_PRTCL

This register determines the type of SMBus transaction generated on the SMBus. In addition to indicating the protocol type to the SMB-HC, a write to this register initiates the transaction on the SMBus. Notice that bit 7 of the protocol value is used to indicate whether packet error checking should be employed. A value of 1 (one) in this bit indicates that PEC format should be used for the specified protocol, and a value of 0 (zero) indicates the standard (non-PEC) format should be used.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
PEC	PROTOCOL

Where:

PROTOCOL:	0x00 – Controller Not In Use
	0x01 – Reserved
	0x02 – Write Quick Command
	0x03 – Read Quick Command
	0x04 – Send Byte
	0x05 – Receive Byte
	0x06 – Write Byte
	0x07 – Read Byte
	0x08 – Write Word
	0x09 – Read Word
	0x0A – Write Block
	0x0B – Read Block
	0x0C – Process Call
	0x0D – Block Write-Block Read Process Call

For example, the protocol value of 0x09 would be used to communicate to a device that supported the standard read word protocol. If this device also supported packet error checking for this protocol, a value of 0x89 (read word with PEC) could optionally be used. See the SMBus specification for more information on packet error checking.
When OSPM initiates a new command such as write to the SMB_PRTCL register, the SMBus controller first updates the SMB_STS register and then clears the SMB_PRTCL register. After the SMB_PRTCL register is cleared, the host controller query value is raised.
All other protocol values are reserved.
12.9.1.3 Address Register, SMB_ADDR
This register contains the 7-bit address to be generated on the SMBus. This is the first byte to be sent on the SMBus for all of the different protocols.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
ADDRESS (A6:A0)							RES

Where:

RES:	Reserved
ADDRESS:	7-bit SMBus address. This address is not zero aligned (in other words, it is only a 7-bit address (A6:A0) that is aligned from bit 1-7).

12.9.1.4 Command Register, SMB_CMD
This register contains the command byte that will be sent to the target device on the SMBus and is used for the following protocols: send byte, write byte, write word, read byte, read word, process call, block read and block write. It is not used for the quick commands or the receive byte protocol, and as such, its value is a "don't care" for those commands.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
COMMAND

Where:

COMMAND:

Command byte to be sent to SMBus device.

12.9.1.5 Data Register Array, SMB_DATA[i], i=0-31

This bank of registers contains the remaining bytes to be sent or received in any of the different protocols that can be run on the SMBus. The SMB_DATA[i] registers are defined on a per-protocol basis and, as such, provide efficient use of register space.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
DATA

Where:

DATA:

One byte of data to be sent or received (depending upon protocol).

12.9.1.6 Block Count Register, SMB_BCNT
This register contains the number of bytes of data present in the SMB_DATA[i] registers preceding any write block and following any read block transaction. The data size is defined on a per protocol basis.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
RES			BCNT

12.9.1.7 Alarm Address Register, SMB_ALRM_ADDR
This register contains the address of an alarm message received by the host controller, at slave address 0x8, from the SMBus master that initiated the alarm. The address indicates the slave address of the device on the SMBus that initiated the alarm message. The status of the alarm message is contained in the SMB_ALRM_DATAx registers. Once an alarm message has been received, the SMB-HC will not receive additional alarm messages until the ALRM status bit is cleared.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
ADDRESS (A6:A0)							RES

Where:

RES:	Reserved
ADDRESS:	Slave address (A6:A0) of the SMBus device that initiated the SMBus alarm message.

12.9.1.8 Alarm Data Registers, SMB_ALRM_DATA[0], SMB_ALRM_DATA[1]
These registers contain the two data bytes of an alarm message received by the host controller, at slave address 0x8, from the SMBus master that initiated the alarm. These data bytes indicate the specific reason for the alarm message, such that OSPM can take actions. Once an alarm message has been received, the SMB-HC will not receive additional alarm messages until the ALRM status bit is cleared.

Bit7	Bit6	Bit5	Bit4	Bit3	Bit2	Bit1	Bit0
DATA (D7:D0)

Where:

DATA:

Data byte received in alarm message.

The alarm address and alarm data registers are not read by OSPM until the alarm status bit is set. OSPM driver then reads the 3 bytes, and clears the alarm status bit to indicate that the alarm registers are now available for the next event.
12.9.2 Protocol Description
This section describes how to initiate the different protocols on the SMBus through the interface described in section 13.9.1, "Register Descriptions." The registers should all be written with the appropriate values before writing the protocol value that starts the SMBus transaction. All transactions can be completed in one pass.
12.9.2.1 Write Quick
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_PRTCL:	Write 0x02 to initiate the write quick protocol.

Data Returned:

SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.2 Read Quick
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_PRTCL:	Write 0x03 to initiate the read quick protocol.

Data Returned:

SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.3 Send Byte
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_PRTCL:	Write 0x04 to initiate the send byte protocol, or 0x84 to initiate the send byte protocol with PEC.

Data Returned:

SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.4 Receive Byte
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_PRTCL:	Write 0x05 to initiate the receive byte protocol, or 0x85 to initiate the receive byte protocol with PEC.

Data Returned:

SMB_DATA[0]:	Data byte received.
SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.5 Write Byte
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_DATA[0]:	Data byte to be sent.
SMB_PRTCL:	Write 0x06 to initiate the write byte protocol, or 0x86 to initiate the write byte protocol with PEC.

Data Returned:

SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.6 Read Byte
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_PRTCL:	Write 0x07 to initiate the read byte protocol, or 0x87 to initiate the read byte protocol with PEC.

Data Returned:

SMB_DATA[0]:	Data byte received.
SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.7 Write Word
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_DATA[0]:	Low data byte to be sent.
SMB_DATA[1]:	High data byte to be sent.
SMB_PRTCL:	Write 0x08 to initiate the write word protocol, or 0x88 to initiate the write word protocol with PEC.

Data Returned:

SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.8 Read Word
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_PRTCL:	Write 0x09 to initiate the read word protocol, or 0x89 to initiate the read word protocol with PEC.

Data Returned:

SMB_DATA[0]:	Low data byte received.
SMB_DATA[1]:	High data byte received.
SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.9 Write Block
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_DATA[0-31]:	Data bytes to write (1-32).
SMB_BCNT:	Number of data bytes (1-32) to be sent.
SMB_PRTCL:	Write 0x0A to initiate the write block protocol, or 0x8A to initiate the write block protocol with PEC.

Data Returned:

SMB_PRTCL:	0x00 to indicate command completion.
SMB_STS:	Status code for transaction.

12.9.2.10 Read Block
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_PRTCL:	Write 0x0B to initiate the read block protocol, or 0x8B to initiate the read block protocol with PEC.

Data Returned:

SMB_BCNT:	Number of data bytes (1-32) received.
SMB_DATA[0-31]:	Data bytes received (1-32).
SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.11 Process Call
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_DATA[0]:	Low data byte to be sent.
SMB_DATA[1]:	High data byte to be sent.
SMB_PRTCL:	Write 0x0C to initiate the process call protocol, or 0x8C to initiate the process call protocol with PEC.

Data Returned:

SMB_DATA[0]:	Low data byte received.
SMB_DATA[1]:	High data byte received.
SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

12.9.2.12 Block Write-Block Read Process Call
Data Sent:

SMB_ADDR:	Address of SMBus device.
SMB_CMD:	Command byte to be sent.
SMB_DATA[0-31]:	Data bytes to write (1-31).
SMB_BCNT:	Number of data bytes (1-31) to be sent.
SMB_PRTCL:	Write 0x0D to initiate the write block-read block process call protocol, or 0x8D to initiate the write block-read block process call protocol with PEC.

Data Returned:

SMB_BCNT:	Number of data bytes (1-31) received.
SMB_DATA[0-31]:	Data bytes received (1-31).
SMB_STS:	Status code for transaction.
SMB_PRTCL:	0x00 to indicate command completion.

Note: The following restrictions apply: The aggregate data length of the write and read blocks must not exceed 32 bytes and each block (write and read) must contain at least 1 byte of data.
12.9.3 SMBus Register Set
The register set for the SMB-HC has the following format. All registers are 8 bit.
Table 12-4 SMB EC Interface

LOCATION	REGISTER NAME	DESCRIPTION
BASE+0	SMB_PRTCL	Protocol register
BASE+1	SMB_STS	Status register
BASE+2	SMB_ADDR	Address register
BASE+3	SMB_CMD	Command register
BASE+4	SMB_DATA[0]	Data register zero
BASE+5	SMB_DATA[1]	Data register one
BASE+6	SMB_DATA[2]	Data register two
BASE+7	SMB_DATA[3]	Data register three
BASE+8	SMB_DATA[4]	Data register four
BASE+9	SMB_DATA[5]	Data register five
BASE+10	SMB_DATA[6]	Data register six
BASE+11	SMB_DATA[7]	Data register seven
BASE+12	SMB_DATA[8]	Data register eight
BASE+13	SMB_DATA[9]	Data register nine
BASE+14	SMB_DATA[10]	Data register ten
BASE+15	SMB_DATA[11]	Data register eleven

Table 12-4 SMB EC Interface (continued)

BASE+16	SMB_DATA[12]	Data register twelve
BASE+17	SMB_DATA[13]	Data register thirteen
BASE+18	SMB_DATA[14]	Data register fourteen
BASE+19	SMB_DATA[15]	Data register fifteen
BASE+20	SMB_DATA[16]	Data register sixteen
BASE+21	SMB_DATA[17]	Data register seventeen
BASE+22	SMB_DATA[18]	Data register eighteen
BASE+23	SMB_DATA[19]	Data register nineteen
BASE+24	SMB_DATA[20]	Data register twenty
BASE+25	SMB_DATA[21]	Data register twenty-one
BASE+26	SMB_DATA[22]	Data register twenty-two
BASE+27	SMB_DATA[23]	Data register twenty-three
BASE+28	SMB_DATA[24]	Data register twenty-four
BASE+29	SMB_DATA[25]	Data register twenty-five
BASE+30	SMB_DATA[26]	Data register twenty-six
BASE+31	SMB_DATA[27]	Data register twenty-seven
BASE+32	SMB_DATA[28]	Data register twenty-eight
BASE+33	SMB_DATA[29]	Data register twenty-nine
BASE+34	SMB_DATA[30]	Data register thirty
BASE+35	SMB_DATA[31]	Data register thirty-one
BASE+36	SMB_BCNT	Block Count Register
BASE+37	SMB_ALRM_ADDR	Alarm address
BASE+38	SMB_ALRM_DATA[0]	Alarm data register zero
BASE+39	SMB_ALRM_DATA[1]	Alarm data register one

12.10   SMBus Devices
The embedded controller interface provides the system with a standard method to access devices on the SMBus. It does not define the data and/or access protocol(s) used by any particular SMBus device. Further, the embedded controller can (and probably will) serve as a gatekeeper to prevent accidental or malicious access to devices on the SMBus.
Some SMBus devices are defined by their address and a specification that describes the data and the protocol used to access that data. For example, the Smart Battery System devices are defined by a series of specifications including:
·      Smart Battery Data specification
·      Smart Battery Charger specification
·      Smart Battery Selector specification
·      Smart Battery System Manager specification
The embedded controller can also be used to emulate (in part or totally) any SMBus device.

12.10.1   SMBus Device Access Restrictions
In some cases, the embedded controller interface will not allow access to a particular SMBus device. Some SMBus devices can and do communicate directly between themselves. Unexpected accesses can interfere with their normal operation and cause unpredictable results.
12.10.2   SMBus Device Command Access Restriction
There are cases where part of an SMBus device's commands are public while others are private. Extraneous attempts to access these commands might cause interference with the SMBus device's normal operation.
The Smart Battery and the Smart Battery Charger are good examples of devices that should not have their entire command set exposed Smart Battery commands the Smart Battery Charger to supply a specific charging voltage and charging current. Attempts by anyone to alter these values can cause damage to the battery or the mobile system. To protect the system's integrity, the embedded controller interface can restrict access to these commands by returning one of the following error codes: Device Command Access Denied (0x12) or Device Access Denied (0x17).
12.11   Defining an Embedded Controller Device in ACPI Namespace
An embedded controller device is created using the named device object. The embedded controller's device object requires the following elements:
Table 12-5   Embedded Controller Device Object Control Methods

Object	Description
_CRS	Named object that returns the Embedded Controller's current resource settings. Embedded Controllers are considered static resources; hence only return their defined resources. The embedded controller resides only in system I/O or memory space. The first address region returned is the data port, and the second address region returned is the status/command port for the embedded controller. CRS is a standard device configuration control method defined in section 6.2.1, "_CRS (Current Resource Settings)."
_HID	Named object that provides the Embedded Controller's Plug and Play identifier. This value is set to PNP0C09. _HID is a standard device configuration control method defined in section 6.1.4, "_HID (Hardware ID)."
_GPE	Named Object that evaluates to either an integer or a package. If _GPE evaluates to an integer, the value is the bit assignment of the SCI interrupt within the GPEx_STS register of a GPE block described in the FADT that the embedded controller will trigger. If _GPE evaluates to a package, then that package contains two elements. The first is an object reference to the GPE Block device that contains the GPE register that will be triggered by the embedded controller. The second element is numeric (integer) that specifies the bit assignment of the SCI interrupt within the GPEx_STS register of the GPE Block device referenced by the first element in the package. This control method is specific to the embedded controller.

12.11.1   Example: EC Definition ASL Code
Example ASL code that defines an embedded controller device is shown below:

Device(EC0) {
    // PnP ID
    Name(_HID, EISAID("PNP0C09"))
    // Returns the "Current Resources" of EC
    Name(_CRS,
       ResourceTemplate(){                 // port 0x62 and 0x66
           IO(Decode16, 0x62, 0x62, 0, 1),
           IO(Decode16, 0x66, 0x66, 0, 1)
           }
       )

// Define that the EC SCI is bit 0 of the GP_STS register
    Name(_GPE, 0)

    OperationRegion(ECOR, EmbeddedControl, 0, 0xFF)
    Field(ECOR, ByteAcc, Lock, Preserve) {
       // Field definitions go here
       }
    }
12.12   Defining an EC SMBus Host Controller in ACPI Namespace
An EC-SMB-HC device is defined using the named device object. The EC-SMB- HC's device object requires the following elements:
Table 12-6   EC SMBus HC Device Objects

Object	Description
_HID	Named object that provides the EC-SMB- HC's Plug and Play identifier. This value is be set to ACPI0001. _HID is a standard device configuration control method defined in section 6.1.4, "_HID (Hardware ID)."
_EC	Named object that evaluates to a WORD that defines the SMBus attributes needed by the SMBus driver. _EC is the Embedded Controller Offset Query Control Method. The most significant byte is the address offset in embedded controller space of the SMBus controller; the least significant byte is the query value for all SMBus events.

12.12.1   Example: EC SMBus Host Controller ASL-Code
Example ASL code that defines an SMB-HC from within an embedded controller device is shown below:

Device(EC0)
{
    Name(_HID, EISAID("PNP0C09"))
    Name(_CRS, ResourceTemplate()
    {
       IO(Decode16, 0x62, 0x62, 0, 1), // Status port
       IO(Decode16, 0x66, 0x66, 0, 1) // command port
    })
    Name(_GPE, 0)

    Device (SMB0)
    {
       Name(_HID, "ACPI0001")                  // EC-SMB-HC
       Name(_UID, 0)                       // Unique device identifier
        Name(_EC, 0x2030)         // EC offset 0x20, query bit 0x30
           :
    }

    Device (SMB1)
    {
       Name(_HID, "ACPI0001")                  // EC-SMB-HC
       Name(_UID, 1)                       // Unique device identifier
        Name(_EC, 0x8031)         // EC offset 0x80, query bit 0x31
           :
    }
} // end of EC0

13   A CPI System Management Bus Interface Specification
This section describes the System Management Bus (SMBus) generic address space and the use of this address space to access SMBus devices from AML.
Unlike other address spaces, SMBus operation regions are inherently non-linear, where each offset within an SMBus address space represents a variable-sized (from 0 to 32 bytes) field. Given this uniqueness, SMBus operation regions include restrictions on their field definitions and require the use of an SMBus-specific data buffer for all transactions.
The SMBus interface presented in this section is intended for use with any hardware implementation compatible with the SMBus specification. SMBus hardware is broadly classified as either non-EC–based or EC-based. EC-based SMBus implementations comply with the standard register set defined in section 13, ACPI Embedded Controller Interface Specification."
Non-EC SMBus implementations can employ any hardware interface and are typically used for their cost savings when SMBus security is not required. Non–EC-based SMBus implementations require the development of hardware specific drivers for each OS implementation. See section 13.2, "Declaring SMBus Host Controller Objects," for more information.
Support of the SMBus generic address space by ACPI-compatible operating systems is optional. As such, the Smart Battery System Implementer's Forum (SBS-IF) has defined an SMBus interface based on a standard set of control methods. This interface is documented in the SMBus Control Method Interface Specification, available from the SBS-IF Web site at: http://www.sbs-forum.org/.
13.1   SMBus Overview
SMBus is a two-wire interface based upon the I�C protocol. The SMBus is a low-speed bus that provides positive addressing for devices, as well as bus arbitration. For more information, refer to the complete set of SMBus specifications published by the SBS-IF.
13.1.1   SMBus Slave Addresses
Slave addresses are specified using a 7-bit non-shifted notation. For example, the slave address of the Smart Battery Selector device would be specified as 0x0A (1010b), not 0x14 (10100b) as might be found in other documents. These two different forms of addresses result from the format in which addresses are transmitted on the SMBus.
During transmission over the physical SMBus, the slave address is formatted in an 8-bit block with bits 7-1 containing the address and bit 0 containing the read/write bit. ASL code, on the other hand, presents the slave address simply as a 7-bit value making it the responsibility of the OS (driver) to shift the value if needed. For example, the ASL value would have to be shifted left 1 bit before being written to the SMB_ADDR register in the EC based SMBus as described in section 12.9.1.3, "Address Register, SMB_ADDR."
13.1.2   SMBus Protocols
There are seven possible command protocols for any given SMBus slave device, and a device may use any or all of the protocols to communicate. The protocols and associated access type indicators are listed below. Notice that the protocols values are similar to those defined for the EC-based SMBus in section 12.9.1.2, "Protocol Register, SMB_PRTCL," except that protocol pairs (for example, Read Byte, Write Byte) have been joined.

Table 13-1 SMBus Protocol Types

Value Type Description
0x02	SMBQuick	SMBus Read/Write Quick Protocol
0x04	SMBSendReceive	SMBus Send/Receive Byte Protocol
0x06	SMBByte	SMBus Read/Write Byte Protocol
0x08	SMBWord	SMBus Read/Write Word Protocol
0x0A	SMBBlock	SMBus Read/Write Block Protocol
0x0C	SMBProcessCall	SMBus Process Call Protocol
0x0D	SMBBlockProcessCall	SMBus Write Block-Read Block Process Call Protocol

All other protocol values are reserved.
Notice that bit 7 of the protocol value is used by this interface to indicate to the SMB-HC whether or not packet error checking (PEC) should be employed for a transaction. Packet error checking is described in section 7.4 of the System Management Bus Specification, Version 1.1. This highly desirable capability improves the reliability and robustness of SMBus communications.
The bit encoding of the protocol value is shown below example, the value 0x86 would be used to specify the PEC version of the SMBus Read/Write Byte protocol.

Figure 13-1   Bit Encoding Example
Notice that bit 0 of the protocol value is always zero (even number hexadecimal values). In a manner similar to the slave address, software that implements the SMBus interface is responsible for setting this bit to indicate whether the transaction is a read (for example, Read Byte) or write (for example, Write Byte) operation.
For example, software implanting this interface for EC-SMBus segments would set bit 0 for read transactions. For the SMBByte protocol (0x06), this would result in the value 0x07 being placed into the SMB_PRTCL register (or 0x87 if PEC is requested) for write transactions.
13.1.3   SMBus Status Codes
The use of status codes helps AML determine whether an SMBus transaction was successful. In general, a status code of zero indicates success, while a non-zero value indicates failure. The SMBus interface uses the same status codes defined for the EC-SMBus (see section 12.9.1.1, "Status Register, SMB_STS").
13.1.4   SMBus Command Values
SMBus devices may optionally support up to 256 device-specific commands. For these devices, each command value supported by the device is modeled by this interface as a separate virtual register. Protocols that do not transmit a command value (for example, Read/Write Quick and Send/Receive Byte) are modeled using a single virtual register (with a command value = 0x00).

13.2   Declaring SMBus Host Controller Objects
EC-based SMBus 1.0-compatible HCs should be modeled in the ACPI namespace as described in section 13.12, "Defining an Embedded Controller SMBus Host Controller in ACPI Namespace." An example definition is given below. Using the HID value "ACPI0001" identifies that this SMB-HC is implemented on an embedded controller using the standard SMBus register set defined in section 12.9, SMBus Host Controller Interface via Embedded Controller."

Device (SMB0)
{
    Name(_HID, "ACPI0001")          // EC-based SMBus 1.0 compatible Host Controller
    Name(_EC, 0x2030) // EC offset 0x20, query bit 0x30
    :
}
EC-based SMBus 2.0-compatible host controllers should be defined similarly in the name space as follows:

Device (SMB0)
{
    Name(_HID, "ACPI0005")          // EC-based SMBus 2.0 compatible Host Controller
    Name(_EC, 0x2030) // EC offset 0x20, query bit 0x30
    :
}
Non–EC-based SMB-HCs should be modeled in a manner similar to the EC-based SMBus HC. An example definition is given below. These devices use a vendor-specific hardware identifier (HID) to specify the type of SMB-HC (do not use "ACPI0001" or "ACPI0005"). Using a vendor-specific HID allows the correct software to be loaded to service this segment's SMBus address space.

Device(SMB0)
{
    Name(_HID, "<Vendor-Specific HID>") // Vendor-Specific HID
    :
}
Regardless of the type of hardware, some OS software element (for example, the SMBus HC driver) must register with OSPM to support all SMBus operation regions defined for the segment. This software allows the generic SMBus interface defined in this section to be used on a specific hardware implementation by translating between the conceptual (for example, SMBus address space) and physical (for example, process of writing/reading registers) models. Because of this linkage, SMBus operation regions must be defined immediately within the scope of the corresponding SMBus device.
13.3   Declaring SMBus Devices
The SMBus, as defined by the SMBus 1.0 Specification, is not an enumerable bus. As a result, an SMBus 1.0-compatible SMB-HC driver cannot discover child devices on the SMBus and load the appropriate corresponding device drivers. As such, SMBus 1.0-compatible devices are declared in the ACPI namespace, in like manner to other motherboard devices, and enumerated by OSPM.
The SMBus 2.0 specification adds mechanisms enabling device enumeration on the bus while providing compatibility with existing devices. ACPI defines and associates the "ACPI0005" HID value with an EC-based SMBus 2.0-compatible host controller. OSPM will enumerate SMBus 1.0-compatible devices when declared in the namespace under an SMBus 2.0-compatible host controller.
The responsibility for the definition of ACPI namespace objects, required by an SMBus 2.0-compatible host controller driver to enumerate non–bus-enumerable devices, is relegated to the Smart Battery System Implementers Forum (http://www.sbs-forum.org).
Starting in ACPI 2.0, _ADR is used to associate SMBus devices with their lowest SMBus slave address.

13.4   Declaring SMBus Operation Regions
Each SMBus operation region definition identifies a single SMBus slave address. Operation regions are defined only for those SMBus devices that need to be accessed from AML. As with other regions, SMBus operation regions are only accessible via the Field term (see section 13.5, "Declaring SMBus Fields").
This interface models each SMBus device as having a 256-byte linear address range. Each byte offset within this range corresponds to a single command value (for example, byte offset 0x12 equates to command value 0x12), with a maximum of 256 command values. By doing this, SMBus address spaces appear linear and can be processed in a manner similar to the other address space types.
The syntax for the OperationRegion term (from section 17.5.89, "OperationRegion (Declare Operation Region]") is described below.

OperationRegion (
    RegionName,       // NameString
    RegionSpace, // RegionSpaceKeyword
    Offset,           // TermArg=>Integer
    Length         // TermArg=>Integer
)
Where:
·      RegionName specifies a name for this slave device (for example, "SBD0").
·      RegionSpace must be set to SMBus (operation region type value 0x04).
·      Offset is a word-sized value specifying the slave address and initial command value offset for the target device. The slave address is stored in the high byte and the command value offset is stored in the low byte. For example, the value 0x4200 would be used for an SMBus device residing at slave address 0x42 with an initial command value offset of zero (0).
·      Length is set to the 0x100 (256), representing the maximum number of possible command values, for regions with an initial command value offset of zero (0). The difference of these two values is used for regions with non-zero offsets. For example, a region with an Offset value of 0x4210 would have a corresponding Length of 0xF0 (0x100 minus 0x10).
For example, the Smart Battery Subsystem (illustrated below) consists of the Smart Battery Charger at slave address 0x09, the Smart Battery System Manager at slave address 0x0A, and one or more batteries (multiplexed) at slave address 0x0B. (Notice that Figure 13-2 represents the logical connection of a Smart Battery Subsystem. The actual physical connections of the Smart Battery(s) and the Smart Battery Charger are made through the Smart Battery System Manager.) All devices support the Read/Write Word protocol. Batteries also support the Read/Write Block protocol.

Figure 13-2 Smart Battery Subsystem Devices

The following ASL code shows the use of the OperationRegion term to describe these SMBus devices:

Device (SMB0)
{
    Name(_HID, "ACPI0001")                  // EC-SMBus Host Controller
    Name(_EC, 0x2030)         // EC offset 0x20, query bit 0x30

OperationRegion(SBC0, SMBus, 0x0900, 0x100)       // Smart Battery Charger
OperationRegion(SBS0, SMBus, 0x0A00, 0x100)       // Smart Battery Selector
OperationRegion(SBD0, SMBus, 0x0B00, 0x100)       // Smart Battery Device(s)
    :
}
Notice that these operation regions in this example are defined within the immediate context of the 'owning' EC-SMBus device. Each definition corresponds to a separate slave address (device), and happens to use an initial command value offset of zero (0).
13.5   Declaring SMBus Fields
As with other regions, SMBus operation regions are only accessible via the Field term. Each field element is assigned a unique command value and represents a virtual register on the targeted SMBus device.
The syntax for the Field term (from section 17.5.38, "Event (Declare Event Synchronization Object]") is described below.

Field(
    RegionName,       // NameString=>OperationRegion
    AccessType,       // AccessTypeKeyword
    LockRule,     // LockRuleKeyword
    UpdateRule     // UpdateRuleKeyword – ignored
) {FieldUnitList}
Where:
·      RegionName specifies the operation region name previously defined for the device.
·      AccessType must be set to BufferAcc. This indicates that access to field elements will be done using a region-specific data buffer. For this access type, the field handler is not aware of the data buffer's contents which may be of any size. When a field of this type is used as the source argument in an operation it simply evaluates to a buffer. When used as the destination, however, the buffer is passed bi-directionally to allow data to be returned from write operations. The modified buffer then becomes the execution result of that operation. This is slightly different than the normal case in which the execution result is the same as the value written to the destination. Note that the source is never changed, since it could be a read only object (see section 13.6, "Declaring an SMBus Data Buffer" and section 17.1.5, "Opcode Terms").
·      LockRule indicates if access to this operation region requires acquisition of the Global Lock for synchronization. This field should be set to Lock on system with firmware that may access the SMBus, and NoLock otherwise.
·      UpdateRule is not applicable to SMBus operation regions since each virtual register is accessed in its entirety. This field is ignored for all SMBus field definitions.
SMBus operation regions require that all field elements be declared at command value granularity. This means that each virtual register cannot be broken down to its individual bits within the field definition.
Access to sub-portions of virtual registers can be done only outside of the field definition. This limitation is imposed both to simplify the SMBus interface and to maintain consistency with the physical model defined by the SMBus specification.
SMBus protocols are assigned to field elements using the AccessAs term within the field definition. The syntax for this term (from section 17.1.3, "ASL Root and SecondaryTerms") is described below.

AccessAs(
    AccessType,   //AccessTypeKeyword
    AccessAttribute   //Nothing | ByteConst | AccessAttribKeyword
)
Where:
·      AccessType must be set to BufferAcc.
·      AccessAttribute indicates the SMBus protocol to assign to command values that follow this term section 13.1.2, "SMBus Protocols," for a listing of the SMBus protocol types and values.
An AccessAs term must appear as the first entry in a field definition to set the initial SMBus protocol for the field elements that follow. A maximum of one SMBus protocol may be defined for each field element. Devices supporting multiple protocols for a single command value can be modeled by specifying multiple field elements with the same offset (command value), where each field element is preceded by an AccessAs term specifying an alternate protocol.
For example, the register at command value 0x08 for a Smart Battery device (illustrated below) represents a word value specifying the battery temperature (in degrees Kelvin), while the register at command value 0x20 represents a variable-length (0 to 32 bytes) character string specifying the name of the company that manufactured the battery.

Figure 13-3   Smart Battery Device Virtual Registers
The following ASL code shows the use of the OperationRegion, Field, AccessAs, and Offset terms to represent these Smart Battery device virtual registers:

    OperationRegion(SBD0, SMBus, 0x0B00, 0x0100)
Field(SBD0, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBWord) // Use the SMBWord protocol for the following�
    MFGA, 8,                     // ManufacturerAccess() [command value 0x00]
    RCAP, 8,                     // RemainingCapacityAlarm() [command value 0x01]
    Offset(0x08)                 // Skip to command value 0x08�
    BTMP, 8,                     // Temperature() [command value 0x08]
    Offset(0x20)                 // Skip to command value 0x20�
    AccessAs(BufferAcc, SMBBlock) // Use the SMBBlock protocol for the following�
    MFGN, 8,                     // ManufacturerName() [command value 0x20]
    DEVN, 8                         // DeviceName() [command value 0x21]
}
Notice that command values are equivalent to the field element's byte offset (for example, MFGA=0, RCAP=1, BTMP=8). The AccessAs term indicates which SMBus protocol to use for each command value.
13.6   Declaring and Using an SMBus Data Buffer
The use of a data buffer for SMBus transactions allows AML to receive status and data length values, as well as making it possible to implement the Process Call protocol. As previously mentioned, the BufferAcc access type is used to indicate to the field handler that a region-specific data buffer will be used.
For SMBus operation regions, this data buffer is defined as a fixed-length 34-byte buffer that, if represented using a 'C'-styled declaration, would be modeled as follows:

typedef struct
{
    BYTE       Status;           // Byte 0 of the data buffer
    BYTE       Length;           // Byte 1 of the data buffer
    BYTE[32]   Data;         // Bytes 2 through 33 of the data buffer
}
Where:
·      Status (byte 0) indicates the status code of a given SMBus transaction. See section 14.1.3, "SMBus Status Code," for more information.
·      Length (byte 1) specifies the number of bytes of valid data that exists in the data buffer. Use of this field is only defined for the Read/Write Block protocol, where valid Length values are 0 through 32. For other protocols—where the data length is implied by the protocol—this field is reserved.
·      Data (bytes 2-33) represents a 32-byte buffer, and is the location where actual data is stored.
For example, the following ASL shows the use of the SMBus data buffer for performing transactions to a Smart Battery device. This code is based on the example ASL presented in section 13.5, "Declaring SMBus Fields," which lists the operation region and field definitions for the Smart Battery device.

/* Create the SMBus data buffer */
Name(BUFF, Buffer(34){})            // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, OB1)    // OB1 = Status (Byte)
CreateByteField(BUFF, 0x01, OB2)    // OB2 = Length (Byte)
CreateWordField(BUFF, 0x02, OB3)    // OB3 = Data (Word – Bytes 2 & 3)
CreateField(BUFF, 0x10, 256, OB4)       // OB4 = Data (Block – Bytes 2-33)

/* Read the battery temperature */
Store(BTMP, BUFF)                   // Invoke Read Word transaction
If(LEqual(OB1, 0x00))               // Successful?
{
    // OB3 = Battery temperature in 1/10^th degrees Kelvin
}

/* Read the battery manufacturer name */
Store(MFGN, BUFF)                   // Invoke Read Block transaction
If(LEqual(OB1, 0x00))               // Successful?
{
    // OB2 = Length of the manufacturer name
    // OB4 = Manufacturer name (as a counted string)
}
Notice the use of the CreateField primitives to access the data buffer's sub-elements (Status, Length, and Data), where Data (bytes 2-33) is 'typecast' as both word (OB3) and block (OB4) data.
The example above demonstrates the use of the Store() operator to invoke a Read Block transaction to obtain the name of the battery manufacturer. Evaluation of the source operand (MFGN) results in a 34-byte buffer that gets copied by Store() to the destination buffer (BUFF).

Capturing the results of a write operation, for example to check the status code, requires an additional Store() operator, as shown below.

Store(Store(BUFF, MFGN), BUFF)      // Invoke Write Block transaction
If(LEqual(OB1, 0x00)) {�}               // Transaction successful?

Note that the outer Store() copies the results of the Write Block transaction back into BUFF. This is the nature of BufferAcc's bi-directionality described in section 13.5, "Declaring SMBus Fields" It should be noted that storing (or parsing) the result of an SMBus Write transaction is not required although useful for ascertaining the outcome of a transaction.
SMBus Process Call protocols require similar semantics due to the fact that only destination operands are passed bi-directionally. These transactions require the use of the double-Store() semantics to properly capture the return results.
13.7   Using the SMBus Protocols
This section provides information and examples on how each of the SMBus protocols can be used to access SMBus devices from AML.
13.7.1   Read/Write Quick (SMBQuick)
The SMBus Read/Write Quick protocol (SMBQuick) is typically used to control simple devices using a device-specific binary command (for example, ON and OFF). Command values are not used by this protocol and thus only a single element (at offset 0) can be specified in the field definition. This protocol transfers no data.
The following ASL code illustrates how a device supporting the Read/Write Quick protocol should be accessed:

OperationRegion(SMBD, SMBus, 0x4200, 0x100)    // SMBus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBQuick)           // Use the SMBus Read/Write Quick protocol
    FLD0, 8                                 // Virtual register at command value 0.
}

/* Create the SMBus data buffer */

Name(BUFF, Buffer(34){})            // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, OB1)    // OB1 = Status (Byte)

/* Signal device (e.g. OFF) */
Store(FLD0, BUFF)                   // Invoke Read Quick transaction
If(LEqual(OB1, 0x00)) {�}               // Successful?

/* Signal device (e.g. ON) */
Store(BUFF, FLD0)                   // Invoke Write Quick transaction
In this example, a single field element (FLD0) at offset 0 is defined to represent the protocol's read/write bit. Access to FLD0 will cause an SMBus transaction to occur to the device. Reading the field results in a Read Quick, and writing to the field results in a Write Quick. In either case data is not transferred—access to the register is simply used as a mechanism to invoke the transaction.
13.7.2   Send/Receive Byte (SMBSendReceive)
The SMBus Send/Receive Byte protocol (SMBSendReceive) transfers a single byte of data. Like Read/Write Quick, command values are not used by this protocol and thus only a single element (at offset 0) can be specified in the field definition.
The following ASL code illustrates how a device supporting the Send/Receive Byte protocol should be accessed:

OperationRegion(SMBD, SMBus, 0x4200, 0x100)    // SMBus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBSendReceive) // Use the SMBus Send/Receive Byte protocol
    FLD0, 8                                 // Virtual register at command value 0.
}

/* Create the SMBus data buffer */

Name(BUFF, Buffer(34){})            // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT)       // STAT = Status (Byte)
CreateByteField(BUFF, 0x02, DATA)       // DATA = Data (Byte)

/* Receive a byte of data from the device */
Store(FLD0, BUFF)                   // Invoke a Receive Byte transaction
If(LEqual(STAT, 0x00))                  // Successful?
{
    // DATA = Received byte�
}

/* Send the byte '0x16' to the device */
Store(0x16, DATA)                   // Save 0x16 into the data buffer
Store(BUFF, FLD0)                   // Invoke a Send Byte transaction
In this example, a single field element (FLD0) at offset 0 is defined to represent the protocol's data byte. Access to FLD0 will cause an SMBus transaction to occur to the device. Reading the field results in a Receive Byte, and writing to the field results in a Send Byte.
13.7.3   Read/Write Byte (SMBByte)
The SMBus Read/Write Byte protocol (SMBByte) also transfers a single byte of data. But unlike Send/Receive Byte, this protocol uses a command value to reference up to 256 byte-sized virtual registers.
The following ASL code illustrates how a device supporting the Read/Write Byte protocol should be accessed:

OperationRegion(SMBD, SMBus, 0x4200, 0x100)    // SMBus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBByte)        // Use the SMBus Read/Write Byte protocol
    FLD0, 8,                            // Virtual register at command value 0.
    FLD1, 8,                            // Virtual register at command value 1.
    FLD2, 8                                 // Virtual register at command value 2.
}

/* Create the SMBus data buffer */
Name(BUFF, Buffer(34){})            // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT)       // STAT = Status (Byte)
CreateByteField(BUFF, 0x02, DATA)       // DATA = Data (Byte)

/* Read a byte of data from the device using command value 1 */
Store(FLD1, BUFF)                   // Invoke a Read Byte transaction
If(LEqual(STAT, 0x00))                  // Successful?
{
    // DATA = Byte read from FLD1�
}

/* Write the byte '0x16' to the device using command value 2 */
Store(0x16, DATA)                   // Save 0x16 into the data buffer
Store(BUFF, FLD2)                   // Invoke a Write Byte transaction

In this example, three field elements (FLD0, FLD1, and FLD2) are defined to represent the virtual registers for command values 0, 1, and 2. Access to any of the field elements will cause an SMBus transaction to occur to the device. Reading FLD1 results in a Read Byte with a command value of 1, and writing to FLD2 results in a Write Byte with command value 2.
13.7.4   Read/Write Word (SMBWord)
The SMBus Read/Write Word protocol (SMBWord) transfers 2 bytes of data. This protocol also uses a command value to reference up to 256 word-sized virtual device registers.
The following ASL code illustrates how a device supporting the Read/Write Word protocol should be accessed:

OperationRegion(SMBD, SMBus, 0x4200, 0x100)    // SMBus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBWord)        // Use the SMBus Read/Write Word protocol
    FLD0, 8,                            // Virtual register at command value 0.
    FLD1, 8,                            // Virtual register at command value 1.
    FLD2, 8                                 // Virtual register at command value 2.
}

/* Create the SMBus data buffer */
Name(BUFF, Buffer(34){})            // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT)       // STAT = Status (Byte)
CreateWordField(BUFF, 0x02, DATA)       // DATA = Data (Word)

/* Read two bytes of data from the device using command value 1 */
Store(FLD1, BUFF)                   // Invoke a Read Word transaction
If(LEqual(STAT, 0x00))                  // Successful?
{
    // DATA = Word read from FLD1�
}
/* Write the word '0x5416' to the device using command value 2 */
Store(0x5416, DATA)                 // Save 0x5416 into the data buffer
Store(BUFF, FLD2)                   // Invoke a Write Word transaction
In this example, three field elements (FLD0, FLD1, and FLD2) are defined to represent the virtual registers for command values 0, 1, and 2. Access to any of the field elements will cause an SMBus transaction to occur to the device. Reading FLD1 results in a Read Word with a command value of 1, and writing to FLD2 results in a Write Word with command value 2.
Notice that although accessing each field element transmits a word (16 bits) of data, the fields are listed as 8 bits each. The actual data size is determined by the protocol. Every field element is declared with a length of 8 bits so that command values and byte offsets are equivalent.
13.7.5   Read/Write Block (SMBBlock)
The SMBus Read/Write Block protocol (SMBBlock) transfers variable-sized (0-32 bytes) data. This protocol uses a command value to reference up to 256 block-sized virtual registers.
The following ASL code illustrates how a device supporting the Read/Write Block protocol should be accessed:

OperationRegion(SMBD, SMBus, 0x4200, 0x100)    // SMBus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBBlock)           // Use the SMBus Read/Write Block protocol
    FLD0, 8,                            // Virtual register at command value 0.
    FLD1, 8,                            // Virtual register at command value 1.
    FLD2, 8                                 // Virtual register at command value 2.
}

/* Create the SMBus data buffer */
Name(BUFF, Buffer(34){})            // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT)       // STAT = Status (Byte)
CreateByteField(BUFF, 0x01, SIZE)       // SIZE = Length (Byte)
CreateField(BUFF, 0x10, 256, DATA) // DATA = Data (Block)

/* Read block data from the device using command value 1 */
Store(FLD1, BUFF)                   // Invoke a Read Block transaction
If(LEqual(STAT, 0x00))                  // Successful?
{
    // SIZE = Size (number of bytes) of the block data read from FLD1�
    // DATA = Block data read from FLD1�
}

/* Write the block 'TEST' to the device using command value 2 */
Store("TEST", DATA)                 // Save "TEST" into the data buffer
Store(4, SIZE)                      // Length of valid data in the data buffer
Store(BUFF, FLD2)                   // Invoke a Write Word transaction
In this example, three field elements (FLD0, FLD1, and FLD2) are defined to represent the virtual registers for command values 0, 1, and 2. Access to any of the field elements will cause an SMBus transaction to occur to the device. Reading FLD1 results in a Read Block with a command value of 1, and writing to FLD2 results in a Write Block with command value 2.
13.7.6   Word Process Call (SMBProcessCall)
The SMBus Process Call protocol (SMBProcessCall) transfers 2 bytes of data bi-directionally (performs a Write Word followed by a Read Word as an atomic transaction). This protocol uses a command value to reference up to 256 word-sized virtual registers.
The following ASL code illustrates how a device supporting the Process Call protocol should be accessed:

OperationRegion(SMBD, SMBus, 0x4200, 0x100)    // SMBus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBProcessCall) // Use the SMBus Process Call protocol
    FLD0, 8,                            // Virtual register at command value 0.
    FLD1, 8,                            // Virtual register at command value 1.
    FLD2, 8                                 // Virtual register at command value 2.
}

/* Create the SMBus data buffer */
Name(BUFF, Buffer(34){})            // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT)       // STAT = Status (Byte)
CreateWordField(BUFF, 0x02, DATA)       // DATA = Data (Word)

/* Process Call with input value '0x5416'to the device using command value 1 */
Store(0x5416, DATA)                 // Save 0x5416 into the data buffer
Store(Store(BUFF, FLD1), BUFF)      // Invoke a Process Call transaction
If(LEqual(STAT, 0x00))                  // Successful?
{
    // DATA = Word returned from FLD1�
}
In this example, three field elements (FLD0, FLD1, and FLD2) are defined to represent the virtual registers for command values 0, 1, and 2. Access to any of the field elements will cause an SMBus transaction to occur to the device. Reading or writing FLD1 results in a Process Call with a command value of 1. Notice that unlike other protocols, Process Call involves both a write and read operation in a single atomic transaction. This means that the Data element of the SMBus data buffer is set with an input value before the transaction is invoked, and holds the output value following the successful completion of the transaction.
13.7.7   Block Process Call (SMBBlockProcessCall)
The SMBus Block Write-Read Block Process Call protocol (SMBBlockProcessCall) transfers a block of data bi-directionally (performs a Write Block followed by a Read Block as an atomic transaction). The maximum aggregate amount of data that may be transferred is limited to 32 bytes. This protocol uses a command value to reference up to 256 block-sized virtual registers.
The following ASL code illustrates how a device supporting the Process Call protocol should be accessed:

OperationRegion(SMBD, SMBus, 0x4200, 0x100) // SMbus device at slave address 0x42
Field(SMBD, BufferAcc, NoLock, Preserve)
{
    AccessAs(BufferAcc, SMBBlockProcessCall) // Use the Block Process Call protocol
    FLD0, 8,   // Virtual register representing a command value of 0
    FLD1, 8    // Virtual register representing a command value of 1
}

/* Create the SMBus data buffer as BUFF */
Name(BUFF, Buffer(34)())             // Create SMBus data buffer as BUFF
CreateByteField(BUFF, 0x00, STAT)       // STAT = Status (Byte)
CreateByteField(BUFF, 0x01, SIZE)       // SIZE = Length (Byte)
CreateField(BUFF, 0x10, 256, DATA)      // Data (Block)

/* Process Call with input value "ACPI" to the device using command value 1 */

Store("ACPI", DATA)              // Fill in outgoing data
Store(8, SIZE)                   // Length of the valid data
Store(Store(BUFF, FLD1), BUFF)       // Execute the PC
if (LEqual(STAT, 0x00))          // Test the status
{
/* BUFF now contains information returned from PC */
/* SIZE now equals size of data returned */
}

14   System Address Map Interfaces
This section explains how an ACPI-compatible system conveys its memory resources/type mappings to OSPM. There are three ways for the system to convey memory resources /mappings to OSPM. The first is an INT 15 BIOS interface that is used in IA-PC–based systems to convey the system's initial memory map. EFI enabled systems use the EFI defined GetMemoryMap() boot services function to convey memory resources to the OS loader. These resources must then be conveyed by the OS loader to OSPM. See the EFI specification for more information on EFI services.
Lastly, if memory resources may be added or removed dynamically, memory devices are defined in the ACPI Namespace conveying the resource information described by the memory device (see section 10.12, "Memory Devices").
ACPI defines five address range types; AddressRangeMemory, AddressRangeACPI, AddressRangeNVS, AddressRangeUnusable, and AddressRangeReserved as described in the table below:
Table 14-1   Address Range Types

Value	Mnemonic	Description
1	AddressRangeMemory	This range is available RAM usable by the operating system.
2	AddressRangeReserved	This range of addresses is in use or reserved by the system and must not be used by the operating system.
3	AddressRangeACPI	ACPI Reclaim Memory. This range is available RAM usable by the OS after it reads the ACPI tables.
4	AddressRangeNVS	ACPI NVS Memory. This range of addresses is in use or reserve by the system and must not be used by the operating system. This range is required to be saved and restored across an NVS sleep.
5	AddressRangeUnusuable	This range of address contains memory in which errors have been detected. This range must not be used by the OSPM.
Other	Undefined	Undefined. Reserved for future use. OSPM must treat any range of this type as if the type returned was AddressRangeReserved.

The BIOS can use the AddressRangeReserved address range type to block out various addresses as not suitable for use by a programmable device. Some of the reasons a BIOS would do this are:
·      The address range contains system ROM.
·      The address range contains RAM in use by the ROM.
·      The address range is in use by a memory-mapped system device.
·      The address range is, for whatever reason, unsuitable for a standard device to use as a device memory space.
·      The address range is within an NVRAM device where reads and writes to memory locations are no longer successful, that is, the device was worn out.
Note: OSPM will not save or restore memory reported as AddressRangeReserved or AddressRangeUnusable when transitioning to or from the S4 sleeping state.
14.1   INT 15H, E820H - Query System Address Map
This interface is used in real mode only on IA-PC-based systems and provides a memory map for all of the installed RAM, and of physical memory ranges reserved by the BIOS. The address map is returned through successive invocations of this interface; each returning information on a single range of physical addresses. Each range includes a type that indicates how the range of physical addresses is to be treated by the OSPM.
If the information returned from E820 in some way differs from INT-15 88 or INT-15 E801, the information returned from E820 supersedes the information returned from INT-15 88 or INT-15 E801. This replacement allows the BIOS to return any information that it requires from INT-15 88 or INT-15 E801 for compatibility reasons. For compatibility reasons, if E820 returns any AddressRangeACPI or AddressRangeNVS memory ranges below 16 MB, the INT-15 88 and INT-15 E801 functions must return the top of memory below the AddressRangeACPI and AddressRangeNVS memory ranges.

The memory map conveyed by this interface is not required to reflect any changes in available physical memory that have occurred after the BIOS has initially passed control to the operating system. For example, if memory is added dynamically, this interface is not required to reflect the new system memory configuration.
Table 14-2 Input to the INT 15h E820h Call

EAX	Function Code	E820h
EBX	Continuation	Contains the continuation value to get the next range of physical memory. This is the value returned by a previous call to this routine. If this is the first call, EBX must contain zero.
ES:DI	Buffer Pointer	Pointer to an Address Range Descriptor structure that the BIOS fills in.
ECX	Buffer Size	The length in bytes of the structure passed to the BIOS BIOS fills in the number of bytes of the structure indicated in the ECX register, maximum, or whatever amount of the structure the BIOS implements. The minimum size that must be supported by both the BIOS and the caller is 20 bytes. Future implementations might extend this structure.
EDX	Signature	'SMAP' Used by the BIOS to verify the caller is requesting the system map information to be returned in ES:DI.

Table 14-3 Output from the INT 15h E820h Call

CF	Carry Flag	Non-Carry – Indicates No Error
EAX	Signature	'SMAP.' Signature to verify correct BIOS revision.
ES:DI	Buffer Pointer	Returned Address Range Descriptor pointer. Same value as on input.
ECX	Buffer Size	Number of bytes returned by the BIOS in the address range descriptor. The minimum size structure returned by the BIOS is 20 bytes.
EBX	Continuation	Contains the continuation value to get the next address range descriptor. The actual significance of the continuation value is up to the discretion of the BIOS. The caller must pass the continuation value unchanged as input to the next iteration of the E820 call in order to get the next Address Range Descriptor. A return value of zero means that this is the last descriptor. Note: the BIOS can also indicate that the last descriptor has already been returned during previous iterations by returning the carry flag set. The caller will ignore any other information returned by the BIOS when the carry flag is set.

Table 14-4 Address Range Descriptor Structure

Offset in Bytes	Name	Description
0	BaseAddrLow	Low 32 Bits of Base Address
4	BaseAddrHigh	High 32 Bits of Base Address
8	LengthLow	Low 32 Bits of Length in Bytes
12	LengthHigh	High 32 Bits of Length in Bytes
16	Type	Address type of this range
20	Extended Attributes	See Table 14-5

The BaseAddrLow and BaseAddrHigh together are the 64-bit base address of this range. The base address is the physical address of the start of the range being specified.
The LengthLow and LengthHigh together are the 64-bit length of this range length is the physical contiguous length in bytes of a range being specified.
The Type field describes the usage of the described address range as defined in Table 14-1.
Table 14-5 Extended Attributes for Address Range Descriptor Structure

Bit	Mnemonic	Description
0	AddressRangeEnabled	If clear, the OSPM ignores the Address Range Descriptor. This allows the BIOS to populate the E820 table with a static number of structures but only enable them as necessary
1	AddressRangeNonVolatile	If set, the Address Range Descriptor represents non-volatile memory. Memory reported as non-volatile may require characterization to determine its suitability for use as conventional RAM.
2-31	Reserved	Reserved for future use.

14.2   E820 Assumptions and Limitations
·       The BIOS returns address ranges describing baseboard memory.
·      The BIOS does not return a range description for the memory mapping of PCI devices, ISA Option ROMs, and ISA Plug and Play cards because the OS has mechanisms available to detect them.
·      The BIOS returns chip set-defined address holes that are not being used by devices as reserved.
·      Address ranges defined for baseboard memory-mapped I/O devices, such as APICs, are returned as reserved.
·      All occurrences of the system BIOS are mapped as reserved, including the areas below 1 MB, at 16 MB (if present), and at end of the 4-GB address space.
·      Standard PC address ranges are not reported. For example, video memory at A0000 to BFFFF physical addresses are not described by this function. The range from E0000 to EFFFF is specific to the baseboard and is reported as it applies to that baseboard.
·      All of lower memory is reported as normal memory. The OS must handle standard RAM locations that are reserved for specific uses, such as the interrupt vector table (0:0) and the BIOS data area (40:0).
14.3   EFI GetMemoryMap() Boot Services Function
EFI enabled systems use the EFI defined GetMemoryMap() boot services function to convey memory resources to the OS loader. These resources must then be conveyed by the OS loader to OSPM.
The GetMemoryMap interface is only available at boot services time. It is not available as a run-time service after OSPM is loaded. The OS or its loader initiates the transition from boot services to run-time services by calling ExitBootServices(). After the call to ExitBootServices() all system memory map information must be derived from objects in the ACPI Namespace.
The GetMemoryMap() interface returns an array of EFI memory descriptors. These memory descriptors define a system memory map of all the installed RAM, and of physical memory ranges reserved by the firmware. Each descriptor contains a type field that dictates how the physical address range is to be treated by the operating system. The table below describes the memory types returned by the EFI GetMemoryMap() interface along with a mapping from EFI memory type to ACPI address range types. See the EFI specification for more information on EFI memory types.
Table 14-6   EFI Memory Types and mapping to ACPI address range types

Type

Mnemonic

Description

ACPI Address Range Type

EfiReservedMemoryType

Not used.

AddressRangeReserved

EfiLoaderCode

The Loader and/or OS may use this memory as they see fit.

Note: the OS loader that called ExitBootServices() is executing out of one or more EfiLoaderCode sections.

AddressRangeMemory

Table 14-7 EFI Memory Types and mapping to ACPI address range types (continued)

Type	Mnemonic	Description	ACPI Address Range Type
2	EfiLoaderData	The Loader and/or OS may use this memory as they see fit. Note: the OS loader that called ExitBootServices() is utilizing out of one or more EfiLoaderData sections.	AddressRangeMemory
3	EfiBootServicesCode	Memory available for general use.	AddressRangeMemory
4	EfiBootServicesData	Memory available for general use.	AddressRangeMemory
5	EfiRuntimeServiceCode	The OS and loader must preserve this memory range in the working and ACPI S1–S3 states.	AddressRangeReserved
6	EfiRuntimeServicesData	The OS and loader must preserve this memory range in the working and ACPI S1–S3 states.	AddressRangeReserved
7	EfiConventionalMemory	Memory available for general use.	AddressRangeMemory
8	EfiUnusableMemory	Memory that should not be used by the OS. For example, memory that failed EFI memory test.	AddressRangeReserved
9	EfiACPIReclainMemory	The memory is to be preserved by the loader and OS until ACPI in enabled. Once ACPI is enabled, the memory in this range is available for general use.	AddressRangeACPI
10	EfiACPIMemoryNVS	The OS and loader must preserve this memory range in the working and ACPI S1–S3 states.	AddressRangeNVS
11	EfiMemoryMappedIO	The OS does not use this memory. All system memory-mapped I/O port space information should come from ACPI tables.	AddressRangeReserved
12	EfiMemoryMappedIOPortSpace	The OS does not use this memory. All system memory-mapped I/O port space information should come from ACPI tables.	AddressRangeReserved
13	EfiPalCode	The OS and loader must preserve this memory range in the working and ACPI S1–S3 states.	AddressRangeReserved

14.4   EFI Assumptions and Limitations
·       The firmware returns address ranges describing the current system memory configuration.
·      The firmware does not return a range description for the memory mapping of PCI devices, ISA Option ROMs, and ISA Plug and Play cards because the OS has mechanisms available to detect them.
·      The firmware returns chip set-defined address holes that are not being used by devices as reserved.
·      Address ranges defined for baseboard memory-mapped I/O devices, such as APICs, are returned as reserved.
·      All occurrences of the system firmware are mapped as reserved, including the areas below 1 MB, at 16 MB (if present), and at end of the 4-GB address space. This can include PAL code on Itanium^TM- based systems.
·      Standard PC address ranges are not reported. For example, video memory at A0000 to BFFFF physical addresses are not described by this function. The range from E0000 to EFFFF is specific to the baseboard and is reported as it applies to that baseboard.
·      All of lower memory is reported as normal memory. The OS must handle standard RAM locations that are reserved for specific uses, such as the interrupt vector table (0:0) and the BIOS data area (40:0).
·      EFI contains descriptors for memory mapped I/O and memory mapped I/O port space to allow for virtual mode calls to EFI run-time functions OS must never use these regions.
14.5   Example Address Map
This sample address map (for an Intel processor-based system) describes a machine that has 128 MB of RAM, 640 KB of base memory and 127 MB of extended memory. The base memory has 639 KB available for the user and 1 KB for an extended BIOS data area. A 4-MB Linear Frame Buffer (LFB) is based at 12 MB. The memory hole created by the chip set is from 8 MB to 16 MB. Memory‑mapped APIC devices are in the system. The I/O Unit is at FEC00000 and the Local Unit is at FEE00000. The system BIOS is remapped to 1 GB–64 KB.
The 639-KB endpoint of the first memory range is also the base memory size reported in the BIOS data segment at 40:13. The following table shows the memory map of a typical system.
Table 14-8   Sample Memory Map

Base (Hex)	Length	Type	Description
0000 0000	639 KB	AddressRangeMemory	Available Base memory. Typically the same value as is returned using the INT 12 function.
0009 FC00	1 KB	AddressRangeReserved	Memory reserved for use by the BIOS(s). This area typically includes the Extended BIOS data area.
000F 0000	64 KB	AddressRangeReserved	System BIOS
0010 0000	7 MB	AddressRangeMemory	Extended memory, which is not limited to the 64‑MB address range.
0080 0000	4 MB	AddressRangeReserved	Chip set memory hole required to support the LFB mapping at 12 MB.
0100 0000	120 MB	AddressRangeMemory	Baseboard RAM relocated above a chip set memory hole.
FEC0 0000	4 KB	AddressRangeReserved	I/O APIC memory mapped I/O at FEC00000.
FEE0 0000	4 KB	AddressRangeReserved	Local APIC memory mapped I/O at FEE00000.
FFFF 0000	64 KB	AddressRangeReserved	Remapped System BIOS at end of address space.

14.6   Example: Operating System Usage
The following code segment illustrates the algorithm to be used when calling the Query System Address Map function. It is an implementation example and uses non‑standard mechanisms.

E820Present = FALSE;
    Reg.ebx = 0;
    do {
       Reg.eax = 0xE820;
       Reg.es = SEGMENT (&Descriptor);
       Reg.di = OFFSET (&Descriptor);
       Reg.ecx = sizeof (Descriptor);
       Reg.edx = 'SMAP';

       _int( 15, regs );

       if ((Regs.eflags & EFLAG_CARRY) || Regs.eax != 'SMAP') {
           break;
       }

       if (Regs.ecx < 20 || Reg.ecx >sizeof (Descriptor) ) {
           // bug in bios -all returned descriptors must be
           // at least 20 bytes long, and cannot be larger then
           // the input buffer.

           break;
       }

       E820Present = TRUE;
           .
           .
           .
       Add address range Descriptor.BaseAddress through
       Descriptor.BaseAddress + Descriptor.Length
       as type Descriptor.Type
           .
           .
           .

    } while (Regs.ebx != 0);

    if (!E820Present) {
       .
       .
       .
    call INT-15 88 and/or INT-15 E801 to obtain old style
    memory information
       .
       .
       .
    }

15 Waking and Sleeping
ACPI defines a mechanism to transition the system between the working state (G0) and a sleeping state (G1) or the soft-off (G2) state. During transitions between the working and sleeping states, the context of the user's operating environment is maintained. ACPI defines the quality of the G1 sleeping state by defining the system attributes of four types of ACPI sleeping states (S1, S2, S3, and S4). Each sleeping state is defined to allow implementations that can tradeoff cost, power, and wake latencies. Additionally, ACPI defines the sleeping states such that an ACPI platform can support multiple sleeping states, allowing the platform to transition into a particular sleeping state for a predefined period of time and then transition to a lower power/higher wake latency sleeping state (transitioning through the G0 state) [15].
ACPI defines a programming model that provides a mechanism for OSPM to initiate the entry into a sleeping or soft-off state (S1-S5); this consists of a 3-bit field SLP_TYPx[16] that indicates the type of sleep state to enter, and a single control bit SLP_EN to start the sleeping process.
Note: Systems containing processors without a hardware mechanism to place the processor in a low-power state may additionally require the execution of appropriate native instructions to place the processor in a low-power state after OSPM sets the SLP_EN bit hardware may implement a number of low-power sleeping states and then associate these states with the defined ACPI sleeping states (through the SLP_TYPx fields). The ACPI system firmware creates a sleeping object associated with each supported sleeping state (unsupported sleeping states are identified by the lack of the sleeping object). Each sleeping object contains two constant 3-bit values that OSPM will program into the SLP_TYPa and SLP_TYPb fields (in fixed register space).
ACPI also defines an alternate mechanism for entering and exiting the S4 state that passes control to the BIOS to save and restore platform context. Context ownership is similar in definition to the S3 state, but hardware saves and restores the context of memory to non-volatile storage (such as a disk drive), and OSPM treats this as an S4 state with implied latency and power constraints. This alternate mechanism of entering the S4 state is referred to as the S4BIOS transition.
Prior to entering a sleeping state (S1-S4), OSPM will execute OEM-specific AML/ASL code contained in the _PTS (Prepare To Sleep) control method. One use of the _PTS control method is that it can indicate to the embedded controller what sleeping state the system will enter when the SLP_EN bit is set. The embedded controller can then respond by executing the proper power-plane sequencing upon this bit being set.
Immediately prior to entering a system sleeping state, OSPM will execute the _GTS (Going To Sleep) control method. _GTS allows ACPI system firmware to perform any necessary system specific functions prior to entering a system sleeping state.
Upon waking, OSPM will execute the _BFS (Back From Sleep) control method. This allows ACPI system firmware to perform any necessary system specific functions prior to returning control to OSPM. The _WAK (Wake) control method is then executed. This control method again contains OEM-specific AML/ASL code. One use of the _WAK control method requests OSPM to check the platform for any devices that might have been added or removed from the system while the system was asleep. For example, a PC Card controller might have had a PC Card added or removed, and because the power to this device was off in the sleeping state, the status change event was not generated.
This section discusses the system initialization sequence of an ACPI-enabled platform. This includes the boot sequence, different wake scenarios, and an example to illustrate how to use the system address map reporting interfaces. This sequence is part of the ACPI event programming model.
For detailed information on the power management control methods described above, see section 7, "Power and Performance Management."
15.1   Sleeping States
The illustration below shows the transitions between the working state, the sleeping states, and the Soft Off state.

Figure 15-1   Example Sleeping States
ACPI defines distinct differences between the G0 and G1 system states.
·      In the G0 state, work is being performed by the OS/application software and the hardware. The CPU or any particular hardware device could be in any one of the defined power states (C0-C3 or D0-D3); however, some work will be taking place in the system.
·      In the G1 state, the system is assumed to be doing no work. Prior to entering the G1 state, OSPM will place devices in a device power state compatible with the system sleeping state to be entered; if a device is enabled to wake the system, then OSPM will place these devices into the lowest Dx state from which the device supports wake. This is defined in the power resource description of that device object. This definition of the G1 state implies:
· The CPUs execute no instructions in the G1 state.
· Hardware devices are not operating (except possibly to generate a wake event).
· ACPI registers are affected as follows:
· Wake event bits are enabled in the corresponding fixed or general-purpose registers according to enabled wake options.
· PM1 control register is programmed for the desired sleeping state.
· WAK_STS is set by hardware in the sleeping state.
All sleeping states have these specifications. ACPI defines additional attributes that allow an ACPI platform to have up to four different sleeping states, each of which has different attributes. The attributes were chosen to allow differentiation of sleeping states that vary in power, wake latency, and implementation cost tradeoffs.
Running processors at reduced levels of performance is not an ACPI sleeping state (G1); this is a working (G0) state–defined event.
The CPU cannot execute any instructions when in the sleeping state; OSPM relies on this fact. A platform designer might be tempted to support a sleeping system by reducing the clock frequency of the system, which allows the platform to maintain a low-power state while at the same time maintaining communication sessions that require constant interaction (as with some network environments). This is definitely a G0 activity where an OS policy decision has been made to turn off the user interface (screen) and run the processor in a reduced performance mode. This type of reduced performance state as a sleeping state is not defined by the ACPI specification; ACPI assumes no code execution during sleeping states.
ACPI defines attributes for four sleeping states: S1, S2, S3 and S4. (Notice that S4 and S5 are very similar from a hardware standpoint.) ACPI-compatible platforms can support multiple sleeping states. ACPI specifies that a 3-bit binary number be associated with each sleeping state (these numbers are given objects within ACPI's root namespace: \_S0, \_S1, \_S2, \_S3, \_S4 and \_S5). When entering a system sleeping state, OSPM will do the following:
1.    Pick the deepest sleeping state supported by the platform and enabled waking devices.
2.    Execute the _PTS control method (which passes the type of intended sleep state to OEM AML code).
3.    If OS policy decides to enter the S4 state and chooses to use the S4BIOS mechanism and S4BIOS is supported by the platform, OSPM will pass control to the BIOS software by writing the S4BIOS_REQ value to the SMI_CMD port.
4.    If not using the S4BIOS mechanism, OSPM gets the SLP_TYPx value from the associated sleeping object (\_S1, \_S2, \_S3, \_S4 or \_S5).
5.    Program the SLP_TYPx fields with the values contained in the selected sleeping object.
6.    Execute the _GTS control method, passing an argument that indicates the sleeping state to be entered (1, 2, 3, or 4 representing S1, S2, S3, and S4).
7.    If entering S1, S2, or S3, flush the processor caches.
8.    If not entering S4BIOS, set the SLP_EN bit to start the sleeping sequence. (This actually occurs on the same write operation that programs the SLP_TYPx field in the PM1_CNT register.) If entering S4BIOS, write the S4BIOS_REQ value into the SMI_CMD port.
9.    On systems containing processors without a hardware mechanism to place the processor in a low-power state, execute appropriate native instructions to place the processor in a low-power state.
The _PTS control method provides the BIOS a mechanism for performing some housekeeping, such as writing the sleep type value to the embedded controller, before entering the system sleeping state. Control method execution occurs "just prior" to entering the sleeping state and is not an event synchronized with the write to the PM1_CNT register. Execution can take place several seconds prior to the system actually entering the sleeping state. As such, no hardware power-plane sequencing takes place by execution of the _PTS control method.
Upon waking, the _BFS control method is executed. OSPM then executes the _WAK control method. This control method executes OEM-specific ASL/AML code that can search for any devices that have been added or removed during the sleeping state.
The following sections describe the sleeping state attributes.
15.1.1   S1 Sleeping State
The S1 state is defined as a low wake-latency sleeping state. In this state, all system context is preserved with the exception of CPU caches. Before setting the SLP_EN bit, OSPM will flush the system caches the platform supports the WBINVD instruction (as indicated by the WBINVD and WBINVD_FLUSH flags in the FADT), OSPM will execute the WBINVD instruction hardware is responsible for maintaining all other system context, which includes the context of the CPU, memory, and chipset.
Examples of S1 sleeping state implementation alternatives follow.
15.1.1.1   Example 1: S1 Sleeping State Implementation
This example references an IA processor that supports the stop grant state through the assertion of the STPCLK# signal. When SLP_TYPx is programmed to the S1 value (the OEM chooses a value, which is then placed in the \_S1 object) and the SLP_ENx bit is subsequently set, the hardware can implement an S1 state by asserting the STPCLK# signal to the processor, causing it to enter the stop grant state.
In this case, the system clocks (PCI and CPU) are still running. Any enabled wake event causes the hardware to de-assert the STPCLK# signal to the processor whereby OSPM must first invalidate the CPU caches and then transition back into the working state.
15.1.1.2   Example 2: S1 Sleeping State Implementation
When SLP_TYPx is programmed to the S1 value and the SLP_ENx bit is subsequently set, the hardware will implement an S1 sleeping state transition by doing the following:
1.    Placing the processor into the stop grant state.
2.    Stopping the processor's input clock, placing the processor into the stop clock state.
3.    Placing system memory into a self-refresh or suspend-refresh state. Refresh is maintained by the memory itself or through some other reference clock that is not stopped during the sleeping state.
4.    Stopping all system clocks (asserts the standby signal to the system PLL chip). Normally the RTC will continue running.
In this case, all clocks in the system have been stopped (except for the RTC). Hardware must reverse the process (restarting system clocks) upon any enabled wake event whereby OSPM must first invalidate the CPU caches and then transition back into the working state.
15.1.2   S2 Sleeping State
The S2 state is defined as a low wake latency sleep state. This state is similar to the S1 sleeping state where any context except for system memory may be lost. Additionally, control starts from the processor's reset vector after the wake event. Before setting the SLP_EN bit, OSPM will flush the system caches. If the platform supports the WBINVD instruction (as indicated by the WBINVD and WBINVD_FLUSH flags in the FADT), OSPM will execute the WBINVD instruction. The hardware is responsible for maintaining chip set and memory context. An example of an S2 sleeping state implementation follows.
15.1.2.1   Example:S2 Sleeping State Implementation
When the SLP_TYPx register(s) are programmed to the S2 value (found in the \_S2 object) and the SLP_EN bit is set, the hardware will implement an S2 sleeping state transition by doing the following:
1.    Stopping system clocks (the only running clock is the RTC).
2.    Placing system memory into a self-refresh or suspend-refresh state.
3.    Powering off the CPU and cache subsystem.
In this case, the CPU is reset upon detection of the wake event; however, core logic and memory maintain their context. Execution control starts from the CPU's boot vector. The BIOS is required to:
·       Program the initial boot configuration of the CPU (such as the CPU's MSR and MTRR registers).
·       Initialize the cache controller to its initial boot size and configuration.
·       Enable the memory controller to accept memory accesses.
·       Jump to the waking vector.
15.1.3   S3 Sleeping State
The S3 state is defined as a low wake-latency sleep state. From the software viewpoint, this state is functionally the same as the S2 state. The operational difference is that some Power Resources that may have been left ON in the S2 state may not be available to the S3 state. As such, some devices may be in a lower power state when the system is in S3 state than when the system is in the S2 state. Similarly, some device wake events can function in S2 but not S3. An example of an S3 sleeping state implementation follows.
15.1.3.1   Example:S3 Sleeping State Implementation
When the SLP_TYPx register(s) are programmed to the S3 value (found in the \_S3 object) and the SLP_EN bit is set, the hardware will implement an S3 sleeping state transition by doing the following:
1.    Placing the memory into a low-power auto-refresh or self-refresh state.
2.    Devices that are maintaining memory isolating themselves from other devices in the system.
3.    Removing power from the system. At this point, only devices supporting memory are powered (possibly partially powered). The only clock running in the system is the RTC clock.
In this case, the wake event repowers the system and resets most devices (depending on the implementation).
Execution control starts from the CPU's boot vector BIOS is required to:
1.    Program the initial boot configuration of the CPU (such as the MSR and MTRR registers).
2.    Initialize the cache controller to its initial boot size and configuration.
3.    Enable the memory controller to accept memory accesses.
4.    Jump to the waking vector.
Notice that if the configuration of cache memory controller is lost while the system is sleeping, the BIOS is required to reconfigure it to either the pre-sleeping state or the initial boot state configuration. The BIOS can store the configuration of the cache memory controller into the reserved memory space, where it can then retrieve the values after waking. OSPM will call the _PTS method once per session (prior to sleeping).
The BIOS is also responsible for restoring the memory controller's configuration. If this configuration data is destroyed during the S3 sleeping state, then the BIOS needs to store the pre-sleeping state or initial boot state configuration in a non-volatile memory area (as with RTC CMOS RAM) to enable it to restore the values during the waking process.
When OSPM re-enumerates buses coming out of the S3 sleeping state, it will discover any devices that have been inserted or removed, and configure devices as they are turned on.
15.1.4   S4 Sleeping State
The S4 sleeping state is the lowest-power, longest wake-latency sleeping state supported by ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform has powered off all devices. Because this is a sleeping state, the platform context is maintained. Depending on how the transition into the S4 sleeping state occurs, the responsibility for maintaining system context changes. S4 supports two entry mechanisms: OS initiated and BIOS-initiated. The OSPM-initiated mechanism is similar to the entry into the S1-S3 sleeping states; OSPM driver writes the SLP_TYPx fields and sets the SLP_EN bit. The BIOS-initiated mechanism occurs by OSPM transferring control to the BIOS by writing the S4BIOS_REQ value to the SMI_CMD port.
In OSPM-initiated S4 sleeping state, OSPM is responsible for saving all system context. Before entering the S4 state, OSPM will save context of all memory with the exception of memory reported as type AddressRangeReserved (see section 15, "System Address Map Interfaces," for more information). Upon waking, OSPM will then restore the system context. When OSPM re-enumerates buses coming out of the S4 sleeping state, it will discover any devices that have come and gone, and configure devices as they are turned on.
In the BIOS-initiated S4 sleeping state, OSPM is responsible for the same system context as described in the S3 sleeping state (BIOS restores the memory and some chip set context). The S4BIOS transition transfers control to the BIOS, allowing it to save context to non-volatile memory (such as a disk partition).
15.1.4.1   Operating System-Initiated S4 Transition
If OSPM supports OSPM-initiated S4 transition, it will not generate a BIOS-initiated S4 transition. Platforms that support the BIOS-initiated S4 transition also support OSPM-initiated S4 transition.
OSPM-initiated S4 transition is initiated by OSPM by saving system context, writing the appropriate values to the SLP_TYPx register(s), and setting the SLP_EN bit. Upon exiting the S4 sleeping state, the BIOS restores the chipset to its POST condition, updates the hardware signature (described later in this section), and passes control to OSPM through a normal boot process.
When the BIOS builds the ACPI tables, it generates a hardware signature for the system. If the hardware configuration has changed during an OS-initiated S4 transition, the BIOS updates the hardware signature in the FACS table. A change in hardware configuration is defined to be any change in the platform hardware that would cause the platform to fail when trying to restore the S4 context; this hardware is normally limited to boot devices. For example, changing the graphics adapter or hard disk controller while in the S4 state should cause the hardware signature to change. On the other hand, removing or adding a PC Card device from a PC Card slot should not cause the hardware signature to change.
15.1.4.2   The S4BIOS Transition
The BIOS-initiated S4 transition begins with OSPM writing the S4BIOS_REQ value into the SMI_CMD port (as specified in the FADT). Once gaining control, the BIOS then saves the appropriate memory and chip set context, and then places the platform into the S4 state (power off to all devices).
In the FACS memory table, there is the S4BIOS_F bit that indicates hardware support for the BIOS-initiated S4 transition. If the hardware platform supports the S4BIOS state, it sets the S4BIOS_F flag within the FACS memory structure prior to booting the OS. If the S4BIOS_F flag in the FACS table is set, this indicates that OSPM can request the BIOS to transition the platform into the S4BIOS sleeping state by writing the S4BIOS_REQ value (found in the FADT) to the SMI_CMD port (identified by the SMI_CMD value in the FADT).
Upon waking the BIOS, software restores memory context and jumps to the waking vector (similar to wake from an S3 state). Coming out of the S4BIOS state, the BIOS must only configure boot devices (so it can read the disk partition where it saved system context). When OSPM re-enumerates buses coming out of the S4BIOS state, it will discover any devices that have come and gone, and configure devices as they are turned on.
15.1.5   S5 Soft Off State
OSPM places the platform in the S5 soft off state to achieve a logical off. Notice that the S5 state is not a sleeping state (it is a G2 state) and no context is saved by OSPM or hardware but power may still be applied to parts of the platform in this state and as such, it is not safe to disassemble. Also notice that from a hardware perspective, the S4 and S5 states are nearly identical. When initiated, the hardware will sequence the system to a state similar to the off state. The hardware has no responsibility for maintaining any system context (memory or I/O); however, it does allow a transition to the S0 state due to a power button press or a Remote Start. Upon start-up, the BIOS performs a normal power-on reset, loads the boot sector, and executes (but not the waking vector, as all ACPI table context is lost when entering the S5 soft off state).
The _TTS control method allows the BIOS a mechanism for performing some housekeeping, such as storing the targeted sleep state in a "global" variable that is accessible by other control methods (such as _PS3 and _DSW).
15.1.6 Transitioning from the Working to the Sleeping State
On a transition of the system from the working to the sleeping state, the following occurs:
1.    OSPM decides (through a policy scheme) to place the system into the sleeping state.
2.    OSPM invokes the _TTS method to indicate the deepest possible system state the system will transition to (1, 2, 3, or 4 representing S1, S2, S3, and S4).
3.    OSPM examines all devices enabled to wake the system and determines the deepest possible sleeping state the system can enter to support the enabled wake functions. The _PRW named object under each device is examined, as well as the power resource object it points to.
4.    OSPM places all device drivers into their respective Dx state. If the device is enabled for wake, it enters the Dx state associated with the wake capability. If the device is not enabled to wake the system, it enters the D3 state.
5.    OSPM executes the _PTS control method, passing an argument that indicates the desired sleeping state (1, 2, 3, or 4 representing S1, S2, S3, and S4).
6.    OSPM saves any other processor's context (other than the local processor) to memory.
7.    OSPM writes the waking vector into the FACS table in memory.
8.    OSPM executes the _GTS control method, passing an argument that indicates the sleeping state to be entered (1, 2, 3, or 4 representing S1, S2, S3, and S4).
9.    OSPM clears the WAK_STS in the PM1a_STS and PM1b_STS registers.
10.  OSPM saves the local processor's context to memory.
11.  OSPM flushes caches (only if entering S1, S2 or S3).
12.  OSPM sets GPE enable registers to ensure that all appropriate wake signals are armed.
13.  If entering an S4 state using the S4BIOS mechanism, OSPM writes the S4BIOS_REQ value (from the FADT) to the SMI_CMD port. This passes control to the BIOS, which then transitions the platform into the S4BIOS state.
14.  If not entering an S4BIOS state, then OSPM writes SLP_TYPa (from the associated sleeping object) with the SLP_ENa bit set to the PM1a_CNT register.
15.  OSPM writes SLP_TYPb with the SLP_EN bit set to the PM1b_CNT register.
16.  On systems containing processors without a hardware mechanism to place the processor in a low-power state, OSPM executes appropriate native instructions to place the processor in a low-power state.
17.  OSPM loops on the WAK_STS bit (in both the PM1a_CNT and PM1b_CNT registers).
18.  The system enters the specified sleeping state.
Note: this is accomplished after step 14 or 15 above.
15.1.7   Transitioning from the Working to the Soft Off State
On a transition of the system from the working to the soft off state, the following occurs:
1.    OSPM executes the _PTS control method, passing the argument 5.
2.    OSPM prepares its components to shut down (flushing disk caches).
3.    OSPM executes the _GTS control method, passing the argument 5.
4.    OSPM writes SLP_TYPa (from the \_S5 object) with the SLP_ENa bit set to the PM1a_CNT register.
5.    OSPM writes SLP_TYPb (from the \_S5 object) with the SLP_ENb bit set to the PM1b_CNT register.
6.    The system enters the Soft Off state.
15.2   Flushing Caches
Before entering the S1, S2 or S3 sleeping states, OSPM is responsible for flushing the system caches. ACPI provides a number of mechanisms to flush system caches. These include:
·       Using a native instruction (for example, the IA32 WBINVD instruction) to flush and invalidate platform caches.
WBINVD_FLUSH flag set (1) in the FADT indicates the system provides this support level.
·       Using the IA32 instruction WBINVD to flush but not invalidate the platform caches.
WBINVD flag set (1) in the FADT indicates the system provides this support level.
The manual flush mechanism has two caveats:
·       Largest cache is 1 MB in size (FLUSH_SIZE is a maximum value of 2 MB).
·       No victim caches (for which the manual flush algorithm is unreliable).
Processors with built-in victim caches will not support the manual flush mechanism and are therefore required to support the WBINVD mechanism to use the S2 or S3 state.
The manual cache-flushing mechanism relies on the two FADT fields:
·       FLUSH_SIZE. > Indicates twice the size of the largest cache in bytes.
·       FLUSH_STRIDE. > Indicates the smallest line size of the caches in bytes.
The cache flush size value is typically twice the size of the largest cache size, and the cache flush stride value is typically the size of the smallest cache line size in the platform. OSPM will flush the system caches by reading a contiguous block of memory indicated by the cache flush size.
15.3   Initialization
This section covers the initialization sequences for an ACPI platform. After a reset or wake from an S2, S3, or S4 sleeping state (as defined by the ACPI sleeping state definitions), the CPU will start execution from its boot vector. At this point, the initialization software has many options, depending on what the hardware platform supports. This section describes at a high level what should be done for these different options. Figure 15-2 illustrates the flow of the boot-up software.

Figure 15-2   BIOS Initialization
The processor will start executing at its power-on reset vector when waking from an S2, S3, or S4 sleeping state, during a power-on sequence, or as a result of a hard or soft reset.
When executing from the power-on reset vector as a result of a power-on sequence, a hard or soft reset, or waking from an S4 sleep state, the platform firmware performs complete hardware initialization; placing the system in a boot configuration. The firmware then passes control to the operating system boot loader.
When executing from the power-on reset vector as a result of waking from an S2 or S3 sleep state, the platform firmware performs only the hardware initialization required to restore the system to either the state the platform was in prior to the initial operating system boot, or to the pre-sleep configuration state. In multiprocessor systems, non-boot processors should be placed in the same state as prior to the initial operating system boot. The platform firmware then passes control back to OSPM system by jumping to either the Firmware_Waking_Vector or the X_Firmware_Waking_Vector in the FACS (see table 5-12 for more information). The contents of operating system memory contents may not be changed during the S2 or S3 sleep state.
First, the BIOS determines whether this is a wake from S2 or S3 by examining the SLP_TYP register value, which is preserved between sleeping sessions. If this is an S2 or S3 wake, then the BIOS restores minimum context of the system before jumping to the waking vector. This includes:
·       CPU configuration. BIOS restores the pre-sleep configuration or initial boot configuration of each CPU (MSR, MTRR, BIOS update, SMBase, and so on). Interrupts must be disabled (for IA-32 processors, disabled by CLI instruction).
·       Memory controller configuration. If the configuration is lost during the sleeping state, the BIOS initializes the memory controller to its pre-sleep configuration or initial boot configuration.
·       Cache memory configuration. If the configuration is lost during the sleeping state, the BIOS initializes the cache controller to its pre-sleep configuration or initial boot configuration.
·       Functional device configuration. The BIOS doesn't need to configure/restore context of functional devices such as a network interface (even if it is physically included in chipset) or interrupt controller. OSPM is responsible for restoring all context of these devices only requirement for the hardware and BIOS is to ensure that interrupts are not asserted by devices when the control is passed to OS.
·       ACPI registers. SCI_EN bit must be set event status/enable bits (PM1x_STS, PM1x_EN, GPEx_STS and GPEx_EN) must not be changed by BIOS.
Note: The BIOS may reconfigure the CPU, memory controller and cache memory controller to either the pre-sleeping configuration or the initial boot configuration. OSPM must accommodate both configurations.
When waking from an S4BIOS sleeping state, the BIOS initializes a minimum number of devices such as CPU, memory, cache, chipset and boot devices. After initializing these devices, the BIOS restores memory context from non-volatile memory such as hard disk, and jumps to waking vector.
As mentioned previously, waking from an S4 state is treated the same as a cold boot: the BIOS runs POST and then initializes memory to contain the ACPI system description tables. After it has finished this, it can call OSPM loader, and control is passed to OSPM.
When waking from S4 (either S4OS or S4BIOS), the BIOS may optionally set SCI_EN bit before passing control to OSPM. In this case, interrupts must be disabled (for IA-32 processors, disabled CLI instruction) until the control is passed to OSPM and the chipset must be configured in ACPI mode.
15.3.1   Placing the System in ACPI Mode
When a platform initializes from a cold boot (mechanical off or from an S4 or S5 state), the hardware platform may be configured in a legacy configuration. From these states, the BIOS software initializes the computer as it would for a legacy operating system. When control is passed to the operating system, OSPM will check the SCI_EN bit and if it is not set will then enable ACPI mode by first finding the ACPI tables, and then by generating a write of the ACPI_ENABLE value to the SMI_CMD port (as described in the FADT). The hardware platform will set the SCI_EN bit to indicate to OSPM that the hardware platform is now configured for ACPI.
Note: Before SCI is enabled, no SCI interrupt can occur. Nor can any SCI interrupt occur immediately after ACPI is on. The SCI interrupt can only be signaled after OSPM has enabled one of the GPE/PM1 enable bits.
When the platform is waking from an S1, S2 or S3 state, OSPM assumes the hardware is already in the ACPI mode and will not issue an ACPI_ENABLE command to the SMI_CMD port.

15.3.2   BIOS Initialization of Memory
During a power-on reset, an exit from an S4 sleeping state, or an exit from an S5 soft-off state, the BIOS needs to initialize memory. This section explains how the BIOS should configure memory for use by a number of features including:
·       ACPI tables.
·       BIOS memory that wants to be saved across S4 sleeping sessions and should be cached.
·       BIOS memory that does not require saving and should be cached.
For example, the configuration of the platform's cache controller requires an area of memory to store the configuration data. During the wake sequence, the BIOS will re-enable the memory controller and can then use its configuration data to reconfigure the cache controllers. To support these three items, IA-PC-based systems contain system address map reporting interfaces that return the following memory range types:
·       ACPI Reclaim Memory. Memory identified by the BIOS that contains the ACPI tables. This memory can be any place above 8 MB and contains the ACPI tables. When OSPM is finished using the ACPI tables, it is free to reclaim this memory for system software use (application space).
·       ACPI Non-Volatile-Sleeping Memory (NVS). Memory identified by the BIOS as being reserved by the BIOS for its use. OSPM is required to tag this memory as cacheable, and to save and restore its image before entering an S4 state. Except as directed by control methods, OSPM is not allowed to use this physical memory. OSPM will call the _PTS control method some time before entering a sleeping state, to allow the platform's AML code to update this memory image before entering the sleeping state. After the system awakes from an S4 state, OSPM will restore this memory area and call the _WAK control method to enable the BIOS to reclaim its memory image.
Note: The memory information returned from the system address map reporting interfaces should be the same before and after an S4 sleep.
When the system is first booting, OSPM will invoke E820 interfaces on IA-PC-based legacy systems or the GetMemoryMap() interface on EFI-enabled systems to obtain a system memory map (see section 15, "System Address Map Interfaces," for more information). As an example, the following memory map represents a typical IA-PC-based legacy platform's physical memory map.

Figure 15-3   Example Physical Memory Map

The names and attributes of the different memory regions are listed below:
·       0–640 KB. Compatibility Memory. Application executable memory for an 8086 system.
·       640 KB–1 MB. Compatibility Holes. Holes within memory space that allow accesses to be directed to the PC-compatible frame buffer (A0000h-BFFFFh), to adapter ROM space (C0000h-DFFFFh), and to system BIOS space (E0000h-FFFFFh).
·       1 MB–8 MB. Contiguous RAM. An area of contiguous physical memory addresses. Operating systems may require this memory to be contiguous in order for its loader to load the OS properly on boot up. (No memory-mapped I/O devices should be mapped into this area.)
·       8 MB–Top of Memory1. This area contains memory to the "top of memory1" boundary. In this area, memory-mapped I/O blocks are possible.
·       Boot Base–4 GB. This area contains the bootstrap ROM.
The BIOS should decide where the different memory structures belong, and then configure the E820 handler to return the appropriate values.
For this example, the BIOS will report the system memory map by E820 as shown in Figure 15-4. Notice that the memory range from 1 MB to top of memory is marked as system memory, and then a small range is additionally marked as ACPI reclaim memory. A legacy OS that does not support the E820 extensions will ignore the extended memory range calls and correctly mark that memory as system memory.

Figure 15-4 Memory as Configured after Boot
Also, from the Top of Memory1 to the Top of Memory2, the BIOS has set aside some memory for its own use and has marked as reserved both ACPI NVS Memory and Reserved Memory. A legacy OS will throw out the ACPI NVS Memory and correctly mark this as reserved memory (thus preventing this memory range from being allocated to any add-in device).

OSPM will call the _PTS control method prior to initiating a sleep (by programming the sleep type, followed by setting the SLP_EN bit). During a catastrophic failure (where the integrity of the AML code interpreter or driver structure is questionable), if OSPM decides to shut the system off, it will not issue a _PTS, but will immediately issue a SLP_TYP of "soft off" and then set the SLP_EN bit. Hence, the hardware should not rely solely on the _PTS control method to sequence the system to the "soft off" state. After waking from an S4 state, OSPM will restore the ACPI NVS memory image and then issue the _WAK control method that informs BIOS that its memory image is back.
15.3.3 OS Loading
At this point, the BIOS has passed control to OSPM, either by using OSPM boot loader (a result of waking from an S4/S5 or boot condition) or OSPM waking vector (a result of waking from an S2 or S3 state). For the Boot OS Loader path, OSPM will get the system address map via one of the mechanisms describe in section 15, "System Address Map Interfaces." If OSPM is booting from an S4 state, it will then check the NVS image file's hardware signature with the hardware signature within the FACS table (built by BIOS) to determine whether it has changed since entering the sleeping state (indicating that the platforms fundamental hardware configuration has changed during the current sleeping state). If the signature has changed, OSPM will not restore the system context and can boot from scratch (from the S4 state). Next, for an S4 wake, OSPM will check the NVS file to see whether it is valid. If valid, then OSPM will load the NVS image into system memory. Next, OSPM will check the SCI_EN bit and if it is not set, will write the ACPI_ENABLE value to the SMI_CMD register to switch into the system into ACPI mode and will then reload the memory image from the NVS file.

Figure 15-5   OS Initialization
If an NVS image file did not exist, then OSPM loader will load OSPM from scratch. At this point, OSPM will generate a _WAK call that indicates to the BIOS that its ACPI NVS memory image has been successfully and completely updated.
15.3.4   Exiting ACPI Mode
For machines that do not boot in ACPI mode, ACPI provides a mechanism that enables the OS to disable ACPI. The following occurs:
1.    OSPM unloads all ACPI drivers (including the ACPI driver).
2.    OSPM disables all ACPI events.
3.    OSPM finishes using all ACPI registers.
4.    OSPM issues an I/O access to the port at the address contained in the SMI_CMD field (in the FADT) with the value contained in the ACPI_DISABLE field (in the FADT).
5.    BIOS then remaps all SCI events to legacy events and resets the SCI_EN bit.
6.    Upon seeing the SCI_EN bit cleared, the ACPI OS enters the legacy OS mode.
When and if the legacy OS returns control to the ACPI OS, if the legacy OS has not maintained the ACPI tables (in reserved memory and ACPI NVS memory), the ACPI OS will reboot the system to allow the BIOS to re-initialize the tables.

16 Non-Uniform Memory Access (NUMA) Architecture Platforms
Systems employing a Non Uniform Memory Access (NUMA) architecture contain collections of hardware resources including processors, memory, and I/O buses, that comprise what is commonly known as a "NUMA node". Two or more NUMA nodes are linked to each other via a high-speed interconnect. Processor accesses to memory or I/O resources within the local NUMA node are generally faster than processor accesses to memory or I/O resources outside of the local NUMA node, accessed via the node interconnect. ACPI defines interfaces that allow the platform to convey NUMA node topology information to OSPM both statically at boot time and dynamically at run time as resources are added or removed from the system.
16.1 NUMA Node
A conceptual model for a node in a NUMA configuration may contain one or more of the following components:
· Processor
· Memory
· I/O Resources
· Networking, Storage
· Chipset
The components defined as part of the model are intended to represent all possible components of a NUMA node. A specific node in an implementation of a NUMA platform may not provide all of these components. At a minimum, each node must have a chipset with an interface to the interconnect between nodes.
The defining characteristic of a NUMA system is a coherent global memory and / or I/O address space that can be accessed by all of the processors. Hence, at least one node must have memory, at least one node must have I/O resources and at least one node must have processors. Other than the chipset, which must have components present on every node, each is implementation dependent. In the ACPI name space, NUMA nodes are described as module devices. See Section 9.12,"Module Device".
16.2 System Locality
A collection of components that are presented to OSPM as a Symmetrical Multi-Processing (SMP) unit belong to the same System Locality, also known as a Proximity Domain. The granularity of a System Locality is typically at the NUMA Node level although the granularity can also be at the sub-NUMA node level or the processor, memory and host bridge level. A System Locality is reported to the OSPM using the _PXM method. If OSPM only needs to know a near/far distinction among the System Localities, the _PXM method is sufficient.
OSPM makes no assumptions about the proximity or nearness of different proximity domains. The difference between two integers representing separate proximity domains does not imply distance between the proximity domains (in other words, proximity domain 1 is not assumed to be closer to proximity domain 0 than proximity domain 6).
16.2.1 System Resource Affinity Table Definition
This optional System Resource Affinity Table (SRAT) provides the boot time description of the processor and memory ranges belonging to a system locality. OSPM will consume the SRAT only at boot time. OSPM should use _PXM for any devices that are hot-added into the system after boot up.
The SRAT describes the system locality that all processors and memory present in a system belong to at system boot. This includes memory that can be hot-added (that is memory that can be added to the system while it is running, without requiring a reboot). OSPM can use this information to optimize the performance of NUMA architecture systems. For example, OSPM could utilize this information to optimize allocation of memory resources and the scheduling of software threads.
16.3 System Locality Distance Information
Optionally, OSPM may further optimize a NUMA architecture system using information about the relative memory latency distances among the System Localities. This may be useful if the distance between multiple system localities is significantly different. In this case, a simple near/far distinction may be insufficient. This information is contained in the optional System Locality Information Table (SLIT) and is returned from the evaluation of the _SLI object.
The SLIT is a matrix that describes the relative distances between all System Localities. Support for the _PXM object is required for SLIT System Locality as returned by the _PXM object is used as the row and column indices of the matrix.
Implementation Note: The size of the SLIT table is determined by the largest _PXM value used in the system. Hence, to minimize the size of the SLIT table, the _PXM values assigned by the system firmware should be in the range 0, �, N-1, where N is the number of System Localities. If _PXM values are not packed into this range, the SLIT will still work, but more memory will have to be allocated to store the "Entries" portion of the SLIT for the matrix.
The static SLIT table provides the boot time description of the relative distances among all System Localities. For hot-added devices and dynamic reconfiguration of the system localities, the _SLI object must be used for runtime update.
The _SLI method is an optional object that provides the runtime update of the relative distances from the System Locality i to all other System Localities in the system. Since _SLI method is providing additional relative distance information among System Localities, if implemented, it is provided alongside with the _PXM method.
16.3.1.1 Online Hot Plug
In the case of online addition, the Bus Check notification (0x0) is performed on a device object to indicate to OSPM that it needs to perform the Plug and Play re-enumeration operation on the device tree starting from the point where it has been notified. OSPM needs to evaluate all _PXM objects associated with the added System Localities, or _SLI objects if the SLIT is present.
In the case of online deletion, OSPM needs to perform the Plug and Play ejection operation when it receives the Eject Request notification (0x03). OSPM needs to remove the relative distance information from its internal data structure for the removed System Localities.
16.3.1.2 Impact to Existing Localities
Dynamic reconfiguration of the system may cause the relative distance information (if the optional SLIT is present) to become stale. If this occurs, the System Locality Information Update notification may be generated by the platform to a device at a point on the device tree that represents a System Locality. This indicates to OSPM that it needs to invoke the _SLI objects associated with the System Localities on the device tree starting from the point where it has been notified.

17   ACPI Source Language (ASL) Reference
This section formally defines the ACPI Source Language (ASL). ASL is a source language for defining ACPI objects including writing ACPI control methods. OEMs and BIOS developers define objects and write control methods in ASL and then use a translator tool (compiler) to generate ACPI Machine Language (AML) versions of the control methods. For a formal definition of AML, see the ACPI Machine Language (AML) Specification, section 18, "ACPI Machine Language Specification."
AML and ASL are different languages though they are closely related.

Every ACPI-compatible OS must support AML. A given user can define some arbitrary source language (to replace ASL) and write a tool to translate it to AML.
An OEM or BIOS vendor needs to write ASL and be able to single-step AML for debugging. (Debuggers and similar tools are expected to be AML-level tools, not source-level tools.) An ASL translator implementer must understand how to read ASL and generate AML. An AML interpreter author must understand how to execute AML.
This section has two parts:
·       The ASL grammar, which is the formal ASL specification and also serves as a quick reference.
·       A full ASL reference, which includes for each ASL operator: the operator invocation syntax, the type of each argument, and a description of the action and use of the operator.
17.1   ASL Language Grammar
The purpose of this section is to state unambiguously the grammar rules used by the syntax checker of an ASL compiler.
ASL statements declare objects. Each object has three parts, two of which might not be present.

Object := ObjectType FixedList VariableList
FixedList refers to a list, of known length, that supplies data that all instances of a given ObjectType must have. A fixed list is written as ( a , b , c , � ) where the number of arguments depends on the specific ObjectType, and some elements can be nested objects, that is (a, b, (q, r, s, t), d). Arguments to a FixedList can have default values, in which case they can be skipped. Thus, (a,,c) will cause the default value for the second argument to be used. Some ObjectTypes can have a null FixedList, which is simply omitted. Trailing arguments of some object types can be left out of a fixed list, in which case the default value is used.
VariableList refers to a list, not of predetermined length, of child objects that help define the parent. It is written as { x, y, z, aa, bb, cc } where any argument can be a nested object. ObjectType > determines what terms are legal elements of the VariableList. Some ObjectTypes >may have a null variable list, which is simply omitted.
Other rules for writing ASL statements are the following:
·       Multiple blanks are the same as one. Blank, (, ), ',' and newline are all token separators.
·       // marks the beginning of a comment, which continues from the // to the end of the line.
·       /* marks the beginning of a comment, which continues from the /* to the next */.
·       "" > surround an ASCII string.
·       Numeric constants can be written in three ways: ordinary decimal, octal (using 0ddd) or hexadecimal, using the notation 0xdd.

· Nothing indicates an empty item. For example, { Nothing } is equivalent to {}.

17.1.1 ASL Grammar Notation
The notation used to express the ASL grammar is specified in the following table.
Table 17‑ 1 ASL Grammar Notation

Notation Convention	Description	Example
Term := Term Term �	The term to the left of := can be expanded into the sequence of terms on the right.	aterm := bterm cterm means that aterm can be expanded into the two-term sequence of bterm followed by cterm.
Angle brackets (< > )	Used to group items.	<a b> \| <c d> means either a b or c d.
Arrow (=>)	Indicates required run-time reduction of an ASL argument to an AML data type. Means "reduces to" or "evaluates to" at run-time.	"TermArg => Integer" means that the argument must be an ASL TermArg that must resolve to an Integer > data type when it is evaluated by an AML interpreter.
Bar symbol ( \| )	Separates alternatives.	aterm := bterm \| <cterm dterm> means the following constructs are possible: bterm cterm dterm aterm := <bterm \| cterm> dterm means the following constructs are possible: bterm dterm cterm dterm
Term Term Term	Terms separated from each other by spaces form an ordered list.	N/A
Word in bold	Denotes the name of a term in the ASL grammar, representing any instance of such a term. ASL terms are not case-sensitive.	In the following ASL term definition: ThermalZone (ZoneName) {ObjectList} the item in bold is the name of the term.
Word in italics	Names of arguments to objects that are replaced for a given instance.	In the following ASL term definition: ThermalZone (ZoneName) {ObjectList} the italicized item is an argument. The item that is not bolded or italicized is defined elsewhere in the ASL grammar.
Single quotes (' ')	Indicate constant characters.	'A'
0xdd	Refers to a byte value expressed as two hexadecimal digits.	0x21 means a value of hexadecimal 21, or decimal 37. Notice that a value expressed in hexadecimal must start with a leading zero (0).
Dash character ( - )	Indicates a range.	1-9 means a single digit in the range 1 to 9 inclusive.

17.1.2 ASL Name and Pathname Terms

LeadNameChar :=
'A'-'Z' | 'a'-'z' | '_'

DigitChar :=
'0'-'9'
NameChar :=
DigitChar | LeadNameChar