Advanced Configuration and Power Interface Specification
There now exists version 4.0 and 4.0a. Version 5.0 is un:wder Development! as of 9/23/10.
Revision |
Change Description |
Affected Sections |
3.0b Oct. 2006 |
Table 5-6 changes. Added BERT, DMAR, ERST, HEST, IBFT, UEFI, & WAET Table signatures, corrected BOOTand TCPA table urls. Added PCIe ASPM Controls to Boot Architecture Flags Table 5-11 Clarified DSDT loading. Clarified SSDTs are ALL loaded during init. Added a section describing guidelines for the ordering of processors in the MADT to support proper boot processor and multi-threaded logical processor operation. Clarified _STA object description. Clarified _INI object description. Clarified _CST entry type field is 1,2, or 3 only. Clarified _PTC ASL
definition, Corrected _PTC ASL examples Clarified _PCT ASL definition. Added section describing PCI Bus and Segment Group Numbers under Module Devices Corrected LoadTable invocation in thermal zone with multiple devices example. Corrected RegisterTerm definition to include optional DescriptorName field. Corrected Buffer declaration example. Corrected DMA Resource Descriptor Macro Descriptor Name description. Corrected DWORD IO Resource Descriptor Macro Descriptor Name description. Corrected DWORD Memory Resource Descriptor Macro Descriptor Name description. Corrected DWORD Space Resource Descriptor Macro Descriptor Name description. Corrected Extended IO Resource Descriptor Macro Descriptor Name description. Corrected Extended Memory Resource Descriptor Macro Descriptor Name description. Corrected Extended Space Resource Descriptor Macro Descriptor Name description. Clarified External object ReturnType and ParamterTypes. Clarified Function object ParamterTypes. Clarified IndexField object operation. Corrected IO Resource Descriptor Macro Descriptor Name description. Corrected Interrupt Resource Descriptor Macro Descriptor Name description. Corrected IRQNoFlags Interrupt Resource Descriptor Macro Descriptor Name description. Clarified LoadTable is not used to load tables with "SSDT" signature. Clarified Match Object SearchPackage argument and description. Corrected Memory24 Memory Resource Descriptor Macro Descriptor Name description. Corrected AddressAlignment field bits. Corrected Memory32 Memory Resource Descriptor Macro Descriptor Name description. Corrected Memory32Fixed Memory Resource Descriptor Macro Descriptor Name description. Clarified Method object ParamterTypes. Corrected QwordIO Resource Descriptor Macro Descriptor Name description. Corrected Qword Memory Resource Descriptor Macro Descriptor Name description. Corrected QwordSpace Resource Descriptor Macro Descriptor Name description. Added Descriptor Name argument description to Register Resource Descriptor Macro definition. Corrected VendorLong Resource Descriptor Macro Descriptor Name description. Corrected VendorShort Resource Descriptor Macro Descriptor Name description. Clarified Wait object TimeoutValue range. Corrected WordBusNumber Resource Descriptor Macro Descriptor Name description. Corrected WordIO Resource Descriptor Macro Descriptor Name description. Corrected WordSpace Resource Descriptor Macro Descriptor Name description. |
5.2.6 5.2.9.3 5.,2.11.1 5.2.11.2 5.2.11.4.1 6.3.7 6.5.1 8.4.2.1 8.4.3.1, 8.4.3.4 8.4.4.1 9.12.1 11.6.3 17.1.8 17.5.9 17.5.30 17.5.31 17.5.32 17.5.33 17.5.39 17.5.40 17.5.41 17.5.42 17.5.49 17.5.54 17.5.56 17.5.57 17.5.58 17.5.68 17.5.71 17.5.72 17.5.73 17.5.74 17.5.75 17.5.94 17.5.95 17.5.96 17.5.98 17.5.127 17.5.128 17.5.129 17.5.131 17.5.132 17.5.133 |
3.0a |
Errata corrected and clarifications added. Table 5-6 changes.Updated HPET web link, added WSPT and WDAT, updated WDRT description and web link Clarified that the endian-ness of data value encodings in externally defined data tables is specified by the external data table specifications Added MSI_Not_Supported bit to IA-PC Boot Architecture Flags Table 5-11 Corrected X_Firmware_Waking_Vector description in Table 5-12 _ADR object encoding for USB Ports clarified as 1-n in Table 6-2 Updated and clarified _HPX object description and setting record types Clarified Resource Data Type descriptions – readability / usability Clarified Small Resource Data Type description - Tables 6-21, 6-22 Corrected IRQ Descriptior ASL macro reference Corrected description text of General Flags field for _MAF and _MIF bits in Address Space Descriptors Updated _PDC ASL example invoking _OSC and accompanying description Corrected processor Throttling State (T-state) control interface definitions Clarified OSPM processing of _TPC notifies on platforms supporting P-states Clarified _PSS entry power field is maximum power consumed in the P-state Clarified _CRS encoding of registers for the GPE Block device Corrected OpCode definitions for DerefOfTerm and IndexTerm Added ProcessorObj to ObjectTypeKeyword Clarified Data Type Conversion Rules in Table 17-8 Clarified creation of zero bit-length field using CreateField causes fatal exception Clarified DMA Resource Descriptor Macro DmaChannelList description Function object ParameterTypes >description corrected. Fixed StringObj type in example Clarified Interrupt Resource Descriptor Macros InterruptList description Corrected Interrupt Resource Descriptor Macro description Corrected Package declaration Clarified Return object ASL syntax providing implicit zero return argument when no parenthesis follow the Return statement ToBuffer - Clarified string null terminator is copied Clarified ASL Resource Macros - ResourceSourceIndex
> and ResourceSource argument requirements and ASL compiler behavior Corrected AML definition - data types Const -> Data Removed the 200 byte length
limitation on ASCII strings Clarified that definition blocks loaded by the Load operator must be in memory marked as AddressRangeReserved or AddressRangeNVS |
5.2.6 5.2.6 5.2.9.3 5.2.10 6.1.1 6.2.7 6.4 6.4.2 6.4.2.1 6.4.3.5.1-4 8.4.1 8.4.3 8.4.3.3 8.4.4.2 9.11 17.1.5 17.1.7 17.2.5.7 17.5.19 17.5.30 17.5.49 17.5.55,57,58 17.5.57 17.5.91 17.5.102 17.5.119 17.5.31,32,33,55,94,95,96,131,132,133 18.2.1 17.2.2.2, 17.2.5, 17.2.5.7, 17.5.123 17.5.67 |
3.0
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Major specification revision. General configuration enhancements. Inter-Processor power, performance, and throttling state dependency support added. Support for > 256 processors added. NUMA Distancing support added. PCI Express support added. SATA support added. Ambient Light Sensor and User Presence device support added. Thermal model extended beyond processor-centric support. |
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2.0c |
Errata corrected and clarifications added.
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2.0b |
Errata corrected and clarifications added.
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2.0a |
Errata corrected and clarifications added. ACPI 2.0 Errata Document Revision 1.0 through 1.5 integrated. |
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ACPI 2.0 Errata Doc. Rev |
Errata corrected and clarifications added.
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ACPI 2.0 Errata Doc. Rev |
Errata corrected and clarifications added.
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ACPI 2.0 Errata Doc. Rev |
Errata corrected and clarifications added.
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ACPI 2.0 Errata Doc. Rev |
Errata corrected and clarifications added.
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ACPI 2.0 Errata Doc. Rev |
Errata corrected and clarifications added.
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ACPI 2.0 Errata Doc. Rev |
Errata corrected and clarifications added.
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2.0 |
Major specification revision. 64-bit addressing support added. Processor and device performance state support added. Numerous multiprocessor workstation and server-related enhancements. Consistency and readability enhancements throughout. |
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1.0b |
Errata corrected and clarifications added. New interfaces added. |
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1.0a |
Errata corrected and clarifications added. New interfaces added. |
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1.0 |
Original Release. |
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Hardware\OS |
Legacy OS |
ACPI OS with OSPM |
Legacy hardware |
A legacy OS on legacy hardware does what it always did. |
If the OS lacks legacy support, legacy support is completely contained within the hardware functions. |
Legacy and ACPI hardware support in machine |
It works just like a legacy OS on legacy hardware. |
During boot, the OS tells the hardware to switch from legacy to OSPM/ACPI mode and from then on, the system has full OSPM/ACPI support. |
ACPI-only hardware |
There is no power management. |
There is full OSPM/ACPI support. |
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Global system state |
Software runs |
Latency |
Power consumption |
OS restart required |
Safe to disassemble computer |
Exit state electronically |
G0 Working |
Yes |
0 |
Large |
No |
No |
Yes |
G1 Sleeping |
No |
>0, varies with sleep state |
Smaller |
No |
No |
Yes |
G2/S5 Soft Off |
No |
Long |
Very near 0 |
Yes |
No |
Yes |
G3 Mechanical Off |
No |
Long |
RTC battery |
Yes |
Yes |
No |
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Device State |
Power Consumption |
Device Context Retained |
Driver Restoration |
D0 - Fully-On |
As needed for operation |
All |
None |
D1 |
D0>D1>D2>D3 |
>D2 |
<D2 |
D2 |
D0>D1>D2>D3 |
<D1 |
>D1 |
D3 - Off |
0 |
None |
Full initialization and load
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Level |
Description |
Warning |
When the total available energy (mWh) or capacity (mAh) in the batteries falls below this level, the OS will notify the user through the UI. This value should allow for a few minutes of run-time before the "Low" level is encountered so the user has time to wrap up any important work, change the battery, or find a power outlet to plug the system in. |
Low |
This value is an estimation of the amount of energy or battery capacity required by the system to transition to any supported sleeping state. When the OS detects that the total available battery capacity is less than this value, it will transition the system to a user defined system state (S1-S5). In most situations this should be S4 so that system state is not lost if the battery eventually becomes completely empty. The design of the OS should consider that users of a multiple battery system may remove one or more of the batteries in an attempt replace or charge it. This might result in the remaining capacity falling below the "Low" level not leaving sufficient battery capacity for the OS to safely transition the system into the sleeping state. Therefore, if the batteries are discharging simultaneously, the action might need to be initiated at the point when both batteries reach this level. |
Critical |
The Critical battery state indicates that all available batteries are discharged and do not appear to be able to supply power to run the system any longer. When this occurs, the OS must attempt to perform an emergency shutdown as described below. For a smart battery system, this would typically occur when all batteries reach a capacity of 0, but an OEM may choose to put a larger value in the Smart Battery Table to provide an extra margin of safely. For a Control Method Battery system with multiple batteries, the flag is reported per battery. If any battery in the system is in a critically low state and is still providing power to the system (in other words, the battery is discharging), the system is considered to be in a critical energy state. The _BST control method is required to return the Critical flag on a discharging battery only when all batteries have reached a critical state; the ACPI BIOS is otherwise required to switch to a non-critical battery. |
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Feature Name |
Description |
Programming Model |
Power Management Timer |
24-bit or 32-bit free running timer. |
Fixed Hardware Feature Control Logic |
Power Button |
User pushes button to switch the system between the working and sleeping states. |
Fixed Hardware Event and Control Logic or Generic Hardware Event and Logic |
Sleep Button |
User pushes button to switch the system between the working and sleeping state. |
Fixed Hardware Event and Control Logic or Generic Hardware Event and Logic |
Power Button Override |
User sequence (press the power button for 4 seconds) to turn off a hung system. |
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Real Time Clock Alarm |
Programmed time to wake the system. |
Optional Fixed Hardware Event[2] |
Sleep/Wake Control Logic |
Logic used to transition the system between the sleeping and working states. |
Fixed Hardware Control and Event Logic |
Embedded Controller Interface |
ACPI Embedded Controller protocol and interface, as described in section 12, "ACPI Embedded Controller Interface Specification." |
Generic Hardware Event Logic, must reside in the general-purpose register block |
Legacy/ACPI Select |
Status bit that indicates the system is using the legacy or ACPI power management model (SCI_EN). |
Fixed Hardware Control Logic |
Lid switch |
Button used to indicate whether the system's lid is open or closed (mobile systems only). |
Generic Hardware Event Feature |
C1 Power State |
Processor instruction to place the processor into a low-power state. |
Processor ISA |
C2 Power Control |
Logic to place the processor into a C2 power state. |
Fixed Hardware Control Logic |
C3 Power Control |
Logic to place the processor into a C3 power state. |
Fixed Hardware Control Logic |
Thermal Control |
Logic to generate thermal events at specified trip points. |
Generic Hardware Event and Control Logic (See description of thermal logic in section 3.10, "Thermal Management.") |
Device Power Management |
Control logic for switching between different device power states. |
Generic Hardware control logic |
AC Adapter |
Logic to detect the insertion and removal of the AC adapter. |
Generic Hardware event logic |
Docking/device insertion and removal |
Logic to detect device insertion and removal events. |
Generic Hardware event logic |
Register |
Size (Bytes) |
Address (relative to register block) |
PM1a_STS |
PM1_EVT_LEN/2 |
<PM1a_EVT_BLK > |
PM1a_EN |
PM1_EVT_LEN/2 |
<PM1a_EVT_BLK >+PM1_EVT_LEN/2 |
PM1b_STS |
PM1_EVT_LEN/2 |
<PM1b_EVT_BLK > |
PM1b_EN |
PM1_EVT_LEN/2 |
<PM1b_EVT_BLK >+PM1_EVT_LEN/2 |
Register |
Size (Bytes) |
Address (relative to register block) |
PM1_CNTa |
PM1_CNT_LEN |
<PM1a_CNT_BLK > |
PM1_CNTb |
PM1_CNT_LEN |
<PM1b_CNT_BLK > |
Register |
Size (Bytes) |
Address (relative to register block) |
PM2_CNT |
PM2_CNT_LEN |
<PM2_CNT_BLK > |
Register |
Size (Bytes) |
Address (relative to register block) |
PM_TMR |
PM_TMR_LEN |
<PM_TMR_BLK > |
Register |
Size (Bytes) |
Address (relative to register block) |
P_CNT |
4 |
Either <P_BLK> or specified by the PTC object (See section 8.3.1, "PTC [Processor Throttling Control].") |
P_LVL2 |
1 |
<P_BLK>+4h |
P_LVL3 |
1 |
<P_BLK>+5h |
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Register |
Size (Bytes) |
Address (relative to register block) |
GPE0_STS |
GPE0_LEN/2 |
<GPE0_BLK> |
GPE0_EN |
GPE0_LEN/2 |
<GPE0_BLK>+GPE0_LEN/2 |
GPE1_STS |
GPE1_LEN/2 |
<GPE1_BLK> |
GPE1_EN |
GPE1_LEN/2 |
<GPE1_BLK>+GPE1_LEN/2 |
Indicated Support |
PWR_BUTTON Flag |
Power Button Device Object |
Fixed hardware power button |
Clear |
Absent |
Control method power button |
Set |
Present |
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Indicated Support |
SLEEP_BUTTON Flag |
Sleep Button Device Object |
No sleep button |
Set |
Absent |
Fixed hardware sleep button |
Clear |
Absent |
Control method sleep button |
Set |
Present |
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Field |
Value |
Address (Location) in RTC CMOS RAM (Must be Bank 0) |
DAY_ALRM |
Eight bit value that can represent 0x01-0x31 days in BCD or 0x01-0x1F days in binary. Bits 6 and 7 of this field are treated as Ignored by software. The RTC is initialized such that this field contains a "don't care" value when the BIOS switches from legacy to ACPI mode. A don't care value can be any unused value (not 0x1-0x31 BCD or 0x01-0x1F hex) that the RTC reverts back to a 24 hour alarm. |
The DAY_ALRM field in the FADT will contain a non-zero value that represents an offset into the RTC's CMOS RAM area that contains the day alarm value. A value of zero in the DAY_ALRM field indicates that the day alarm feature is not supported. |
MON_ALRM |
Eight bit value that can represent 01-12 months in BCD or 0x01-0xC months in binary. The RTC is initialized such that this field contains a don't care value when the BIOS switches from legacy to ACPI mode. A "don't care" value can be any unused value (not 1-12 BCD or x01-xC hex) that the RTC reverts back to a 24 hour alarm and/or 31 day alarm). |
The MON_ALRM field in the FADT will contain a non-zero value that represents an offset into the RTC's CMOS RAM area that contains the month alarm value. A value of zero in the MON_ALRM field indicates that the month alarm feature is not supported. If the month alarm is supported, the day alarm function must also be supported. |
CENTURY |
8-bit BCD or binary value. This value indicates the thousand year and hundred year (Centenary) variables of the date in BCD (19 for this century, 20 for the next) or binary (x13 for this century, x14 for the next). |
The CENTURY field in the FADT will contain a non-zero value that represents an offset into the RTC's CMOS RAM area that contains the Centenary value for the date. A value of zero in the CENTURY field indicates that the Centenary value is not supported by this RTC. |
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Name |
Description | |
0 |
TMR_STS |
This is the timer carry status bit. This bit gets set any time the 23rd/31st bit of a 24/32-bit counter changes (whenever the MSB changes from clear to set or set to clear. While TMR_EN and TMR_STS are set, an interrupt event is raised. |
1-3 |
Reserved |
Reserved |
4 |
BM_STS |
This is the bus master status bit. This bit is set any time a system bus master requests the system bus, and can only be cleared by writing a "1" to this bit position. Notice that this bit reflects bus master activity, not CPU activity (this bit monitors any bus master that can cause an incoherent cache for a processor in the C3 state when the bus master performs a memory transaction). |
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Bit |
Name |
Description |
5 |
GBL_STS |
This bit is set when an SCI is generated due to the BIOS wanting the attention of the SCI handler. BIOS will have a control bit (somewhere within its address space) that will raise an SCI and set this bit. This bit is set in response to the BIOS releasing control of the Global Lock and having seen the pending bit set. |
6-7 |
Reserved |
Reserved. These bits always return a value of zero. |
8 |
PWRBTN_STS |
This optional bit is set when the Power Button is pressed the system working state, while PWRBTN_EN and PWRBTN_STS are both set, an interrupt event is raised. In the sleeping or soft-off state, a wake event is generated when the power button is pressed (regardless of the PWRBTN_EN bit setting). This bit is only set by hardware and can only be reset by software writing a "1" to this bit position. ACPI defines an optional mechanism for unconditional transitioning a system that has stopped working from the G0 working state into the G2 soft-off state called the power button override. If the Power Button is held active for more than four seconds, this bit is cleared by hardware and the system transitions into the G2/S5 Soft Off state (unconditionally). Support for the power button is indicated by the PWR_BUTTON flag in the FADT being reset (zero). If the PWR_BUTTON flag is set or a power button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM. If the power button was the cause of the wake (from an S1-S4 state), then this bit is set prior to returning control to OSPM. |
9 |
SLPBTN_STS |
This optional bit is set when the sleep button is pressed the system working state, while SLPBTN_EN and SLPBTN_STS are both set, an interrupt event is raised. In the sleeping or soft-off states a wake event is generated when the sleeping button is pressed and the SLPBTN_EN bit is set. This bit is only set by hardware and can only be reset by software writing a "1" to this bit position. Support for the sleep button is indicated by the SLP_BUTTON flag in the FADT being reset (zero). If the SLP_BUTTON flag is set or a sleep button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM. If the sleep button was the cause of the wake (from an S1-S4 state), then this bit is set prior to returning control to OSPM. |
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Bit |
Name |
Description |
10 |
RTC_STS |
This optional bit is set when the RTC generates an alarm (asserts the RTC IRQ signal). Additionally, if the RTC_EN bit is set then the setting of the RTC_STS bit will generate a power management event (an SCI, SMI, or resume event). This bit is only set by hardware and can only be reset by software writing a "1" to this bit position. If the RTC was the cause of the wake (from an S1-S3 state), then this bit is set prior to returning control to OSPM. If the RTC_S4 flag within the FADT is set, and the RTC was the cause of the wake from the S4 state), then this bit is set prior to returning control to OSPM. |
11 |
Ignore |
This bit field is ignored by software. |
12-13 |
Reserved |
Reserved. These bits always return a value of zero. |
14 |
PCIEXP_WAKE_STS |
This bit is required for chipsets that implement PCI Express. This bit is set by hardware to indicate that the system woke due to a PCI Express wakeup event. A PCI Express wakeup event is defined as the PCI Express WAKE# pin being active , one or more of the PCI Express ports being in the beacon state, or receipt of a PCI Express PME message at a root port. This bit should only be set when one of these events causes the system to transition from a non-S0 system power state to the S0 system power state. This bit is set independent of the state of the PCIEXP_WAKE_DIS bit. Software writes a 1 to clear this bit. If the WAKE# pin is still active during the write, one or more PCI Express ports is in the beacon state or the PME message received indication has not been cleared in the root port, then the bit will remain active (i.e. all inputs to this bit are level-sensitive). Note: This bit does not itself cause a wake event or prevent entry to a sleeping state. Thus if the bit is 1 and the system is put into a sleeping state, the system will not automatically wake. |
15 |
WAK_STS |
This bit is set when the system is in the sleeping state and an enabled wake event occurs. Upon setting this bit system will transition to the working state. This bit is set by hardware and can only be cleared by software writing a "1" to this bit position. |
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Bit |
Name |
Description |
0 |
TMR_EN |
This is the timer carry interrupt enable bit. When this bit is set then an SCI event is generated anytime the TMR_STS bit is set. When this bit is reset then no interrupt is generated when the TMR_STS bit is set. |
1-4 |
Reserved |
Reserved. These bits always return a value of zero. |
5 |
GBL_EN |
The global enable bit. When both the GBL_EN bit and the GBL_STS bit are set, an SCI is raised. |
6-7 |
Reserved |
Reserved |
8 |
PWRBTN_EN |
This optional bit is used to enable the setting of the PWRBTN_STS bit to generate a power management event (SCI or wake) PWRBTN_STS bit is set anytime the power button is asserted. The enable bit does not have to be set to enable the setting of the PWRBTN_STS bit by the assertion of the power button (see description of the power button hardware). Support for the power button is indicated by the PWR_BUTTON flag in the FADT being reset (zero). If the PWR_BUTTON flag is set or a power button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM. |
9 |
SLPBTN_EN |
This optional bit is used to enable the setting of the SLPBTN_STS bit to generate a power management event (SCI or wake) SLPBTN_STS bit is set anytime the sleep button is asserted. The enable bit does not have to be set to enable the setting of the SLPBTN_STS bit by the active assertion of the sleep button (see description of the sleep button hardware). Support for the sleep button is indicated by the SLP_BUTTON flag in the FADT being reset (zero). If the SLP_BUTTON flag is set or a sleep button device object is present in the ACPI Namespace, then this bit field is ignored by OSPM. |
10 |
RTC_EN |
This optional bit is used to enable the setting of the RTC_STS bit to generate a wake event. The RTC_STS bit is set any time the RTC generates an alarm. |
11-13 |
Reserved |
Reserved. These bits always return a value of zero. |
PCIEXP_WAKE_DIS |
This bit is required for chipsets that implement PCI Express. This bit disables the inputs to the PCIEXP_WAKE_STS bit in the PM1 Status register from waking the system. Modification of this bit has no impact on the value of the PCIEXP_WAKE_STS bit. | |
15 |
Reserved |
Reserved. These bits always return a value of zero. |
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Bit |
Name |
Description |
0 |
SCI_EN |
Selects the power management event to be either an SCI or SMI interrupt for the following events. When this bit is set, then power management events will generate an SCI interrupt. When this bit is reset power management events will generate an SMI interrupt. It is the responsibility of the hardware to set or reset this bit. OSPM always preserves this bit position. |
1 |
BM_RLD |
When set, this bit allows the generation of a bus master request to cause any processor in the C3 state to transition to the C0 state. When this bit is reset, the generation of a bus master request does not affect any processor in the C3 state. |
2 |
GBL_RLS |
This write-only bit is used by the ACPI software to raise an event to the BIOS software, that is, generates an SMI to pass execution control to the BIOS for IA-PC platforms. BIOS software has a corresponding enable and status bit to control its ability to receive ACPI events (for example, BIOS_EN and BIOS_STS). The GBL_RLS bit is set by OSPM to indicate a release of the Global Lock and the setting of the pending bit in the FACS memory structure. |
3-8 |
Reserved |
Reserved. These bits are reserved by OSPM. |
9 |
Ignore |
Software ignores this bit field. |
10-12 |
SLP_TYPx |
Defines the type of sleeping state the system enters when the SLP_EN bit is set to one. This 3-bit field defines the type of hardware sleep state the system enters when the SLP_EN bit is set. The \_Sx object contains 3-bit binary values associated with the respective sleeping state (as described by the object). OSPM takes the two values from the \_Sx object and programs each value into the respective SLP_TYPx field. |
13 |
SLP_EN |
This is a write-only bit and reads to it always return a zero. Setting this bit causes the system to sequence into the sleeping state associated with the SLP_TYPx fields programmed with the values from the \_Sx object. |
14-15 |
Reserved |
Reserved. This field always returns zero. |
Bit |
Name |
Description |
0-23 |
TMR_VAL |
This read-only field returns the running count of the power management timer. This is a 24-bit counter that runs off a 3.579545-MHz clock and counts while in the S0 working system state. The starting value of the timer is undefined, thus allowing the timer to be reset (or not) by any transition to the S0 state from any other state. The timer is reset (to any initial value), and then continues counting until the system's 14.31818 MHz clock is stopped upon entering its Sx state. If the clock is restarted without a reset, then the counter will continue counting from where it stopped. |
24-31 |
E_TMR_VAL |
This read-only field returns the upper eight bits of a 32-bit power management timer. If the hardware supports a 32-bit timer, then this field will return the upper eight bits; if the hardware supports a 24-bit timer then this field returns all zeros. |
Bit |
Name |
Description |
0 |
ARB_DIS |
This bit is used to enable and disable the system arbiter. When this bit is CLEAR the system arbiter is enabled and the arbiter can grant the bus to other bus masters. When this bit is SET the system arbiter is disabled and the default CPU has ownership of the system. OSPM clears this bit when using the C0, C1 and C2 power states. |
>0 |
Reserved |
Reserved |
Bit |
Name |
Description |
0-3 |
CLK_VAL |
Possible locations for the clock throttling value. |
4 |
THT_EN |
This bit enables clock throttling of the clock as set in the CLK_VAL field. THT_EN bit must be reset LOW when changing the CLK_VAL field (changing the duty setting). |
5-31 |
CLK_VAL |
Possible locations for the clock throttling value. |
Bit |
Name |
Description |
0-7 |
P_LVL2 |
Reads to this register return all zeros; writes to this register have no effect. Reads to this register also generate an "enter a C2 power state" to the clock control logic. |
Name |
Description | |
0-7 |
P_LVL3 |
Reads to this register return all zeros; writes to this register have no effect. Reads to this register also generate an "enter a C3 power state" to the clock control logic. |
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|
|
|
Field |
Byte Length |
Byte Offset |
Description |
Address_Space_ID |
1 |
0 |
The address space where the data structure or register exists. 0 System Memory 1 System I/O 2 PCI Configuration Space 3 Embedded Controller 4 SMBus 5 to 0x7E – Reserved 0x7F Functional Fixed Hardware 0x80 to 0xBF – Reserved 0xC0 to 0xFF – OEM Defined |
Register_Bit_Width |
1 |
1 |
The size in bits of the given register. When addressing a data structure, this field must be zero. |
Register_Bit_Offset |
1 |
2 |
The bit offset of the given register at the given address. When addressing a data structure, this field must be zero. |
Access_Size |
1 |
3 |
Specifies access size. 0 Undefined (legacy reasons) 1 Byte access 2 Word access 3 Dword access 4 Qword access |
Address |
8 |
4 |
The 64-bit address of the data structure or register in the given address space (relative to the processor). (See below for specific formats.) |
|
Address Space |
Format | |
0–System Memory |
The 64-bit physical memory address (relative to the processor) of the register. 32-bit platforms must have the high DWORD set to 0. | |
1–System I/O |
The 64-bit I/O address (relative to the processor) of the register. 32-bit platforms must have the high DWORD set to 0. | |
2–PCI Configuration Space |
PCI Configuration space addresses must be confined to devices on PCI Segment Group 0, bus 0. This restriction exists to accommodate access to fixed hardware prior to PCI bus enumeration. The format of addresses are defined as follows: | |
WORD Location |
Description | |
Highest WORD |
Reserved (must be 0) | |
… |
PCI Device number on bus 0 | |
… |
PCI Function number | |
Lowest WORD |
Offset in the configuration space header | |
For example: Offset 23h of Function 2 on device 7 on bus 0 segment 0 would be represented as: 0x0000000700020023. | ||
0x7F–Functional Fixed Hardware |
Use of GAS fields other than Address_Space_ID is specified by the CPU manufacturer. The use of functional fixed hardware carries with it a reliance on OS specific software that must be considered. OEMs should consult OS vendors to ensure that specific functional fixed hardware interfaces are supported by specific operating systems. |
Byte Length |
Byte Offset |
Description | |
Signature |
8 |
0 |
"RSD PTR " (Notice that this signature must contain a trailing blank character.) |
Checksum |
1 |
8 |
This is the checksum of the fields defined in the ACPI 1.0 specification. This includes only the first 20 bytes of this table, bytes 0 to 19, including the checksum field. These bytes must sum to zero. |
OEMID |
6 |
9 |
An OEM-supplied string that identifies the OEM. |
Revision |
1 |
15 |
The revision of this structure. Larger revision numbers are backward compatible to lower revision numbers. The ACPI version 1.0 revision number of this table is zero. The current value for this field is 2. |
RsdtAddress |
4 |
16 |
32 bit physical address of the RSDT. |
Length |
4 |
20 |
The length of the table, in bytes, including the header, starting from offset 0. This field is used to record the size of the entire table. |
XsdtAddress |
8 |
24 |
64 bit physical address of the XSDT. |
Extended Checksum |
1 |
32 |
This is a checksum of the entire table, including both checksum fields. |
Reserved |
3 |
33 |
Reserved field |
Field |
Byte Length |
Byte Offset |
Description |
Signature |
4 |
0 |
The ASCII string representation of the table identifier. Notice that if OSPM finds a signature in a table that is not listed in Table 5-5, OSPM ignores the entire table (it is not loaded into ACPI namespace); OSPM ignores the table even though the values in the Length and Checksum fields are correct. |
Length |
4 |
4 |
The length of the table, in bytes, including the header, starting from offset 0. This field is used to record the size of the entire table. |
Revision |
1 |
8 |
The revision of the structure corresponding to the signature field for this table. Larger revision numbers are backward compatible to lower revision numbers with the same signature. |
Checksum |
1 |
9 |
The entire table, including the checksum field, must add to zero to be considered valid. |
OEMID |
6 |
10 |
An OEM-supplied string that identifies the OEM. |
OEM Table ID |
8 |
16 |
An OEM-supplied string that the OEM uses to identify the particular data table. This field is particularly useful when defining a definition block to distinguish definition block functions. The OEM assigns each dissimilar table a new OEM Table ID. |
OEM Revision |
4 |
24 |
An OEM-supplied revision number. Larger numbers are assumed to be newer revisions. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler. |
Description |
Reference | |
"APIC" |
Multiple APIC Description Table |
Section 5.2.11.4, "Multiple APIC Description Table" |
"DSDT" |
Differentiated System Description Table |
Section 5.2.11.1, "Differentiated System Description Table" |
"ECDT" |
Embedded Controller Boot Resources Table |
Section 5.2.14, "Embedded Controller Boot Resources Table" |
"FACP" |
Fixed ACPI Description Table (FADT) |
Section 5.2.9, "Fixed ACPI Description Table" |
"FACS" |
Firmware ACPI Control Structure |
Section 5.2.10, "Firmware ACPI Control Structure" |
"OEMx" |
OEM Specific Information Tables |
OEM Specific tables. All table signatures starting with "OEM" are reserved for OEM use. |
"PSDT" |
Persistent System Description Table |
Section 5.2.11.3, "Persistent System Description Table" |
"RSDT" |
Root System Description Table |
Section 5.2.7, "Root System Description Table" |
"SBST" |
Smart Battery Specification Table |
Section 5.2 13, "Smart Battery Table" |
"SLIT" |
System Locality Distance Information Table |
Section 5.2.16, "System Locality Distance Information Table" |
"SRAT" |
System Resource Affinity Table |
Section 5.2.15, "System Resource Affinity Table" |
"SSDT" |
Secondary System Description Table |
Section 5.2.11.2, "Secondary System Description Table" |
"XSDT" |
Extended System Description Table |
Section 5.2.8, "Extended System Description Table" |
Signature |
Description |
Comments / Reference |
"BERT" |
Boot Error Record Table | |
"BOOT" |
Simple Boot Flag Table |
Microsoft Simple Boot Flag Specification |
"CPEP" |
Corrected Platform Error Polling Table |
DIG64 Corrected Platform Error Polling Specification http://www.dig64.org/specifications |
"DBGP" |
Debug Port Table |
Microsoft Debug Port Specification |
"DMAR" |
DMA Remapping Table |
http://download.intel.com/technology/computing/vptech/Intel(r)_VT_for_Direct_IO.pdf |
"ERST" |
Error Record Serialization Table | |
"ETDT" |
Event Timer Description Table |
IA-PC Multimedia Timers Specification. This signature has been superseded by "HPET" and is now obsolete. |
"HEST" |
Hardware Error Source Table | |
"HPET" |
IA-PC High Precision Event Timer Table |
IA-PC High Precision Event Timer Specification. http://www.intel.com/hardwaredesign/hpetspec.htm |
"IBFT" |
iSCSI Boot Firmware Table | |
"MCFG" |
PCI Express memory mapped configuration space base address Description Table |
PCI Firmware Specification, Revision 3.0 http://pcisig.com |
"SPCR" |
Serial Port Console Redirection Table |
Microsoft Serial Port Console Redirection Table http://www.microsoft.com/HWDEV/PLATFORM/server/headless/SPCR.asp |
"SPMI" |
Server Platform Management Interface Table |
ftp://download.intel.com/design/servers/ipmi/IPMIv2_0rev1_0.pdf |
"TCPA" |
Trusted Computing Platform Alliance Capabilities Table |
TCPA PC Specific Implementation Specification https://www.trustedcomputinggroup.org/home |
"UEFI" |
UEFI ACPI Boot Optimization Table |
UEFI Specification, http://www.uefi.org. |
"WAET" |
Windows ACPI Enlightenment Table | |
"WDAT" |
Watch Dog Action Table |
Requirements for Hardware Watchdog Timers Supported by Windows – Design Specification |
"WDRT" |
Watchdog Resource Table |
Watchdog Timer Hardware Requirements for Windows Server 2003 |
"WSPT" |
Windows Specific Properties Table |
Byte Length |
Byte Offset |
Description | |
Header |
|
|
|
Signature |
4 |
0 |
'RSDT' Signature for the Root System Description Table. |
Length |
4 |
4 |
Length, in bytes, of the entire RSDT. The length implies the number of Entry fields (n) at the end of the table. |
Revision |
1 |
8 |
1 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
For the RSDT, the table ID is the manufacture model ID. This field must match the OEM Table ID in the FADT. |
OEM Revision |
4 |
24 |
OEM revision of RSDT table for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler. |
Entry |
4*n |
36 |
An array of 32-bit physical addresses that point to other DESCRIPTION_HEADERs. OSPM assumes at least the DESCRIPTION_HEADER is addressable, and then can further address the table based upon its Length field. |
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'XSDT'. Signature for the Extended System Description Table. |
Length |
4 |
4 |
Length, in bytes, of the entire table. The length implies the number of Entry fields (n) at the end of the table. |
Revision |
1 |
8 |
1 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
For the XSDT, the table ID is the manufacture model ID. This field must match the OEM Table ID in the FADT. |
OEM Revision |
4 |
24 |
OEM revision of XSDT table for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler. |
Entry |
8*n |
36 |
An array of 64-bit physical addresses that point to other DESCRIPTION_HEADERs. OSPM assumes at least the DESCRIPTION_HEADER is addressable, and then can further address the table based upon its Length field. |
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'FACP'. Signature for the Fixed ACPI Description Table. |
Length |
4 |
4 |
Length, in bytes, of the entire FADT. |
Revision |
1 |
8 |
4 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
For the FADT, the table ID is the manufacture model ID. This field must match the OEM Table ID in the RSDT. |
OEM Revision |
4 |
24 |
OEM revision of FADT for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler. |
FIRMWARE_CTRL |
4 |
36 |
Physical memory address (0-4 GB) of the FACS, where OSPM and Firmware exchange control information. See section 5.2.6, "Root System Description Table," for a description of the FACS. |
DSDT |
4 |
40 |
Physical memory address (0-4 GB) of the DSDT. |
Reserved |
1 |
44 |
ACPI 1.0 defined this offset as a field named INT_MODEL, which was eliminated in ACPI 2.0. Platforms should set this field to zero but field values of one are also allowed to maintain compatibility with ACPI 1.0. |
Preferred_PM_Profile |
1 |
45 |
This field is set by the OEM to convey the preferred power management profile to OSPM. OSPM can use this field to set default power management policy parameters during OS installation. Field Values: 0 Unspecified 1 Desktop 2 Mobile 3 Workstation 4 Enterprise Server 5 SOHO Server 6 Appliance PC 7 Performance Server >7 Reserved |
SCI_INT |
2 |
46 |
System vector the SCI interrupt is wired to in 8259 mode systems that do not contain the 8259, this field contains the Global System interrupt number of the SCI interrupt. OSPM is required to treat the ACPI SCI interrupt as a sharable, level, active low interrupt. |
SMI_CMD |
4 |
48 |
System port address of the SMI Command Port. During ACPI OS initialization, OSPM can determine that the ACPI hardware registers are owned by SMI (by way of the SCI_EN bit), in which case the ACPI OS issues the ACPI_ENABLE command to the SMI_CMD port. The SCI_EN bit effectively tracks the ownership of the ACPI hardware registers. OSPM issues commands to the SMI_CMD port synchronously from the boot processor. This field is reserved and must be zero on system that does not support System Management mode. |
ACPI_ENABLE
|
1 |
52 |
The value to write to SMI_CMD to disable SMI ownership of the ACPI hardware registers. The last action SMI does to relinquish ownership is to set the SCI_EN bit. During the OS initialization process, OSPM will synchronously wait for the transfer of SMI ownership to complete, so the ACPI system releases SMI ownership as quickly as possible. This field is reserved and must be zero on systems that do not support Legacy Mode. |
ACPI_DISABLE |
1 |
53 |
The value to write to SMI_CMD to re-enable SMI ownership of the ACPI hardware registers. This can only be done when ownership was originally acquired from SMI by OSPM using ACPI_ENABLE. An OS can hand ownership back to SMI by relinquishing use to the ACPI hardware registers, masking off all SCI interrupts, clearing the SCI_EN bit and then writing ACPI_DISABLE to the SMI_CMD port from the boot processor. This field is reserved and must be zero on systems that do not support Legacy Mode. |
S4BIOS_REQ |
1 |
54 |
The value to write to SMI_CMD to enter the S4BIOS state S4BIOS state provides an alternate way to enter the S4 state where the firmware saves and restores the memory context. A value of zero in S4BIOS_F indicates S4BIOS_REQ is not supported. (See Table 5-12.) |
PSTATE_CNT |
1 |
55 |
If non-zero, this field contains the value OSPM writes to the SMI_CMD register to assume processor performance state control responsibility. |
PM1a_EVT_BLK |
4 |
56 |
System port address of the PM1a Event Register Block section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This is a required field. This field is superseded by the X_PM1a_EVT_BLK field. |
PM1b_EVT_BLK |
4 |
60 |
System port address of the PM1b Event Register Block section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. This field is superseded by the X_PM1b_EVT_BLK field. |
PM1a_CNT_BLK |
4 |
64 |
System port address of the PM1a Control Register Block section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This is a required field. This field is superseded by the X_PM1a_CNT_BLK field. |
PM1b_CNT_BLK |
4 |
68 |
System port address of the PM1b Control Register Block section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. This field is superseded by the X_PM1b_CNT_BLK field. |
PM2_CNT_BLK |
4 |
72 |
System port address of the PM2 Control Register Block section 4.7.3.4, "PM2 Control (PM2_CNT)," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. This field is superseded by the X_PM2_CNT_BLK field. |
PM_TMR_BLK |
4 |
76 |
System port address of the Power Management Timer Control Register Block. See section 4.7.3.3, "Power Management Timer (PM_TMR)," for a hardware description layout of this register block. This is a required field. This field is superseded by the X_PM_TMR_BLK field. |
GPE0_BLK |
4 |
80 |
System port address of General-Purpose Event 0 Register Block. See section 4.7.4.1, "General-Purpose Event Register Blocks," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero. This field is superseded by the X_GPE0_BLK field. |
GPE1_BLK |
4 |
84 |
System port address of General-Purpose Event 1 Register Block. See section 4.7.4.1, "General-Purpose Event Register Blocks," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero. This field is superseded by the X_GPE1_BLK field. |
PM1_EVT_LEN |
1 |
88 |
Number of bytes decoded by PM1a_EVT_BLK and, if supported, PM1b_ EVT_BLK. This value is ³ 4. |
PM1_CNT_LEN |
1 |
89 |
Number of bytes decoded by PM1a_CNT_BLK and, if supported, PM1b_CNT_BLK. This value is ³ 2. |
PM2_CNT_LEN |
1 |
90 |
Number of bytes decoded by PM2_CNT_BLK. Support for the PM2 register block is optional. If supported, this value is ³ 1. If not supported, this field contains zero. |
PM_TMR_LEN |
1 |
91 |
Number of bytes decoded by PM_TMR_BLK. This field's value must be 4. |
GPE0_BLK_LEN |
1 |
92 |
Number of bytes decoded by GPE0_BLK. The value is a non-negative multiple of 2. |
GPE1_BLK_LEN |
1 |
93 |
Number of bytes decoded by GPE1_BLK. The value is a non-negative multiple of 2. |
GPE1_BASE |
1 |
94 |
Offset within the ACPI general-purpose event model where GPE1 based events start. |
CST_CNT |
1 |
95 |
If non-zero, this field contains the value OSPM writes to the SMI_CMD register to indicate OS support for the _CST object and C States Changed notification. |
P_LVL2_LAT |
2 |
96 |
The worst-case hardware latency, in microseconds, to enter and exit a C2 state. A value > 100 indicates the system does not support a C2 state. |
P_LVL3_LAT |
2 |
98 |
The worst-case hardware latency, in microseconds, to enter and exit a C3 state. A value > 1000 indicates the system does not support a C3 state. |
FLUSH_SIZE |
2 |
100 |
If WBINVD=0, the value of this field is the number of flush strides that need to be read (using cacheable addresses) to completely flush dirty lines from any processor's memory caches. Notice that the value in FLUSH_STRIDE is typically the smallest cache line width on any of the processor's caches (for more information, see the FLUSH_STRIDE field definition). If the system does not support a method for flushing the processor's caches, then FLUSH_SIZE and WBINVD are set to zero. Notice that this method of flushing the processor caches has limitations, and WBINVD=1 is the preferred way to flush the processors caches. This value is typically at least 2 times the cache size. The maximum allowed value for FLUSH_SIZE multiplied by FLUSH_STRIDE is 2 MB for a typical maximum supported cache size of 1 MB. Larger cache sizes are supported using WBINVD=1. This value is ignored if WBINVD=1. This field is maintained for ACPI 1.0 processor compatibility on existing systems. Processors in new ACPI-compatible systems are required to support the WBINVD function and indicate this to OSPM by setting the WBINVD field = 1. |
FLUSH_STRIDE |
2 |
102 |
If WBINVD=0, the value of this field is the cache line width, in bytes, of the processor's memory caches. This value is typically the smallest cache line width on any of the processor's caches. For more information, see the description of the FLUSH_SIZE field. This value is ignored if WBINVD=1. This field is maintained for ACPI 1.0 processor compatibility on existing systems. Processors in new ACPI-compatible systems are required to support the WBINVD function and indicate this to OSPM by setting the WBINVD field = 1. |
DUTY_OFFSET |
1 |
104 |
The zero-based index of where the processor's duty cycle setting is within the processor's P_CNT register. |
DUTY_WIDTH |
1 |
105 |
The bit width of the processor's duty cycle setting value in the P_CNT register. Each processor's duty cycle setting allows the software to select a nominal processor frequency below its absolute frequency as defined by: THTL_EN = 1 BF * DC/(2DUTY_WIDTH) Where: BF–Base frequency DC–Duty cycle setting When THTL_EN is 0, the processor runs at its absolute BF. A DUTY_WIDTH value of 0 indicates that processor duty cycle is not supported and the processor continuously runs at its base frequency. |
DAY_ALRM |
1 |
106 |
The RTC CMOS RAM index to the day-of-month alarm value this field contains a zero, then the RTC day of the month alarm feature is not supported. If this field has a non-zero value, then this field contains an index into RTC RAM space that OSPM can use to program the day of the month alarm. See section 4.7.2.4, "Real Time Clock Alarm," for a description of how the hardware works. |
MON_ALRM |
1 |
107 |
The RTC CMOS RAM index to the month of year alarm value this field contains a zero, then the RTC month of the year alarm feature is not supported. If this field has a non-zero value, then this field contains an index into RTC RAM space that OSPM can use to program the month of the year alarm. If this feature is supported, then the DAY_ALRM feature must be supported also. |
CENTURY |
1 |
108 |
The RTC CMOS RAM index to the century of data value (hundred and thousand year decimals). If this field contains a zero, then the RTC centenary feature is not supported. If this field has a non-zero value, then this field contains an index into RTC RAM space that OSPM can use to program the centenary field. |
IAPC_BOOT_ARCH |
2 |
109 |
IA-PC Boot Architecture Flags. See Table 5-11 for a description of this field. |
Reserved |
1 |
111 |
Must be 0. |
Flags |
4 |
112 |
Fixed feature flags. See Table 5-10 for a description of this field. |
RESET_REG |
12 |
116 |
The address of the reset register represented in Generic Address Structure format (See section 4.7.3.6, "Reset Register," for a description of the reset mechanism.) Note: Only System I/O space, System Memory space and PCI Configuration space (bus #0) are valid for values for Address_Space_ID. Also, Register_Bit_Width must be 8 and Register_Bit_Offset must be 0. |
RESET_VALUE |
1 |
128 |
Indicates the value to write to the RESET_REG port to reset the system. (See section 4.7.3.6, "Reset Register," for a description of the reset mechanism.) |
Reserved |
3 |
129 |
Must be 0. |
X_FIRMWARE_CTRL |
8 |
132 |
64bit physical address of the FACS. |
X_DSDT |
8 |
140 |
64bit physical address of the DSDT. |
X_PM1a_EVT_BLK |
12 |
148 |
Extended address of the PM1a Event Register Block, represented in Generic Address Structure format. See section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This is a required field. |
X_PM1b_EVT_BLK |
12 |
160 |
Extended address of the PM1b Event Register Block, represented in Generic Address Structure format. See section 4.7.3.1, "PM1 Event Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. |
X_PM1a_CNT_BLK |
12 |
172 |
Extended address of the PM1a Control Register Block, represented in Generic Address Structure format. See section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This is a required field. |
X_PM1b_CNT_BLK |
12 |
184 |
Extended address of the PM1b Control Register Block, represented in Generic Address Structure format. See section 4.7.3.2, "PM1 Control Grouping," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. |
X_PM2_CNT_BLK |
12 |
196 |
Extended address of the Power Management 2 Control Register Block, represented in Generic Address Structure format. See section 4.7.3.4, "PM2 Control (PM2_CNT)," for a hardware description layout of this register block. This field is optional; if this register block is not supported, this field contains zero. |
X_PM_TMR_BLK |
12 |
208 |
Extended address of the Power Management Timer Control Register Block, represented in Generic Address Structure format. See section 4.7.3.3, "Power Management Timer (PM_TMR)," for a hardware description layout of this register block. This is a required field. |
X_GPE0_BLK |
12 |
220 |
Extended address of the General-Purpose Event 0 Register Block, represented in Generic Address Structure format. See section 5.2.8, "Fixed ACPI Description Table," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero. |
X_GPE1_BLK |
12 |
232 |
Extended address of the General-Purpose Event 1 Register Block, represented in Generic Address Structure format. See section 5.2.8, "Fixed ACPI Description Table," for a hardware description of this register block. This is an optional field; if this register block is not supported, this field contains zero. |
FACP - Flag |
Bit Length |
Bit Offset |
Description |
WBINVD |
1 |
0 |
Processor properly implements a functional equivalent to the WBINVD IA-32 instruction. If set, signifies that the WBINVD instruction correctly flushes the processor caches, maintains memory coherency, and upon completion of the instruction, all caches for the current processor contain no cached data other than what OSPM references and allows to be cached. If this flag is not set, the ACPI OS is responsible for disabling all ACPI features that need this function. This field is maintained for ACPI 1.0 processor compatibility on existing systems. Processors in new ACPI-compatible systems are required to support this function and indicate this to OSPM by setting this field. |
WBINVD_FLUSH |
1 |
1 |
If set, indicates that the hardware flushes all caches on the WBINVD instruction and maintains memory coherency, but does not guarantee the caches are invalidated. This provides the complete semantics of the WBINVD instruction, and provides enough to support the system sleeping states neither of the WBINVD flags is set, the system will require FLUSH_SIZE and FLUSH_STRIDE to support sleeping states. If the FLUSH parameters are also not supported, the machine cannot support sleeping states S1, S2, or S3. |
PROC_C1 |
1 |
2 |
A one indicates that the C1 power state is supported on all processors. |
P_LVL2_UP |
1 |
3 |
A zero indicates that the C2 power state is configured to only work on a uniprocessor (UP) system. A one indicates that the C2 power state is configured to work on a UP or multiprocessor (MP) system. |
PWR_BUTTON |
1 |
4 |
A zero indicates the power button is handled as a fixed feature programming model; a one indicates the power button is handled as a control method device. If the system does not have a power button, this value would be "1" and no sleep button device would be present. Independent of the value of this field, the presence of a power button device in the namespace indicates to OSPM that the power button is handled as a control method device. |
SLP_BUTTON |
1 |
5 |
A zero indicates the sleep button is handled as a fixed feature programming model; a one indicates the sleep button is handled as a control method device. If the system does not have a sleep button, this value would be "1" and no sleep button device would be present. Independent of the value of this field, the presence of a sleep button device in the namespace indicates to OSPM that the sleep button is handled as a control method device. |
FIX_RTC |
1 |
6 |
A zero indicates the RTC wake status is supported in fixed register space; a one indicates the RTC wake status is not supported in fixed register space. |
RTC_S4 |
1 |
7 |
Indicates whether the RTC alarm function can wake the system from the S4 state. The RTC must be able to wake the system from an S1, S2, or S3 sleep state. The RTC alarm can optionally support waking the system from the S4 state, as indicated by this value. |
TMR_VAL_EXT |
1 |
8 |
A zero indicates TMR_VAL is implemented as a 24-bit value. A one indicates TMR_VAL is implemented as a 32-bit value. The TMR_STS bit is set when the most significant bit of the TMR_VAL toggles. |
DCK_CAP |
1 |
9 |
A zero indicates that the system cannot support docking. A one indicates that the system can support docking. Notice that this flag does not indicate whether or not a docking station is currently present; it only indicates that the system is capable of docking. |
RESET_REG_SUP |
1 |
10 |
If set, indicates the system supports system reset via the FADT RESET_REG as described in section 4.7. 3.6, "Reset Register." |
SEALED_CASE |
1 |
11 |
System Type Attribute. If set indicates that the system has no internal expansion capabilities and the case is sealed. |
HEADLESS |
1 |
12 |
System Type Attribute. If set indicates the system cannot detect the monitor or keyboard / mouse devices. |
CPU_SW_SLP |
1 |
13 |
If set, indicates to OSPM that a processor native instruction must be executed after writing the SLP_TYPx register. |
PCI_EXP_WAK |
1 |
14 |
If set, indicates the platform supports the PCIEXP_WAKE_STS bit in the PM1 Status register and the PCIEXP_WAKE_EN bit in the PM1 Enable register. |
USE_PLATFORM_CLOCK |
1 |
15 |
A value of one indicates that OSPM should use a platform provided timer to drive any monotonically non-decreasing counters, such as OSPM performance counter services. Which particular platform timer will be used is OSPM specific, however, it is recommended that the timer used is based on the following algorithm: If the HPET is exposed to OSPM, OSPM should use the HPET. Otherwise, OSPM will use the ACPI power management timer. A value of one indicates that the platform is known to have a correctly implemented ACPI power management timer.
A platform may choose to set this flag if a internal processor clock (or clocks in a multi-processor configuration) cannot provide consistent monotonically non-decreasing counters.
Note: If a value of zero is present, OSPM may arbitrarily choose to use an internal processor clock or a platform timer clock for these operations. That is, a zero does not imply that OSPM will necessarily use the internal processor clock to generate a monotonically non-decreasing counter to the system. |
S4_RTC_STS_VALID |
1 |
16 |
A one indicates that the contents of the RTC_STS flag is valid when waking the system from S4. See Table 4-11 – PM1 Status Registers Fixed Hardware Feature Status Bits for more information. Some existing systems do not reliably set this input today, and this bit allows OSPM to differentiate correctly functioning platforms from platforms with this errata. |
REMOTE_POWER_ON_CAPABLE |
1 |
17 |
A one indicates that the platform is compatible with remote power on. That is, the platform supports OSPM leaving GPE wake events armed prior to an S5 transition. Some existing platforms do not reliably transition to S5 with wake events enabled (for example, the platform may immediately generate a spurious wake event after completing the S5 transition). This flag allows OSPM to differentiate correctly functioning platforms from platforms with this type of errata. |
FORCE_ APIC_CLUSTER_MODEL |
1 |
18 |
A one indicates that all local APICs must be configured for the cluster destination model when delivering interrupts in logical mode. If this bit is set, then logical mode interrupt delivery operation may be undefined until OSPM has moved all local APICs to the cluster model. Note that the cluster destination model doesn't apply to Itanium processor local SAPICs. This bit is intended for xAPIC based machines that require the cluster destination model even when 8 or fewer local APICs are present in the machine. |
FORCE_APIC_PHYSICAL_DESTINATION_MODE |
1 |
19 |
A one indicates that all local xAPICs must be configured for physical destination mode. If this bit is set, interrupt delivery operation in logical destination mode is undefined. On machines that contain fewer than 8 local xAPICs or that do not use the xAPIC architecture, this bit is ignored. |
Reserved |
12 |
20 |
|
BOOT_ARCH |
Bit length |
Bit offset |
Description |
LEGACY_DEVICES |
1 |
0 |
If set, indicates that the motherboard supports user-visible devices on the LPC or ISA bus. User-visible devices are devices that have end-user accessible connectors (for example, LPT port), or devices for which the OS must load a device driver so that an end-user application can use a device. If clear, the OS may assume there are no such devices and that all devices in the system can be detected exclusively via industry standard device enumeration mechanisms (including the ACPI namespace). |
8042 |
1 |
1 |
If set, indicates that the motherboard contains support for a port 60 and 64 based keyboard controller, usually implemented as an 8042 or equivalent micro-controller. |
VGA Not Present |
1 |
2 |
If set, indicates to OSPM that it must not blindly probe the VGA hardware (that responds to MMIO addresses A0000h-BFFFFh and IO ports 3B0h-3BBh and 3C0h-3DFh) that may cause machine check on this system. If clear, indicates to OSPM that it is safe to probe the VGA hardware.. |
MSI Not Supported |
1 |
3 |
If set, indicates to OSPM that it must not enable Message Signaled Interrupts (MSI) on this platform. |
PCIe ASPM Controls |
1 |
4 |
If set, indicates to OSPM that it must not enable OSPM ASPM control on this platform. |
Reserved |
11 |
5 |
Must be 0. |
Byte Length |
Byte Offset |
Description | |
Signature |
4 |
0 |
'FACS' |
Length |
4 |
4 |
Length, in bytes, of the entire Firmware ACPI Control Structure. This value is 64 bytes or larger. |
Hardware Signature |
4 |
8 |
The value of the system's "hardware signature" at last boot. This value is calculated by the BIOS on a best effort basis to indicate the base hardware configuration of the system such that different base hardware configurations can have different hardware signature values. OSPM uses this information in waking from an S4 state, by comparing the current hardware signature to the signature values saved in the non-volatile sleep image the values are not the same, OSPM assumes that the saved non-volatile image is from a different hardware configuration and cannot be restored. |
Firmware_Waking_ |
4 |
12 |
This field is superseded by the X_Firmware_Waking_Vector field. The 32-bit address field where OSPM puts its waking vector. Before transitioning the system into a global sleeping state, OSPM fills in this field with the physical memory address of an OS-specific wake function. During POST, the platform firmware first checks if the value of the X_Firmware_Waking_Vector field is non-zero and if so transfers control to OSPM as outlined in the X_Firmware_Waking_vector field description below the X_Firmware_Waking_Vector field is zero then the platform firmware checks the value of this field and if it is non-zero, transfers control to the specified address. On PCs, the wake function address is in memory below 1 MB and the control is transferred while in real mode. OSPM's wake function restores the processors' context. For IA-PC platforms, the following example shows the relationship between the physical address in the Firmware Waking Vector and the real mode address the BIOS jumps to. If, for example, the physical address is 0x12345, then the BIOS must jump to real mode address 0x1234:0x0005. In general this relationship is Real-mode address = Physical address>>4 : Physical address and 0x000F Notice that on IA-PC platforms, A20 must be enabled when the BIOS jumps to the real mode address derived from the physical address stored in the Firmware Waking Vector. |
Field |
Byte Length |
Byte Offset |
Description |
Global_Lock |
4 |
16 |
This field contains the Global Lock used to synchronize access to shared hardware resources between the OSPM environment and an external controller environment (for example, the SMI environment). This lock is owned exclusively by either OSPM or the firmware at any one time. When ownership of the lock is attempted, it might be busy, in which case the requesting environment exits and waits for the signal that the lock has been released. For example, the Global Lock can be used to protect an embedded controller interface such that only OSPM or the firmware will access the embedded controller interface at any one time. See section 5.2.10.1, "Global Lock," for more information on acquiring and releasing the Global Lock. |
Flags |
4 |
20 |
Firmware control structure flags. See Table 5-13 for a description of this field. |
X_Firmware_Waking_Vector |
8 |
24 |
64-bit physical address of OSPM's Waking Vector. Before transitioning the system into a global sleeping state, OSPM fills in this field with the physical memory address of an OS-specific wake function. During POST, the platform firmware checks if the value of this field is non-zero and if so transfers control to OSPM by jumping to this address. Prior to transferring control, the execution environment must be configured as follows: Memory address translation / paging and interrupts must be disabled. For IA 32-bit platforms, a 4GB flat address space for all segment registers and EFLAGS.IF set to 0. For 64-bit ItaniumTM-based platforms, the processor must have psr.i, psr.it, psr.dt, and psr.rt set to 0. See the Intel® ItaniumTM Architecture Software Developer's Manual for more information. If this field is zero, the platform firmware checks the Firmware_Waking_Vector field as outlined above. |
Version |
1 |
32 |
1–Version of this table |
Reserved |
31 |
33 |
This value is zero. |
FACS – Flag |
Bit Length |
Bit Offset |
Description |
S4BIOS_F |
1 |
0 |
Indicates whether the platform supports S4BIOS_REQ S4BIOS_REQ is not supported, OSPM must be able to save and restore the memory state in order to use the S4 state. |
Reserved |
31 |
1 |
The value is zero. |
Field |
Bit Length |
Bit Offset |
Description |
Pending |
1 |
0 |
Non-zero indicates that a request for ownership of the Global Lock is pending. |
Owned |
1 |
1 |
Non-zero indicates that the Global Lock is Owned. |
Reserved |
30 |
2 |
Reserved for future use. |
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'DSDT' Signature for the Differentiated System Description Table. |
Length |
4 |
4 |
Length, in bytes, of the entire DSDT (including the header). |
Revision |
1 |
8 |
2 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
The manufacture model ID. |
OEM Revision |
4 |
24 |
OEM revision of DSDT for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision number of the ASL Compiler. |
Definition Block |
n |
36 |
n bytes of AML code (see section 5.4, "Definition Block Encoding") |
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'SSDT' Signature for the Secondary System Description Table. |
Length |
4 |
4 |
Length, in bytes, of the entire SSDT (including the header). |
Revision |
1 |
8 |
2 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
The manufacture model ID. |
OEM Revision |
4 |
24 |
OEM revision of DSDT for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision number of the ASL Compiler. |
Definition Block |
n |
36 |
n bytes of AML code (see section 5.4 , "Definition Block Encoding") |
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'APIC' Signature for the Multiple APIC Description Table. |
Length |
4 |
4 |
Length, in bytes, of the entire MADT. |
Revision |
1 |
8 |
2 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
For the MADT, the table ID is the manufacturer model ID. |
OEM Revision |
4 |
24 |
OEM revision of MADT for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler. |
Local APIC Address |
4 |
36 |
The 32-bit physical address at which each processor can access its local APIC. |
Flags |
4 |
40 |
Multiple APIC flags. See Table 5-18 for a description of this field. |
APIC Structure[n] |
— |
44 |
A list of APIC structures for this implementation. This list will contain all of the I/O APIC, I/O SAPIC, Local APIC, Local SAPIC, Interrupt Source Override, Non-maskable Interrupt Source, Local APIC NMI Source, Local APIC Address Override, and Platform Interrupt Sources structures needed to support this platform. These structures are described in the following sections. |
Multiple APIC Flags |
Bit Length |
Bit Offset |
Description |
PCAT_COMPAT |
1 |
0 |
A one indicates that the system also has a PC-AT-compatible dual-8259 setup. The 8259 vectors must be disabled (that is, masked) when enabling the ACPI APIC operation. |
Reserved |
31 |
1 |
This value is zero. |
Value |
Description |
0 |
Processor Local APIC |
1 |
I/O APIC |
2 |
Interrupt Source Override |
3 |
Non-maskable Interrupt Source (NMI) |
4 |
Local APIC NMI Structure |
5 |
Local APIC Address Override Structure |
6 |
I/O SAPIC |
7 |
Local SAPIC |
8 |
Platform Interrupt Sources |
9-127 |
Reserved. OSPM skips structures of the reserved type. |
128-255 |
Reserved for OEM use |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
0 Processor Local APIC structure |
Length |
1 |
1 |
8 |
ACPI Processor ID |
1 |
2 |
The ProcessorId for which this processor is listed in the ACPI Processor declaration operator. For a definition of the Processor operator, see section 17.5.93, "Processor (Declare Processor)." |
APIC ID |
1 |
3 |
The processor's local APIC ID. |
Flags |
4 |
4 |
Local APIC flags. See Table 5-21 for a description of this field. |
LocalAPIC Flags |
Bit Length |
Bit Offset |
Description |
Enabled |
1 |
0 |
If zero, this processor is unusable, and the operating system support will not attempt to use it. |
31 |
1 |
Must be zero. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
1 I/O APIC structure |
Length |
1 |
1 |
12 |
I/O APIC ID |
1 |
2 |
The I/O APIC's ID. |
Reserved |
1 |
3 |
0 |
I/O APIC Address |
4 |
4 |
The 32-bit physical address to access this I/O APIC. Each I/O APIC resides at a unique address. |
Global System Interrupt Base |
4 |
8 |
The global system interrupt number where this I/O APIC's interrupt inputs start. The number of interrupt inputs is determined by the I/O APIC's Max Redir Entry register. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
2 Interrupt Source Override |
Length |
1 |
1 |
10 |
Bus |
1 |
2 |
0 Constant, meaning ISA |
Source |
1 |
3 |
Bus-relative interrupt source (IRQ) |
Global System Interrupt |
4 |
4 |
The Global System Interrupt that this bus-relative interrupt source will signal. |
Flags |
2 |
8 |
MPS INTI flags. See Table 5-24 for a description of this field. |
Local APIC - Flags |
Bit Length |
Bit Offset |
Description |
Polarity |
2 |
0 |
Polarity of the APIC I/O input signals: 00 Conforms to the specifications of the bus (For example, EISA is active-low for level-triggered interrupts) 01 Active high 10 Reserved 11 Active low |
Trigger Mode |
2 |
2 |
Trigger mode of the APIC I/O Input signals: 00 Conforms to specifications of the bus (For example, ISA is edge-triggered) 01 Edge-triggered 10 Reserved 11 Level-triggered |
Reserved |
12 |
4 |
Must be zero. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
3 NMI |
Length |
1 |
1 |
8 |
Flags |
2 |
2 |
Same as MPS INTI flags |
Global System Interrupt |
4 |
4 |
The Global System Interrupt that this NMI will signal. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
4 Local APIC NMI Structure |
Length |
1 |
1 |
6 |
ACPI Processor ID |
1 |
2 |
Processor ID corresponding to the ID listed in the processor object. A value of 0xFF signifies that this applies to all processors in the machine. |
Flags |
2 |
3 |
MPS INTI flags. See Table 5-24 for a description of this field. |
Local APIC LINT# |
1 |
5 |
Local APIC interrupt input LINTn to which NMI is connected. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
5 Local APIC Address Override Structure |
Length |
1 |
1 |
12 |
Reserved |
2 |
2 |
Reserved (must be set to zero) |
Local APIC Address |
8 |
4 |
Physical address of Local APIC. For ItaniumTM-based systems, this field contains the starting address of the Processor Interrupt Block. See the Intel® ItaniumTM Architecture Software Developer's Manual for more information. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
6 I/O SAPIC Structure |
Length |
1 |
1 |
16 |
I/O APIC ID |
1 |
2 |
I/O SAPIC ID |
Reserved |
1 |
3 |
Reserved (must be zero) |
Global System Interrupt Base |
4 |
4 |
The global system interrupt number where this I/O SAPIC's interrupt inputs start. The number of interrupt inputs is determined by the I/O SAPIC's Max Redir Entry register. |
I/O SAPIC Address |
8 |
8 |
The 64-bit physical address to access this I/O SAPIC. Each I/O SAPIC resides at a unique address. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
7 Processor Local SAPIC structure |
Length |
1 |
1 |
Length of the Local SAPIC Structure in bytes. |
ACPI Processor ID |
1 |
2 |
OSPM associates the Local SAPIC Structure with a processor object declared in the namespace using the Processor statement by matching the processor object's ProcessorID value with this field. For a definition of the Processor object, see section 17.5.93, "Processor (Declare Processor)." |
Local SAPIC ID |
1 |
3 |
The processor's local SAPIC ID |
Local SAPIC EID |
1 |
4 |
The processor's local SAPIC EID |
Reserved |
3 |
5 |
Reserved (must be set to zero) |
Flags |
4 |
8 |
Local SAPIC flags. See Table 5-21 for a description of this field. |
ACPI Processor UID Value |
4 |
12 |
OSPM associates the Local SAPIC Structure with a processor object declared in the namespace using the Device statement, when the _UID child object of the processor device evaluates to a numeric value, by matching the numeric value with this field. |
ACPI Processor UID String |
>=1 |
16 |
OSPM associates the Local SAPIC Structure with a processor object declared in the namespace using the Device statement, when the _UID child object of the processor device evaluates to a string, by matching the string with this field. This value is stored as a null-terminated ASCII string. |
|
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
8 Platform Interrupt Source structure |
Length |
1 |
1 |
16 |
Flags |
2 |
2 |
MPS INTI flags. See Table 5-24 for a description of this field. |
Interrupt Type |
1 |
4 |
1 PMI 2 INIT 3 Corrected Platform Error Interrupt All other values are reserved. |
Processor ID |
1 |
5 |
Processor ID of destination. |
Processor EID |
1 |
6 |
Processor EID of destination. |
I/O SAPIC Vector |
1 |
7 |
Value that OSPM must use to program the vector field of the I/O SAPIC redirection table entry for entries with the PMI interrupt type. |
Global System Interrupt |
4 |
8 |
The Global System Interrupt that this platform interrupt will signal. |
Platform Interrupt Source Flags |
4 |
12 |
Platform Interrupt Source Flags. See Table 5-31 for a description of this field |
|
Platform Interrupt Source Flags |
Bit Length |
Bit Offset |
Description |
CPEI Processor Override |
1 |
0 |
When set, indicates that retrieval of error information is allowed from any processor and OSPM is to use the information provided by the processor ID, EID fields of the Platform Interrupt Source Structure (Table 5-30) as a target processor hint. |
Reserved |
31 |
1 |
Must be zero. |
|
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'SBST' Signature for the Smart Battery Description Table. |
Length |
4 |
4 |
Length, in bytes, of the entire SBST |
Revision |
1 |
8 |
1 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
For the SBST, the table ID is the manufacturer model ID. |
OEM Revision |
4 |
24 |
OEM revision of SBST for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler. |
Warning Energy Level |
4 |
36 |
OEM suggested energy level in milliWatt-hours (mWh) at which OSPM warns the user. |
Low Energy Level |
4 |
40 |
OEM suggested platform energy level in mWh at which OSPM will transition the system to a sleeping state. |
Critical Energy Level |
4 |
44 |
OEM suggested platform energy level in mWh at which OSPM performs an emergency shutdown. |
|
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'ECDT' Signature for the Embedded Controller Table. |
Length |
4 |
4 |
Length, in bytes, of the entire Embedded Controller Table |
Revision |
1 |
8 |
1 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID |
OEM Table ID |
8 |
16 |
For the Embedded Controller Table, the table ID is the manufacturer model ID. |
OEM Revision |
4 |
24 |
OEM revision of Embedded Controller Table for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For tables containing Definition Blocks, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For tables containing Definition Blocks, this is the revision for the ASL Compiler. |
EC_CONTROL |
12 |
36 |
Contains the processor relative address, represented in
Generic Address Structure format, of the Embedded Controller Command/Status
register. |
EC_DATA |
12 |
48 |
Contains the processor-relative address, represented in
Generic Address Structure format, of the Embedded Controller Data register. |
UID |
4 |
60 |
Unique ID–Same as the value returned by the _UID under the device in the namespace that represents this embedded controller. |
GPE_BIT |
1 |
64 |
The bit assignment of the SCI interrupt within the GPEx_STS register of a GPE block described in the FADT that the embedded controller triggers. |
EC_ID |
Variable |
65 |
ASCII, null terminated, string that contains a fully qualified reference to the name space object that is this embedded controller device (for example, "\\_SB.PCI0.ISA.EC"). Quotes are omitted in the data field. |
|
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'SRAT'. Signature for the System Resource Affinity Table. |
Length |
4 |
4 |
Length, in bytes, of the entire SRAT. The length implies the number of Entry fields at the end of the table |
Revision |
1 |
8 |
2 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID. |
OEM Table ID |
8 |
16 |
For the System Resource Affinity Table, the table ID is the manufacturer model ID. |
OEM Revision |
4 |
24 |
OEM revision of System Resource Affinity Table for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. |
Reserved |
4 |
36 |
Reserved to be 1 for backward compatibility |
Reserved |
8 |
40 |
Reserved |
Static Resource Allocation Structure[n] |
--- |
48 |
A list of static resource allocation structures for the platform. See section 5.2.15.1,"Processor Local APIC/SAPIC Affinity Structure" and section 5.2.15.2 Memory Affinity Structure". |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
0 Processor Local APIC/SAPIC Affinity Structure |
Length |
1 |
1 |
16 |
Proximity Domain [7:0] |
1 |
2 |
Bit[7:0] of the proximity domain to which the processor belongs. |
APIC ID |
1 |
3 |
The processor local APIC ID. |
Flags |
4 |
4 |
Flags – Processor Local APIC/SAPIC Affinity Structure. See Table 5-36 for a description of this field. |
Local SAPIC EID |
1 |
8 |
The processor local SAPIC EID. |
Proximity Domain [31:8] |
3 |
9 |
Bit[31:8] of the proximity domain to which the processor belongs. |
Reserved |
4 |
12 |
Reserved |
Field |
Bit Length |
Bit Offset |
Description |
Enabled |
1 |
0 |
If clear, the OSPM ignores the contents of the Processor Local APIC/SAPIC Affinity Structure. This allows system firmware to populate the SRAT with a static number of structures but only enable them as necessary. |
Reserved |
31 |
1 |
Must be zero. |
Field |
Byte Length |
Byte Offset |
Description |
Type |
1 |
0 |
1 Memory Affinity Structure |
Length |
1 |
1 |
40 |
Proximity Domain |
4 |
2 |
Integer that represents the proximity domain to which the processor belongs |
Reserved |
2 |
6 |
Reserved |
Base Address Low |
4 |
8 |
Low 32 Bits of the Base Address of the memory range |
Base Address High |
4 |
12 |
High 32 Bits of the Base Address of the memory range |
Length Low |
4 |
16 |
Low 32 Bits of the length of the memory range. |
Length High |
4 |
20 |
High 32 Bits of the length of the memory range. |
Reserved |
4 |
24 |
Reserved. |
Flags |
4 |
28 |
Flags – Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged. Details in See Table 5-38. |
Reserved |
8 |
32 |
Reserved. |
Field |
Bit Length |
Bit Offset |
Description |
Enabled |
1 |
0 |
If clear, the OSPM ignores the contents of the Memory Affinity Structure. This allows system firmware to populate the SRAT with a static number of structures but only enable then as necessary. |
Hot Pluggable[5] |
1 |
1 |
The information conveyed by this bit depends on the value of the Enabled bit. If the Enabled bit is set and the Hot Pluggable bit is also set. The system hardware supports hot-add and hot-remove of this memory region If the Enabled bit is set and the Hot Pluggable bit is clear, the system hardware does not support hot-add or hot-remove of this memory region. If the Enabled bit is clear, the OSPM will ignore the contents of the Memory Affinity Structure |
Reserved |
29 |
3 |
Must be zero. |
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'SLIT'. Signature for the System Locality Distance Information Table. |
Length |
4 |
4 |
Length, in bytes, of the entire System Locality Distance Information Table. |
Revision |
1 |
8 |
1 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID. |
OEM Table ID |
8 |
16 |
For the System Locality Information Table, the table ID is the manufacturer model ID. |
OEM Revision |
4 |
24 |
OEM revision of System Locality Information Table for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the revision for the ASL Compiler. |
Number of System Localities |
8 |
36 |
Indicates the number of System Localities in the system. |
Entry[0][0] |
1 |
44 |
Matrix entry (0,0), contains a value of 10. |
… |
|
|
|
Entry[0][Number of System Localities-1] |
1 |
|
Matrix entry (0, Number of System Localities-1) |
Entry[1][0] |
1 |
|
Matrix entry (1,0) |
…… |
|
|
…… |
Entry[Number of System Localities-1][Number of System Localities-1] |
1 |
|
Matrix entry (Number of System Localities-1, Number of System Localities-1), contains a value of 10 |
|
|
|
Name |
Description |
\_GPE |
General events in GPE register block. |
\_PR |
ACPI 1.0 Processor Namespace. ACPI 1.0 requires all Processor objects to be defined under this namespace. ACPI allows Processor object definitions under the \_SB namespace. Platforms may maintain the \_PR namespace for compatibility with ACPI 1.0 operating systems ACPI-compatible namespace may define Processor objects in either the \_SB or \_PR scope but not both. For more information about defining Processor objects, see section 8, "Processor Power and Performance State Configuration and Control." |
\_SB |
All Device/Bus Objects are defined under this namespace. |
\_SI |
System indicator objects are defined under this namespace more information about defining system indicators, see section 9.1, \_S1 System Indicators." |
\_TZ |
ACPI 1.0 Thermal Zone namespace. ACPI 1.0 requires all Thermal Zone objects to be defined under this namespace. Thermal Zone object definitions may now be defined under the \_SB namespace. ACPI-compatible systems may maintain the \_TZ namespace for compatibility with ACPI 1.0 operating systems. An ACPI-compatible namespace may define Thermal Zone objects in either the \_SB or \_TZ scope but not both. For more information about defining Thermal Zone objects, see section 11, "Thermal Management." |
|
|
|
|
|
Component |
Description |
OSPM |
Receives all SCI interrupts raised (receives all SCI events). Either handles the event or masks the event off and later invokes an OEM-provided control method to handle the event. Events handled directly by OSPM are fixed ACPI events; interrupts handled by control methods are general-purpose events. |
FADT |
Specifies the base address for the following fixed register blocks on an ACPI-compatible platform: PM1x_STS and PM1x_EN fixed registers and the GPEx_STS and GPEx_EN fixed registers. |
PM1x_STS and PM1x_EN fixed registers |
PM1x_STS bits raise fixed ACPI events. While a PM1x_STS bit is set, if the matching PM1x_EN bit is set, the ACPI SCI event is raised. |
GPEx_STS and GPEx_EN fixed registers |
GPEx_STS bits that raise general-purpose events. For every event bit implemented in GPEx_STS, there must be a comparable bit in GPEx_EN. Up to 256 GPEx_STS bits and matching GPEx_EN bits can be implemented. While a GPEx_STS bit is set, if the matching GPEx_EN bit is set, then the general-purpose SCI event is raised. |
SCI interrupt |
A level-sensitive, shareable interrupt mapped to a declared interrupt vector. The SCI interrupt vector can be shared with other low-priority interrupts that have a low frequency of occurrence. |
ACPI AML code general-purpose event model |
A model that allows OEM AML code to use GPEx_STS events. This includes using GPEx_STS events as "wake" sources as well as other general service events defined by the OEM ("button pressed," "thermal event," "device present/not present changed," and so on). |
ACPI device-specific model events |
Devices in the ACPI namespace that have ACPI-specific device IDs can provide additional event model functionality. In particular, the ACPI embedded controller device provides a generic event model. |
ACPI Embedded Controller event model |
A model that allows OEM AML code to use the response from the Embedded Controller Query command to provide general-service event defined by the OEM. |
Event |
Comment |
Power management timer carry bit set. |
For more information, see the description of the TMR_STS and TMR_EN bits of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping," as well as the TMR_VAL register in the PM_TMR_BLK in section 4.7.3.3, "Power Management Timer." |
Power button signal |
A power button can be supplied in two ways. One way is to simply use the fixed status bit, and the other uses the declaration of an ACPI power device and AML code to determine the event. For more information about the alternate-device based power button, see section 4.7.2.2.1.2, Control Method Power Button." Notice that during the S0 state, both the power and sleep buttons merely notify OSPM that they were pressed. If the system does not have a sleep button, it is recommended that OSPM use the power button to initiate sleep operations as requested by the user. |
Sleep button signal |
A sleep button can be supplied in one of two ways. One way is to simply use the fixed status button. The other way requires the declaration of an ACPI sleep button device and AML code to determine the event. |
RTC alarm |
ACPI-defines an RTC wake alarm function with a minimum of one-month granularity. The ACPI status bit for the device is optional. If the ACPI status bit is not present, the RTC status can be used to determine when an alarm has occurred. For more information, see the description of the RTC_STS and RTC_EN bits of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping." |
Wake status |
The wake status bit is used to determine when the sleeping state has been completed. For more information, see the description of the WAK_STS and WAK_EN bits of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping." |
|
Event |
Comment |
System bus master request |
The bus-master status bit provides feedback from the hardware as to when a bus master cycle has occurred. This is necessary for supporting the processor C3 power savings state. For more information, see the description of the BM_STS bit of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping." |
Global release status |
This status is raised as a result of the Global Lock protocol, and is handled by OSPM as part of Global Lock synchronization. For more information, see the description of the GBL_STS bit of the PM1x fixed register block in section 4.7.3.1, "PM1 Event Grouping." For more information on Global Lock, see section 5.2.10.1, "Global Lock." |
|
Value |
Description |
0 |
Bus Check. This notification is performed on a device object to indicate to OSPM that it needs to perform the Plug and Play re-enumeration operation on the device tree starting from the point where it has been notified. OSPM will only perform this operation at boot, and when notified. It is the responsibility of the ACPI AML code to notify OSPM at any other times that this operation is required. The more accurately and closer to the actual device tree change the notification can be done, the more efficient the operating system's response will be; however, it can also be an issue when a device change cannot be confirmed. For example, if the hardware cannot notice a device change for a particular location during a system sleeping state, it issues a Bus Check notification on wake to inform OSPM that it needs to check the configuration for a device change. |
1 |
Device Check. Used to notify OSPM that the device either appeared or disappeared. If the device has appeared, OSPM will re-enumerate from the parent. If the device has disappeared, OSPM will invalidate the state of the device. OSPM may optimize out re-enumeration. If _DCK is present, then Notify(object,1) is assumed to indicate an undock request. |
2 |
Device Wake. Used to notify OSPM that the device has signaled its wake event, and that OSPM needs to notify OSPM native device driver for the device. This is only used for devices that support _PRW. |
3 |
Eject Request. Used to notify OSPM that the device should be ejected, and that OSPM needs to perform the Plug and Play ejection operation. OSPM will run the _EJx method. |
4 |
Device Check Light. Used to notify OSPM that the device either appeared or disappeared. If the device has appeared, OSPM will re-enumerate from the device itself, not the parent. If the device has disappeared, OSPM will invalidate the state of the device. |
5 |
Frequency Mismatch. Used to notify OSPM that a device inserted into a slot cannot be attached to the bus because the device cannot be operated at the current frequency of the bus. For example, this would be used if a user tried to hot-plug a 33 MHz PCI device into a slot that was on a bus running at greater than 33 MHz. |
6 |
Bus Mode Mismatch. Used to notify OSPM that a device has been inserted into a slot or bay that cannot support the device in its current mode of operation. For example, this would be used if a user tried to hot-plug a PCI device into a slot that was on a bus running in PCI-X mode. |
7 |
Power Fault. Used to notify OSPM that a device cannot be moved out of the D3 state because of a power fault. |
8 |
Capabilities Check. This notification is performed on a device object to indicate to OSPM that it needs to re-evaluate the _OSC control method associated with the device. |
9 |
Device _PLD Check. Used to notify OSPM to reevaluate the _PLD object, as the Device's connection point has changed. |
0xA |
Reserved. |
0xC-0x7F |
Reserved. |
Hex value |
Description |
0x80 |
Battery Status Changed. Used to notify OSPM that the Control Method Battery device status has changed. |
0x81 |
Battery Information Changed. Used to notify OSPM that the Control Method Battery device information has changed. This only occurs when a battery is replaced. |
0x82 |
Battery Maintenance Data Status Flags Check. Used to notify OSPM that the Control Method Battery device battery maintenance data status flags should be checked. |
0x83-0xBF |
Reserved. |
Hex value |
Description |
0x80 |
Power Source Status Changed. Used to notify OSPM that the power source status has changed. |
0x81-0xBF |
Reserved. |
Hex value |
Description |
0x80 |
Thermal Zone Status Changed. Used to notify OSPM that the thermal zone temperature has changed. |
0x81 |
Thermal Zone Trip points Changed. Used to notify OSPM that the thermal zone trip points have changed. |
0x82 |
Device Lists Changed. Used to notify OSPM that the thermal zone device lists (_ALx, _PSL, _TZD) have changed. |
0x83 |
Thermal Relationship Table Changed. Used to notify OSPM that values in the thermal relationship table have changed. |
0x84-0xBF |
Reserved. |
Hex value |
Description |
0x80 |
S0 Power Button Pressed. Used to notify OSPM that the power button has been pressed while the system is in the S0 state. Notice that when the button is pressed while the system is in the S1-S4 state, a Device Wake notification must be issued instead. |
0x81-0xBF |
Reserved. |
Hex value |
Description |
0x80 |
S0 Sleep Button Pressed. Used to notify OSPM that the sleep button has been pressed while the system is in the S0 state. Notice that when the button is pressed while the system is in the S1-S4 state, a Device Wake notification must be issued instead. |
0x81-0xBF |
Reserved. |
|
Hex value |
Description |
0x80 |
Lid Status Changed. Used to notify OSPM that the control method lid device status has changed. |
0x81-0xBF |
Reserved. |
Hex value |
Description |
0x80 |
Performance Present Capabilities Changed. Used to notify OSPM that the number of supported processor performance states has changed. This notification causes OSPM to re-evaluate the _PPC object. See section 8, "Processor Power and Performance State Configuration and Control," for more information. |
0x81 |
C States Changed. Used to notify OSPM that the number or type of supported processor C States has changed. This notification causes OSPM to re-evaluate the _CST object. See section 8, "Processor Power and Performance State Configuration and Control," for more information. |
0x82 |
Throttling Present Capabilities Changed. Used to notify OSPM that the number of supported processor throttling states has changed. This notification causes OSPM to re-evaluate the _TPC object. See section 8, "Processor Power and Performance State Configuration and Control," for more information. |
0x83-0xBF |
Reserved. |
Hex value |
Description |
0x80 |
User Presence Changed. Used to notify OSPM that a meaningful change in user presence has occurred, causing OSPM to re-evaluate the _UPD object. |
0x81-0xBF |
Reserved. |
Hex value |
Description |
0x80 |
ALS Illuminance Changed. Used to notify OSPM that a meaningful change in ambient light illuminance has occurred, causing OSPM to re-evaluate the _ALI object. |
0x81 |
ALS Color Temperature Changed. Used to notify OSPM that a meaningful change in ambient light color temperature or chromacity has occurred, causing OSPM to re-evaluate the _ALT and/or _ALC objects. |
0x82 |
ALS Response Changed. Used to notify OSPM that the set of points used to convey the ambient light response has changed, causing OSPM to re-evaluate the _ALR object. |
0x83-0xBF |
Reserved. |
Plug and Play ID |
Description |
PNP0C08 |
ACPI. Not declared in ACPI as a device. This ID is used by OSPM for the hardware resources consumed by the ACPI fixed register spaces, and the operation regions used by AML code. It represents the core ACPI hardware itself. |
PNP0A05 |
Generic Container Device. A device whose settings are totally controlled by its ACPI resource information, and otherwise needs no device or bus-specific driver support. This was originally known as Generic ISA Bus Device. This ID should only be used for containers that do not produce resources for consumption by child devices. Any system resources claimed by a PNP0A05 device's _CRS object must be consumed by the container itself. |
PNP0A06 |
Generic Container Device. This device behaves exactly the same as the PNP0A05 device. This was originally known as Extended I/O Bus. This ID should only be used for containers that do not produce resources for consumption by child devices. Any system resources claimed by a PNP0A06 device's _CRS object must be consumed by the container itself. |
PNP0C09 |
Embedded Controller Device. A host embedded controller controlled through an ACPI-aware driver. |
PNP0C0A |
Control Method Battery. A device that solely implements the ACPI Control Method Battery functions. A device that has some other primary function would use its normal device ID. This ID is used when the devices primary function is that of a battery. |
PNP0C0B |
Fan. A device that causes cooling when "on" (D0 device state). |
|
Plug and Play ID |
Description |
PNP0C0C |
Power Button Device. A device controlled through an ACPI-aware driver that provides power button functionality. This device is only needed if the power button is not supported using the fixed register space. |
PNP0C0D |
Lid Device. A device controlled through an ACPI-aware driver that provides lid status functionality. This device is only needed if the lid state is not supported using the fixed register space. |
PNP0C0E |
Sleep Button Device. A device controlled through an ACPI-aware driver that provides power button functionality. This device is optional. |
PNP0C0F |
PCI Interrupt Link Device. A device that allocates an interrupt connected to a PCI interrupt pin. See section 6., "Configuration," for more details. |
PNP0C80 |
Memory Device. This device is a memory subsystem. |
ACPI0001 |
SMBus 1.0 Host Controller. An SMBus host controller (SMB-HC) compatible with the embedded controller-based SMB-HC interface (as specified in section 12.9, "SMBus Host Controller Interface via Embedded Controller") and implementing the SMBus 1.0 Specification. |
ACPI0002 |
Smart Battery Subsystem. The Smart battery Subsystem specified in section 10, "Power Source Devices." |
ACPI0003 |
AC Device. The AC adapter specified in section 10, "Power Source Devices." |
ACPI0004 |
Module Device. This device is a container object that acts as a bus node in a namespace. A Module Device without any of the _CRS, _PRS and _SRS methods behaves the same way as the Generic Container Devices (PNP0A05 or PNP0A06). If the Module Device contains a _CRS method, only these resources described in the _CRS are available for consumption by its child devices. Also, the Module Device can support _PRS and _SRS methods if _CRS is supported. |
ACPI0005 |
SMBus 2.0 Host Controller. An SMBus host controller (SMB-HC compatible with the embedded controller-based SMB-HC interface (as specified in section 12.9, "SMBus Host Controller Interface via Embedded Controller") and implementing the SMBus 2.0 Specification. |
ACPI0006 |
GPE Block Device. This device allows a system designer to describe GPE blocks beyond the two that are described in the FADT. |
ACPI0007 |
Processor Device. This device provides an alternative to declaring processors using the Processor ASL statement. See section 8.4, "Declaring Processors", for more details. |
ACPI0008 |
Ambient Light Sensor Device. This device is an ambient light sensor. See section 9.2, "Control Method Ambient Light Sensor Device". |
ACPI0009 |
I/OxAPIC Device. This device is an I/O unit that complies with both the APIC and SAPIC interrupt models. |
ACPI000A |
I/O APIC Device. This device is an I/O unit that complies with the APIC interrupt model. |
ACPI000B |
I/O SAPIC Device. This device is an I/O unit that complies with the SAPIC interrupt model. |
Table 5-54 Defined Generic Object and Control Methods | ||||
Object |
Description |
Reference | ||
_ACx |
Thermal Zone object that returns active cooling policy threshold values in tenths of degrees Kelvin. |
11.3.1 | ||
_ADR |
Device object that evaluates to a device's address on its parent bus. For the display output device, this object returns a unique ID. (B.5.1, "_ADR - Return the Unique ID for this Device.") |
6.1.1 | ||
_ALC |
Object evaluates to current Ambient Light Color Chromacity |
9.2.4 |
| |
_ALI |
The current ambient light brightness in lux (lumen per square meter). |
9.2.2 | ||
_ALN |
Resource data type reserved field name |
17.1.8 | ||
_ALP |
Ambient light sensor polling frequency in tenths of seconds. |
9.2.6 | ||
_ALR |
Returns a set of ambient light brightness to display brightness mappings that can be used by an OS to calibrate its ambient light policy. |
9.2.5 | ||
_ALT |
The current ambient light color temperature in degrees Kelvin. |
9.2.3 | ||
_ALx |
Thermal zone object containing a list of cooling device objects. |
11.3.2 | ||
_ASI |
Resource data type reserved field name |
17.1.8 | ||
_BAS |
Resource data type reserved field name |
17.1.8 | ||
_BBN |
PCI bus number setup by the BIOS |
6.5.5 | ||
_BCL |
Returns a buffer of bytes indicating list of brightness control levels supported. |
B.6.2 | ||
_BCM |
Sets the brightness level of the built-in display output device. |
B.6.3 | ||
_BDN |
Correlates a docking station between ACPI and legacy interfaces. |
6.5.3 | ||
_BFS |
Control method executed immediately following a wake event. |
7.3.1 | ||
_BIF |
Control Method Battery information object |
10.2.2.1 | ||
_BLT |
Object that conveys user's battery level threshold preferences to platform. |
9.1.3 | ||
_BM |
Resource data type reserved field name |
17.1.8 | ||
_BMC |
Powers source object used to initiate battery calibration cycles or to control the charger and whether or not a battery is powering the system. |
10.2.2.7 | ||
_BMD |
Power source object that returns information about the battery's capabilities and current state in relation to battery calibration and charger control features. |
10.2.2.6 | ||
_BQC |
Object that returns current display brightness level. |
B.6.4 | ||
_BST |
Control Method Battery status object |
10.2.2.3 | ||
_BTM |
Returns estimated runtime at the present average rate of drain, or the runtime at a specified rate. |
10.2.2.5 | ||
_BTP |
Sets Control Method Battery trip point |
10.2.2.4 | ||
_CBA |
Provides the Configuration Base Address for a PCI Express host bridge |
PCI Firmware Specification, Revision 3.0 http://pcisig.com | ||
_CID |
Device identification object that evaluates to a device's Plug and Play Compatible ID list. |
6.1.2 | ||
_CRS |
Device configuration object that specifies a device's current resource settings, or a control method that generates such an object. |
6.2.1 | ||
_CRT |
Thermal zone object that returns critical trip point in tenths of degrees Kelvin. |
11.3.3 | ||
_CSD |
Object that conveys C-State dependencies |
8.4.2.2 | ||
_CST |
Processor power state declaration object |
8.4.2.1 | ||
_DCK |
Indicates that the device is a docking station. |
6.5.2 | ||
_DCS |
Returns the status of the display output device. |
B.6.6 | ||
_DDC |
Returns the EDID for the display output device |
B.6.5 | ||
_DDN |
Object that associates a logical software name (for example, COM1) with a device. |
6.1.3 | ||
_DEC |
Resource data type reserved field name |
17.1.8 | ||
_DGS |
Control method used to query the state of the output device. |
B.6.7 | ||
_DIS |
Device configuration control method that disables a device. |
6.2.2 | ||
_DMA |
Object that specifies a device's current resources for DMA transactions. |
6.2.3 | ||
_DOD |
Control method used to enumerate devices attached to the display adapter. |
B.4.2 | ||
_DOS |
Control method used to enable/disable display output switching. |
B.4.1 | ||
_DSM |
Generic device control method object |
9.15.1 | ||
_DSS |
Control method used to set display device state. |
B.6.8 | ||
_DSW |
Set up a device for device-only wake |
7.2.1 | ||
_Exx |
Control method executed as a result of a general-purpose event. |
5.6.2.2, | ||
_EC |
Control Method used to define the offset address and Query value of an SMB-HC defined within an embedded controller device. |
12.12 | ||
_EDL |
Device removal object that returns a packaged list of devices that are dependent on a device. |
6.3.1 | ||
_EJx |
Device insertion/removal control method that ejects a device. |
6.3.3 | ||
_EJD |
Device removal object that evaluates to the name of a device object upon which a device is dependent. Whenever the named device is ejected, the dependent device must receive an ejection notification. |
6.3.2 | ||
_FDE |
Object that indicates the presence or absence of floppy disks. |
9.10.1 | ||
_FDI |
Object that returns floppy drive information. |
9.10.2 | ||
_FDM |
Control method that changes the mode of floppy drives. |
9.10.3 | ||
_FIX |
Object used to provide correlation between the fixed hardware register blocks defined in the FADT and the devices that implement these fixed hardware registers. |
6.2.4 | ||
_GL |
OS-defined Global Lock mutex object |
5.7.1 | ||
_GLK |
Indicates the need to acquire the Global Lock, must be acquired when accessing the device. |
6.5.7 | ||
_GPD |
Control method that returns which VGA device will be posted at boot |
B.4.4 | ||
_GPE |
1. General-Purpose Events root name space 2. Object that returns the SCI interrupt within the GPx_STS register that is connected to the EC. |
5.3.1 12.11 | ||
_GRA |
Resource data type reserved field name. |
17.1.8 | ||
_GTF |
IDE device control method to get the Advanced Technology Attachment (ATA) task file needed to re-initialize the drive to boot up defaults. |
9.9.1.1 | ||
_GTM |
IDE device control method to get the IDE controller timing information. |
9.9.2.1.1 | ||
_GSB |
Object that provides the Global System Interrupt Base for a hot-plugged I/O APIC device. |
6.2.5 | ||
_GTS |
Control method executed just prior to setting the sleep enable (SLP_EN) bit. |
7.3.3 | ||
_HE |
Resource data type reserved field name |
17.1.8 | ||
_HID |
Device identification object that evaluates to a device's Plug and Play Hardware ID. |
6.1.4 | ||
_HOT |
Object returns critical temperature when OSPM enters S4 |
11.3.4 | ||
_HPP |
An object that specifies the Cache-line size, Latency timer, SERR enable, and PERR enable values to be used when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot. |
6.2.6 | ||
_HPX |
Object that provides device parameters when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot. Supersedes _HPP. |
6.2.7 | ||
_IFT |
IPMI Interface Type |
Intelligent Platform Management Interface Specification href="http://www.intel.com/design/servers/ipmi/index.htm">http://www.intel.com/design/servers/ipmi/index.htm | ||
_INI |
Device initialization method that performs device specific initialization. |
6.5.1 | ||
_INT |
Resource data type reserved field name |
17.1.8 | ||
_IRC |
Power management object that signifies the device has a significant inrush current draw. |
7.2.12 | ||
_Lxx |
Control method executed as a result of a general-purpose event. |
5.6.2.2, | ||
_LCK |
Device insertion/removal control method that locks or unlocks a device. |
6.3.4 | ||
_LEN |
Resource data type reserved field name |
17.1.8 | ||
_LID |
Object that returns the status of the Lid on a mobile system. |
9.4.1 | ||
_LL |
Resource data type reserved field name |
17.1.8 | ||
_MAF |
Resource data type reserved field name |
17.1.8 | ||
_MAT |
Object evaluates to a buffer of MADT APIC Structure entries. |
6.2.8 | ||
_MAX |
Resource data type reserved field name |
17.1.8 | ||
_MEM |
Resource data type reserved field name |
17.1.8 | ||
_MIF |
Resource data type reserved field name |
17.1.8 | ||
_MIN |
Resource data type reserved field name |
17.1.8 | ||
_MSG |
System indicator control that indicates messages are waiting. |
9.1.2 | ||
_MLS |
Object that provides a human readable description of a device in multiple languages. |
6.1.5 | ||
_OFF |
Power resource object that sets the resource off. |
7.1.2 | ||
_ON |
Power resource object that sets the resource on. |
7.1.3 | ||
_OS |
Object that evaluates to a string that identifies the operating system. |
5.7.2 | ||
_OSC |
Convey specific software support / capabilities to the platform allowing the platform to configure itself appropriately. |
6.2.9 | ||
_OST |
OSPM Status Indication |
6.3.5 | ||
_PCL |
Power source object that contains a list of devices powered by a power source. |
10.3.2 | ||
_PCT |
Processor performance control object |
8.4.4.1 | ||
_PDC |
Processor Driver Capabilities |
8.4.1 | ||
_PIC |
Control method that conveys interrupt model in use to the system firmware. |
5.8.1 | ||
_PLD |
Object that provides physical location description information. |
6.1.6 | ||
_PPC |
Control method used to determine number of performance states currently supported by the platform. |
8.4.4.3 | ||
_PPE |
Object provides polling interval to retrieve Corrected Platform Error information |
DIG64 Corrected Platform Error Polling Specification. http://www.dig64.org/specifications | ||
_PR |
ACPI 1.0 Processor Namespace |
5.3.1 | ||
_PR0 |
Power management object that evaluates to the device's power requirements in the D0 device state (device fully on). |
7.2.7 | ||
_PR1 |
Power management object that evaluates to the device's power requirements in the D1 device state. Only devices that can achieve the defined D1 device state according to its given device class would supply this level. |
7.2.8 | ||
_PR2 |
Power management object that evaluates to the device's power requirements in the D2 device state. Only devices that can achieve the defined D2 device state according to its given device class would supply this level. |
7.2.9 | ||
_PRS |
Device configuration object that specifies a device's possible resource settings, or a control method that generates such an object. |
6.2.10 | ||
_PRT |
An object that specifies the PCI interrupt Routing Table. |
6.2.11 | ||
_PRW |
Power management object that evaluates to the device's power requirements in order to wake the system from a system sleeping state. |
7.2.10 | ||
_PS0 |
Power management control method that puts the device in the D0 device state. (device fully on). |
7.2.2 | ||
_PS1 |
Power management control method that puts the device in the D1 device state. |
7.2.3 | ||
_PS2 |
Power management control method that puts the device in the D2 device state. |
7.2.4 | ||
_PS3 |
Power management control method that puts the device in the D3 device state (device off). |
7.2.5 | ||
_PSC |
Power management object that evaluates to the device's current power state. |
7.2.6 | ||
_PSD |
Object that conveys P-State dependencies |
8.4.4.5 | ||
_PSL |
Thermal zone object that returns list of passive cooling device objects. |
11.3.5 | ||
_PSR |
Power source object that returns present power source device. |
10.3.1 | ||
_PSS |
Object indicates the number of supported processor performance states. |
8.4.4.2 | ||
_PSV |
Thermal zone object that returns Passive trip point in tenths of degrees Kelvin. |
11.3.6 | ||
_PSW |
Power management control method that enables or disables the device's wake function. |
7.2.11 | ||
_PTC |
Object used to define a processor throttling control register. |
8.4.3.1 | ||
_PTS |
Control method used to notify the platform of impending sleep transition. |
7.3.2 | ||
_PXM |
Object used to describe proximity domains within a machine. |
6.2.12 | ||
_Qxx |
Embedded Controller Query and SMBus Alarm control method |
5.6.2.2.3 | ||
_RBO |
Resource data type reserved field name |
17.1.8 | ||
_RBW |
Resource data type reserved field name |
17.1.8 | ||
_REG |
Notifies AML code of a change in the availability of an operation region. |
6.5.4 | ||
_REV |
Revision of the ACPI specification that OSPM implements. |
5.7.4 | ||
_RMV |
Device insertion/removal object that indicates that the given device is removable. |
6.3.6 | ||
_RNG |
Resource data type reserved field name |
17.1.8 | ||
_ROM |
Control method used to get a copy of the display devices' ROM data. |
B.4.3 | ||
_RT |
Resource Type field of the QWordSpace, DWordSpace or WordSpace address descriptors |
17.1.8 | ||
_RTV |
Object indicates whether temperature values are relative or absolute. |
11.3.7 | ||
_RW |
Resource data type reserved field name |
17.1.8 | ||
_S0 |
Power management package that defines system \_S0 state mode. |
7.3.4.1 | ||
_S1 |
Power management package that defines system \_S1 state mode. |
7.3.4.2 | ||
_S2 |
Power management package that defines system \_S2 state mode. |
7.3.4.3 | ||
_S3 |
Power management package that defines system \_S3 state mode. |
7.3.4.4 | ||
_S4 |
Power management package that defines system \_S4 state mode. |
7.3.4.5 | ||
_S5 |
Power management package that defines system \_S5 state mode. |
7.3.4.6 | ||
_S1D |
Highest D-state supported by the device in the S1 state. |
7.2.13 | ||
_S2D |
Highest D-state supported by the device in the S2 state. |
7.2.14 | ||
_S3D |
Highest D-state supported by the device in the S3 state. |
7.2.15 | ||
_S4D |
Highest D-state supported by the device in the S4 state. |
7.2.16 | ||
_S0W |
Lowest D-state supported by the device in the S0 state which can wake the device |
7.2.17 | ||
_S1W |
Lowest D-state supported by the device in the S1 state which can wake the system |
7.2.18 | ||
_S2W |
Lowest D-state supported by the device in the S2 state which can wake the system |
7.2.19 | ||
_S3W |
Lowest D-state supported by the device in the S3 state which can wake the system |
7.2.20 | ||
_S4W |
Lowest D-state supported by the device in the S4 state which can wake the system |
7.2.21 | ||
_SB |
System bus scope |
5.3.1 | ||
_SBS |
Smart Battery object that returns Smart Battery configuration. |
10.1.2 | ||
_SCP |
Thermal zone object that sets user cooling policy (Active or Passive). |
11.3.8 | ||
_SDD |
Control method that informs the platform of the type of device attached to a SATA port. |
9.9.3.3.1 | ||
_SEG |
Evaluates to the PCI Segment Group number. |
6.5.6 | ||
_SHR |
Resource data type reserved field name |
17.1.8 | ||
_SI |
System indicators scope |
9.1 | ||
_SIZ |
Resource data type reserved field name |
17.1.8 | ||
_SLI |
Object that provides updated distance information for a system locality. |
6.2.13 | ||
_SPD |
Control method used to update which video device will be posted at boot. |
B.4.5 | ||
_SRS |
Device configuration control method that sets a device's settings. |
6.2.14 | ||
_SRV |
IPMI Spec Revision |
Intelligent Platform Management Interface Specification href="http://www.intel.com/design/servers/ipmi/index.htm">http://www.intel.com/design/servers/ipmi/index.htm | ||
_SST |
System indicator control method that indicates the system status. |
9.1.1 | ||
_STA |
1. Device insertion/removal control method that returns a device's status. 2. Power resource object that evaluates to the current on or off state of the Power Resource. |
6.3.7 7.1.4 | ||
_STM |
IDE device control method used to set the IDE controller transfer timings. |
9.9.2.1.2 | ||
_STR |
Object evaluates to a Unicode string to describe a device. |
6.1.7 | ||
_SUN |
Object that evaluates to the slot unique ID number for a slot. |
6.1.8 | ||
_SWS |
Object that returns the source event that caused the system to wake. |
7.3.5 | ||
_T_x |
Reserved for use by the ASL compiler. |
17.2.1.1 | ||
_TC1 |
Thermal zone object that contains thermal constant for Passive cooling. |
11.3.9 | ||
_TC2 |
Thermal zone object that contains thermal constant for Passive cooling. |
11.3.10 | ||
_TMP |
Thermal zone object that returns current temperature in tenths of degrees Kelvin. |
11.3.11 | ||
_TPC |
Object evaluates to the current number of supported throttling states. |
8.4.3.3 | ||
_TPT |
Control method invoked when a devices' embedded temperature sensor crosses a temperature trip point. |
11.3.12 | ||
_TRA |
Resource data type reserved field name |
17.1.8 | ||
_TRS |
Resource data type reserved field name |
17.1.8 | ||
_TRT |
Object provides thermal relationship information between platform devices. |
11.3.13 | ||
_TSD |
Object that conveys Throttling State dependencies |
8.4.3.4 | ||
_TSF |
Type-Specific Flags fields in a Word, DWord or QWord address space descriptor |
17.1.8 | ||
_TSP |
Thermal zone object that contains thermal sampling period for Passive cooling. |
11.3.14 | ||
_TST |
Object returns minimum temperature separation for device's programmable temperature trip points. |
11.3.15 | ||
_TSS |
Object evaluates to a table of support throttling states. |
8.4.3.2 | ||
_TTP |
Resource data type reserved field name |
17.1.8 | ||
\_TTS |
Control method used to prepare to sleep and run once awakened |
7.3.6 | ||
_TYP |
Resource data type reserved field name |
17.1.8 | ||
_TZ |
ACPI 1.0 thermal zone scope |
5.3.1 | ||
_TZD |
Object evaluates to a package of device names associated with a Thermal Zone. |
11.3.16 | ||
_TZM |
Object indicates the thermal zone of which a device is a member. |
11.3.17 | ||
_TZP |
Thermal zone polling frequency in tenths of seconds. |
11.3.18 | ||
_UID |
Device identification object that specifies a device's unique persistent ID, or a control method that generates it. |
6.1.9 | ||
_UPC |
Object provides USB port capabilities information.. |
9.14 | ||
_UPD |
Object that returns user presence information. |
9.17.1 | ||
_UPP |
Object evaluates to user presence polling interval. |
9.17.2 | ||
_VPO |
Returns 32-bit integer indicating the video post options. |
B.4.6 | ||
\_WAK |
Power management control method run once system is awakened. |
7.3.7 |
Description | |
\_GL |
Global Lock |
\_OS |
Name of the operating system |
\_OSI |
Operating System Interface support |
\_REV |
Revision of the ACPI specification that OSPM implements. |
Operating System Vendor String Prefix |
Description |
"FreeBSD" |
Free BSD |
"HP-UX" |
HP Unix Operating Environment |
"Linux" |
GNU/Linux Operating system |
"OpenVMS" |
HP OpenVMS Operating Environment |
"Windows" |
Microsoft Windows |
Feature Group String |
Description |
"Module Device" |
OSPM supports the declaration of module device (ACPI0004) in the namespace and will enumerate objects under the module device scope. |
"Processor Device" |
OSPM supports the declaration of processors in the namespace using the ACPI0007 processor device HID. |
"3.0 Thermal Model" |
OSPM supports the extensions to the ACPI thermal model in Revision 3.0. |
"Extended Address Space Descriptor" |
OSPM supports the Extended Address Space Descriptor |
"3.0 _SCP Extensions" |
OSPM evaluates _SCP with the additional acoustic limit and power limit arguments defined in ACPI 3.0. |
|
Object |
Description |
_ADR |
Object that evaluates to a device's address on its parent bus. |
_CID |
Object that evaluates to a device's Plug and Play-compatible ID list. |
_DDN |
Object that associates a logical software name (for example, COM1) with a device. |
_HID |
Object that evaluates to a device's Plug and Play hardware ID. |
_MLS |
Object that provides a human readable description of a device in multiple languages. |
_PLD |
Object that provides physical location description information. |
_SUN |
Object that evaluates to the slot-unique ID number for a slot. |
_STR |
Object that contains a Unicode identifier for a device. |
_UID |
Object that specifies a device's unique persistent ID, or a control method that generates it. |
BUS |
Address encoding |
EISA |
EISA slot number 0–F |
Floppy Bus |
Drive select values used for programming the floppy controller to access the specified INT13 unit number. The _ADR Objects should be sorted based on drive select encoding from 0-3. |
IDE Controller |
0–Primary Channel, 1–Secondary Channel |
IDE Channel |
0–Master drive, 1–Slave drive |
Intel® High Definition Audio |
High word – SDI (Serial Data In) ID of the codec that contains the function group. Low word – Node ID of the function group. |
PCI |
High word–Device #, Low word–Function #. (for example, device 3, function 2 is 0x00030002). To refer to all the functions on a device #, use a function number of FFFF). |
PCMCIA |
Socket #; 0–First Socket |
PC CARD |
Socket #; 0–First Socket |
Serial ATA |
SATA Port: High word—Root port #, Low word—port number off of a SATA port multiplier, or 0xFFFF if no port multiplier attached. (For example, root port 2 would be 0x0002FFFF. If instead a port multiplier had been attached to root port 2, the ports connected to the multiplier would be encoded 0x00020000, 0x00020001, etc.) The value 0xFFFFFFFF is reserved. |
SMBus |
Lowest Slave Address |
USB Root HUB |
Only one child of the host controller. It must have an _ADR of 0. No other children or values of _ADR are allowed. |
USB Ports |
Port number (1-n) |
RFC String |
Supported Alias String |
zh-Hans |
zh-chs |
zh-Hant |
zh-cht |
Object |
Description |
_CRS |
Object that specifies a device's current resource settings, or a control method that generates such an object. |
_DIS |
Control method that disables a device. |
_DMA |
Object that specifies a device's current resources for DMA transactions. |
_FIX |
Object used to provide correlation between the fixed-hardware register blocks defined in the FADT and the devices that implement these fixed-hardware registers. |
_GSB |
Object that provides the Global System Interrupt Base for a hot-plugged I/O APIC device. |
_HPP |
Object that specifies the cache-line size, latency timer, SERR enable, and PERR enable values to be used when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot. |
_HPX |
Object that provides device parameters when configuring a PCI device inserted into a hot-plug slot or initial configuration of a PCI device at system boot. Supersedes _HPP. |
_MAT |
Object that evaluates to a buffer of MADT APIC Structure entries. |
_OSC |
An object OSPM evaluates to convey specific software support / capabilities to the platform allowing the platform to configure itself appropriately. |
_PRS |
An object that specifies a device's possible resource settings, or a control method that generates such an object. |
_PRT |
Object that specifies the PCI interrupt routing table. |
_PXM |
Object that specifies a proximity domain for a device. |
_SLI |
Object that provides updated distance information for a system locality. |
_SRS |
Control method that sets a device's settings. |
|
|
|
Field |
Format |
Definition |
Cache-line size |
INTEGER |
Cache-line size reported in number of DWORDs. |
Latency timer |
INTEGER |
Latency timer value reported in number of PCI clock cycles. |
Enable SERR |
INTEGER |
When set to 1, indicates that action must be performed to enable SERR in the command register. |
Enable PERR |
INTEGER |
When set to 1, indicates that action must be performed to enable PERR in the command register. |
|
|
Field |
Format |
Definition |
Header |
|
|
Type |
INTEGER |
0x00: Type 0 (PCI) setting record. |
Revision |
INTEGER |
0x01: Revision 1, defining the set of fields below. |
Cache-line size |
INTEGER |
Cache-line size reported in number of DWORDs. |
Latency timer |
INTEGER |
Latency timer value reported in number of PCI clock cycles. |
Enable SERR |
INTEGER |
When set to 1, indicates that action must be performed to enable SERR in the command register. |
Enable PERR |
INTEGER |
When set to 1, indicates that action must be performed to enable PERR in the command register. |
|
Field |
Format |
Definition |
Header |
|
|
Type |
INTEGER |
0x01: Type 1 (PCI-X) setting record. |
Revision |
INTEGER |
0x01: Revision 1, defining the set of fields below. |
Maximum memory read byte count |
INTEGER |
maximum memory read byte count reported: Value 0: Maximum byte count 512, Value 1: Maximum byte count 1024, Value 2: Maximum byte count 2048, Value 3: Maximum byte count 4096 |
Average maximum outstanding split transactions |
INTEGER |
The following values are defined, Value 0: Maximum outstanding split transaction 1, Value 1: Maximum outstanding split transaction 2, Value 2: Maximum outstanding split transaction 3, Value 3: Maximum outstanding split transaction 4, Value 4: Maximum outstanding split transaction 8, Value 5: Maximum outstanding split transaction 12, Value 6: Maximum outstanding split transaction 16, Value 7: Maximum outstanding split transaction 32, |
Total maximum outstanding split transactions |
INTEGER |
See the definition for the average maximum outstanding split transactions. |
Field |
Format |
Definition |
Header |
|
|
Type |
INTEGER |
0x02: Type 2 (PCI Express) setting record. |
Revision |
INTEGER |
0x01: Revision 1, defining the set of fields below. |
Uncorrectable Error Mask Register AND Mask |
INTEGER |
Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above. |
Uncorrectable Error Mask Register OR Mask |
INTEGER |
Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above. |
Uncorrectable Error Severity Register AND Mask |
INTEGER |
Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above. |
Uncorrectable Error Severity Register OR Mask |
INTEGER |
Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above. |
Correctable Error Mask Register AND Mask |
INTEGER |
Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above. |
Correctable Error Mask Register OR Mask |
INTEGER |
Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above. |
Advanced Error Capabilities and Control Register AND Mask |
INTEGER |
Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above. |
Advanced Error Capabilities and Control Register OR Mask |
INTEGER |
Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above. |
Device Control Register AND Mask |
INTEGER |
Bits 0 to 15 contain the "AND mask" to be used in the OSPM algorithm described above. |
Device Control Register OR Mask |
INTEGER |
Bits 0 to 15 contain the "OR mask" to be used in the OSPM algorithm described above. |
Link Control Register AND Mask |
INTEGER |
Bits 0 to 15 contain the "AND mask" to be used in the OSPM algorithm described above. |
Link Control Register OR Mask |
INTEGER |
Bits 0 to 15 contain the "OR mask" to be used in the OSPM algorithm described above. |
Secondary Uncorrectable Error Severity Register AND Mask |
INTEGER |
Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above |
Secondary Uncorrectable Error Severity Register OR Mask |
INTEGER |
Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above |
Secondary Uncorrectable Error Mask Register AND Mask |
INTEGER |
Bits 0 to 31 contain the "AND mask" to be used in the OSPM algorithm described above |
Secondary Uncorrectable Error Mask Register OR Mask |
INTEGER |
Bits 0 to 31 contain the "OR mask" to be used in the OSPM algorithm described above |
Support Field bit offset |
Interpretation |
0 |
Extended PCI Config operation regions supported The OS sets this bit to 1 if it supports ASL accesses through PCI Config operation regions to extended configuration space (offsets greater than 0xFF). Otherwise, the OS sets this bit to 0. |
1 |
Active State Power Management supported The OS sets this bit to 1 if it natively supports configuration of Active State Power Management registers in PCI Express devices. Otherwise, the OS sets this bit to 0. |
2 |
Clock Power Management Capability supported The OS sets this bit to 1 if it supports the Clock Power Management Capability, and will enable this feature during a native hot plug insertion event if supported by the newly added device. Otherwise, the OS sets this bit to 0. Note: The Clock Power Management Capability is defined in an errata to the PCI Express Base Specification, 1.0. |
3 |
PCI Segment Groups supported The OS sets this bit to 1 if it supports PCI Segment Groups as defined by the _SEG object, and access to the configuration space of devices in PCI Segment Groups as described by this specification. Otherwise, the OS sets this bit to 0. |
4 |
MSI supported The OS sets this bit to 1 if it supports configuration of devices to generate message-signaled interrupts, either through the MSI Capability or the MSI-X Capability. Otherwise, the OS sets this bit to 0. |
5-31 |
Reserved |
Control Field bit offset |
Interpretation |
0 |
PCI Express Native Hot Plug control The OS sets this bit to 1 to request control over PCI Express native hot plug. If the OS successfully receives control of this feature, it must track and update the status of hot plug slots and handle hot plug events as described in the PCI Express Base Specification. |
1 |
SHPC Native Hot Plug control The OS sets this bit to 1 to request control over PCI/PCI-X Standard Hot-Plug Controller (SHPC) hot plug. If the OS successfully receives control of this feature, it must track and update the status of hot plug slots and handle hot plug events as described in the SHPC Specification. |
2 |
PCI Express Native Power Management Events control The OS sets this bit to 1 to request control over PCI Express native power management event interrupts (PMEs). If the OS successfully receives control of this feature, it must handle power management events as described in the PCI Express Base Specification. |
3 |
PCI Express Advanced Error Reporting control The OS sets this bit to 1 to request control over PCI Express Advanced Error Reporting. If the OS successfully receives control of this feature, it must handle error reporting through the Advanced Error Reporting Capability as described in the PCI Express Base Specification. |
4 |
PCI Express Capability Structure control The OS sets this bit to 1 to request control over the PCI Express Capability Structures (standard and extended) defined in the PCI Express Base Specification version 1.1. These capability structures are the PCI Express Capability, the virtual channel extended capability, the power budgeting extended capability, the advanced error reporting extended capability, and the serial number extended capability. If the OS successfully receives control of this feature, it is responsible for configuring the registers in all PCI Express Capabilities in a manner that complies with the PCI Express Base Specification. Additionally, the OS is responsible for saving and restoring all PCI Express Capability register settings across power transitions when register context may have been lost. |
5-31 |
Reserved |
Control Field bit offset |
Interpretation |
0 |
PCI Express Native Hot Plug control The firmware sets this bit to 1 to grant control over PCI Express native hot plug interrupts. If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that all hot plug events are routed to device interrupts as described in the PCI Express Base Specification. Additionally, after control is transferred to the OS, firmware must not update the state of hot plug slots, including the state of the indicators and power controller. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0. |
1 |
SHPC Native Hot Plug control The firmware sets this bit to 1 to grant control over control over PCI/PCI-X Standard Hot-Plug Controller (SHPC)hot plug. If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that all hot plug events are routed to device interrupts as described in the SHPC Specification. Additionally, after control is transferred to the OS, firmware must not update the state of hot plug slots, including the state of the indicators and power controller. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0. |
2 |
PCI Express Native Power Management Events control The firmware sets this bit to 1 to grant control over control over PCI Express native power management event interrupts (PMEs). If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that all PMEs are routed to root port interrupts as described in the PCI Express Base Specification. Additionally, after control is transferred to the OS, firmware must not update the PME Status field in the Root Status register or the PME Interrupt Enable field in the Root Control register. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0. |
3 |
PCI Express Advanced Error Reporting control The firmware sets this bit to 1 to grant control over PCI Express Advanced Error Reporting. If firmware allows the OS control of this feature, then in the context of the _OSC method it must ensure that error messages are routed to device interrupts as described in the PCI Express Base Specification. Additionally, after control is transferred to the OS, firmware must not modify the Advanced Error Reporting Capability. If control of this feature was requested and denied or was not requested, firmware returns this bit set to 0. |
4 |
PCI Express Capability Structure control The firmware sets this bit to 1 to grant control over the PCI Express Capability the firmware does not grant control of this feature, firmware must handle configuration of the PCI Express Capability Structure. If firmware grants the OS control of this feature, any firmware configuration of the PCI Express Capability may be overwritten by an OS configuration, depending on OS policy. |
5-31 |
Reserved |
|
Field |
Type |
Description |
Address |
DWORD |
The address of the device (uses the same format as _ADR). |
Pin |
BYTE |
The PCI pin number of the device (0–INTA, 1–INTB, 2–INTC, 3–INTD). |
Source |
NamePath Or BYTE |
Name of the device that allocates the interrupt to which the above pin is connected. The name can be a fully qualified path, a relative path, or a simple name segment that utilizes the namespace search rules. Note: This field is a NamePath and not a String literal, meaning that it should not be surrounded by quotes. If this field is the integer constant Zero (or a BYTE value of 0), then the interrupt is allocated from the global interrupt pool. |
Source Index |
DWORD |
Index that indicates which resource descriptor in the resource template of the device pointed to in the Source field this interrupt is allocated from. If the Source field is the BYTE value zero, then this field is the global system interrupt number to which the pin is connected. |
Proximity Domain |
0 |
1 |
2 |
3 |
0 |
10 |
15 |
20 |
18 |
1 |
15 |
10 |
16 |
24 |
2 |
20 |
16 |
10 |
12 |
3 |
18 |
24 |
12 |
10 |
Field |
Byte Length |
Byte Offset |
Description |
Header |
|
|
|
Signature |
4 |
0 |
'SLIT'. |
Length |
4 |
4 |
60 |
Revision |
1 |
8 |
1 |
Checksum |
1 |
9 |
Entire table must sum to zero. |
OEMID |
6 |
10 |
OEM ID. |
OEM Table ID |
8 |
16 |
For the System Locality Information Table, the table ID is the manufacturer model ID. |
OEM Revision |
4 |
24 |
OEM revision of System Locality Information Table for supplied OEM Table ID. |
Creator ID |
4 |
28 |
Vendor ID of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the ID for the ASL Compiler. |
Creator Revision |
4 |
32 |
Revision of utility that created the table. For the DSDT, RSDT, SSDT, and PSDT tables, this is the revision for the ASL Compiler. |
Number of System Localities |
8 |
36 |
4 |
Entry[0][0] |
1 |
44 |
10 |
Entry[0][1] |
1 |
45 |
15 |
Entry[0][2] |
1 |
46 |
20 |
Entry[0][3] |
1 |
47 |
18 |
Entry[1][0] |
1 |
48 |
15 |
Entry[1][1] |
1 |
49 |
10 |
Entry[1][2] |
1 |
50 |
16 |
Entry[1][3] |
1 |
51 |
24 |
Entry[2][0] |
1 |
52 |
20 |
Entry[2][1] |
1 |
53 |
16 |
Entry[2][2] |
1 |
54 |
10 |
Entry[2][3] |
1 |
55 |
12 |
Entry[3][0] |
1 |
56 |
18 |
Entry[3][1] |
1 |
57 |
24 |
Entry[3][2] |
1 |
58 |
12 |
Entry[3][3] |
1 |
59 |
10 |
Proximity Domain |
0 |
1 |
2 |
3 |
4 |
0 |
10 |
15 |
20 |
18 |
17 |
1 |
15 |
10 |
16 |
24 |
21 |
2 |
20 |
16 |
10 |
12 |
14 |
3 |
18 |
24 |
12 |
10 |
23 |
4 |
17 |
21 |
14 |
23 |
10 |
|
|
Object |
Description |
_EDL |
Object that evaluates to a package of namespace references of device objects that depend on the device containing _EDL. Whenever the named device is ejected, OSPM ejects all dependent devices. |
_EJD |
Object that evaluates to the name of a device object on which a device depends. Whenever the named device is ejected, the dependent device must receive an ejection notification. |
_EJx |
Control method that ejects a device. |
_LCK |
Control method that locks or unlocks a device. |
_OST |
Control method invoked by OSPM to convey processing status to the platform.. |
_RMV |
Object that indicates that the given device is removable. |
_STA |
Control method that returns a device's status. |
|
|
Source Event Code |
Description |
0-0xFF |
Reserved for Notification Values |
0x100-0x102 |
Reserved |
0x103 |
Ejection Processing |
0x104-0x1FF |
Reserved |
0x200 |
Insertion Processing |
0x201-0xFFFFFFFF |
Reserved |
Status Code |
Description |
0 |
Success |
1 |
Non-specific failure |
2 |
Unrecognized Notify Code |
3-0x7F |
Reserved |
0x80-0xFFFFFFFF |
Notification value specific status codes |
Status Code |
Description |
0x80 |
Device ejection not supported by OSPM |
0x81 |
Device in use by application |
0x82 |
Device Busy |
0x83 |
Ejection dependency is busy or not supported for ejection by OSPM |
0x84 |
Ejection is in progress (pending) |
0x85-0xFFFFFFFF |
Reserved |
Status Code |
Description |
0x80 |
Device insertion in progress (pending) |
0x81 |
Device driver load failure |
0x82-0x8F |
Reserved |
0x90-0x9F |
Insertion failure – Resources Unavailable as described by the following bit encodings: Bit[3] Bus Numbers Bit[2] Interrupts Bit[1] I/O Bit[0] Memory |
0xA0-0xFFFFFFFF |
Reserved |
|
Offset |
Field | ||
Byte 0 |
Tag Bit[7] |
Tag Bits[6:3] |
Tag Bits [2:0] |
|
Type–0 (Small item) |
Small item name |
Length–n bytes |
Bytes 1 to n |
Data bytes (Length 0 – 7) |
Small Item Name |
Value |
Reserved |
0x00-0x03 |
IRQ Format Descriptor |
0x04 |
DMA Format Descriptor |
0x05 |
Start Dependent Functions Descriptor |
0x06 |
End Dependent Functions Descriptor |
0x07 |
I/O Port Descriptor |
0x08 |
Fixed Location I/O Port Descriptor |
0x09 |
Reserved |
0x0A–0x0D |
Vendor Defined Descriptor |
0x0E |
End Tag Descriptor |
0x0F |
Offset |
Field Name |
Byte 0 |
Value = 0x22 or 0x23 (0010001nB) – Type = 0, Small item name = 0x4, Length = 2 or 3 |
Byte 1 |
IRQ mask bits[7:0], _INT Bit[0] represents IRQ0, bit[1] is IRQ1, and so on. |
Byte 2 |
IRQ mask bits[15:8], _INT Bit[0] represents IRQ8, bit[1] is IRQ9, and so on. |
Byte 3 |
IRQ Information. Each bit, when set, indicates this device is capable of driving a certain type of interrupt. (Optional—if not included then assume edge sensitive, high true interrupts.) These bits can be used both for reporting and setting IRQ resources. Note: This descriptor is meant for describing interrupts that are connected to PIC-compatible interrupt controllers, which can only be programmed for Active-High-Edge-Triggered or Active-Low-Level-Triggered interrupts other combination is illegal. The Extended Interrupt Descriptor can be used to describe other combinations. Bit[7:5] Reserved (must be 0) Bit[4] Interrupt is sharable, _SHR Bit[3] Interrupt Polarity, _LL 0 Active-High – This interrupt is sampled when the signal is high, or true 1 Active-Low – This interrupt is sampled when the signal is low, or false. Bit[2:1] Ignored Bit[0] Interrupt Mode, _HE 0 Level-Triggered – Interrupt is triggered in response to signal in a low state. 1 Edge-Triggered – Interrupt is triggered in response to a change in signal state from low to high. |
Offset |
Field Name |
Byte 0 |
Value = 0x2A (00101010B) – Type = 0, Small item name = 0x5, Length = 2 |
Byte 1 |
DMA channel mask bits[7:0] (channels 0 – 7), _DMA Bit[0] is channel 0, etc. |
Byte 2 |
Bit[7] Reserved (must be 0) Bits[6:5] DMA
channel speed supported, _TYP Bits[4:3] Ignored Bit[2] Logical
device bus master status, _BM Bits[1:0] DMA
transfer type preference, _SIZ |
Offset |
Field Name |
Byte 0 |
Value = 0x30 or 0x31 (0011000nB) – Type = 0, small item name = 0x6, Length = 0 or 1 |
Bits |
Definition |
1:0 |
Compatibility priority. Acceptable values are: 0 Good configuration: Highest Priority and preferred configuration 1 Acceptable configuration: Lower Priority but acceptable configuration 2 Sub-optimal configuration: Functional configuration but not optimal 3 Reserved |
3:2 |
Performance/robustness. Acceptable values are: 0 Good configuration: Highest Priority and preferred configuration 1 Acceptable configuration: Lower Priority but acceptable configuration 2 Sub-optimal configuration: Functional configuration but not optimal 3 Reserved |
7:4 |
Reserved (must be 0) |
Offset |
Field Name |
Byte 0 |
Value = 0x38 (00111000B) – Type = 0, Small item name = 0x7, Length =0 |
Offset |
Field Name |
Definition |
Byte 0 |
I/O Port Descriptor |
Value = 0x47 (01000111B) – |
Byte 1 |
Information |
Bits[7:1] Reserved and must be 0 Bit[0] (_DEC) |