GNU make

The GNU make utility determines which pieces of a large program need to be recompiled and issues the commands to recompile them.

This edition of the GNU Make Manual, last updated 08 July 2002, documents GNU make Version 8

i.e. over twenty years ago!
The current version (as of 21 Nov '21 ) is

See this for information about the version of the document.

In fact the GNU documentation is pretty nice so just use it

Edition 75, last updated 17 January 2020, of The GNU Make Manual, for GNU make version
Tersified by DGG.

DGG notes:
*** missing separator. Stop. is the first character a [TAB] !

variable assignments CANNOT have training comment i.e. #

interrupt make usually ^c, do NOT quit ^\

Overview
Introduction
Writing Makefiles
Writing RulesRules describe when a file must be remade.
Writing the Commands in RulesCommands define how to remake a file.
Variables
Conditionals Use or ignore parts of the makefile based on the values of variables.
Functions for Transforming Text
Invoking
Implicit Rules to treat many files alike, based on their file names.
Update Archive Files
GNU make vs other makes
Incompatibilities and Missing Features
Conventions
Quick Reference
Errors Generated by Make
Complex Makefile Example
GNU Free Documentation License  License for copying this manual
Index of Concepts  
Index of Functions, Variables, & Directives  


Overview

Preparing and Running Make  
How to Read This Manual  On Reading this Text
Problems and Bugs  

Introduction

What a Rule Looks Like
A Simple Makefile
How make Processes a Makefile  How make Processes This Makefile
Variables Make Makefiles Simpler
Letting make Deduce the Commands
Another Style of Makefile
Rules for Cleaning the Directory

Writing Makefiles

What Makefiles Contain  What makefiles contain.
What Name to Give Your Makefile  name your makefile.
Including Other Makefiles  How one makefile can use another makefile.
The Variable MAKEFILES  The environment can specify extra makefiles.
The Variable MAKEFILE_LIST  Discover which makefiles have been read.
Other Special Variables  Other special variables.
How Makefiles Are Remade  How makefiles get remade.
Overriding Part of Another Makefile  override part of one makefile with another makefile.
How make Reads a Makefile  How makefiles are parsed.

Writing Rules

Rule Example  An example explained.
Rule Syntax  General syntax explained.
Types of Prerequisites  There are two types of prerequisites.
Using Wildcard Characters in File Names  Using wildcard characters such as `*'.
Searching Directories for Prerequisites  Searching other directories for source files.
Phony Targets  Using a target that is not a real file's name.
Rules without Commands or Prerequisites   use a target without commands or prerequisites to mark other targets as phony.
Empty Target Files to Record Events  When only the date matters and the files are empty.
Special Built-in Target Names  Targets with special built-in meanings.
Multiple Targets in a Rule  When to make use of several targets in a rule.
Multiple Rules for One Target  use several rules with the same target.
Static Pattern Rules  Static pattern rules apply to multiple targets and can vary the prerequisites according to the target name.
Double-Colon Rules  use a special kind of rule to allow several independent rules for one target.
Generating Prerequisites Automatically  automatically generate rules giving prerequisites from source files themselves.

Using Wildcard Characters in File Names

Wildcard Examples  Several examples
Pitfalls of Using Wildcards  Problems to avoid.
The Function wildcard  cause wildcard expansion where it does not normally take place.

Searching Directories for Prerequisites

VPATH: Search Path for All Prerequisites  Specifying a search path that applies to every prerequisite.
The vpath Directive  Specifying a search path for a specified class of names.
How Directory Searches are Performed  When and how search paths are applied.
Writing Shell Commands with Directory Search  write shell commands that work together with search paths.
Directory Search and Implicit Rules  How search paths affect implicit rules.
Directory Search for Link Libraries  Directory search for link libraries.

Static Pattern Rules

Syntax of Static Pattern Rules  The syntax of static pattern rules.
Static Pattern Rules versus Implicit Rules  When are they better than implicit rules?

Writing the Commands in Rules

Command Echoing  control when commands are echoed.
Command Execution  How commands are executed.
Parallel Execution  How commands can be executed in parallel.
Errors in Commands  What happens after a command execution error.
Interrupting or Killing make  What happens when a command is interrupted.
Recursive Use of make  Invoking make from makefiles.
Defining Canned Command Sequences  Defining canned sequences of commands.
Using Empty Commands  Defining useful, do-nothing commands.

Recursive Use of make

How the MAKE Variable Works  The special effects of using $(MAKE).
Communicating Variables to a Sub-make  communicate variables to a sub-make.
Communicating Options to a Sub-make  communicate options to a sub-make.
The --print-directory Option  How the -w or --print-directory option helps debug use of recursive make commands.

How to Use Variables

Basics of Variable References  use the value of a variable.
The Two Flavors of Variables  Variables come in two flavors.
Advanced Features for Reference to Variables  Advanced features for referencing a variable.
How Variables Get Their Values  All the ways variables get their values.
Setting Variables  set a variable in the makefile.
Appending More Text to Variables  append more text to the old value of a variable.
The override Directive  set a variable in the makefile even if the user has set it with a command argument.
Defining Variables Verbatim  An alternate way to set a variable to a verbatim string.
Variables from the Environment  Variable values can come from the environment.
Target-specific Variable Values  Variable values can be defined on a per-target basis.
Pattern-specific Variable Values  Target-specific variable values can be applied to a group of targets that match a pattern.

Advanced Features for Reference to Variables

Substitution References  Referencing a variable with substitutions on the value.
Computed Variable Names  Computing the name of the variable to refer to.

Conditional Parts of Makefiles

Example of a Conditional  Example of a conditional
Syntax of Conditionals  The syntax of conditionals.
Conditionals that Test Flags  Conditionals that test flags.

Functions for Transforming Text

Function Call Syntax  write a function call.
Functions for String Substitution and Analysis  General-purpose text manipulation functions.
Functions for File Names  Functions for manipulating file names.
The foreach Function  Repeat some text with controlled variation.
The if Function  Conditionally expand a value.
The call Function  Expand a user-defined function.
The value Function  Return the un-expanded value of a variable.
The eval Function  Evaluate the arguments as makefile syntax.
The origin Function  Find where a variable got its value.
The shell Function  Substitute the output of a shell command.
Functions That Control Make  Functions that control how make runs.

How to Run make

Arguments to Specify the Makefile  specify which makefile to use.
Arguments to Specify the Goals  use goal arguments to specify which parts of the makefile to use.
Instead of Executing the Commands  use mode flags to specify what kind of thing to do with the commands in the makefile other than simply execute them.
Avoiding Recompilation of Some Files  avoid recompiling certain files.
Overriding Variables  override a variable to specify an alternate compiler and other things.
Testing the Compilation of a Program  proceed past some errors, to test compilation.
Summary of Options  

Using Implicit Rules

Using Implicit Rules  use an existing implicit rule to get the commands for updating a file.
Catalogue of Implicit Rules  A list of built-in implicit rules.
Variables Used by Implicit Rules  change what predefined rules do.
Chains of Implicit Rules  use a chain of implicit rules.
Defining and Redefining Pattern Rules  define new implicit rules.
Defining Last-Resort Default Rules  defining commands for rules which cannot find any.
Old-Fashioned Suffix Rules  The old-fashioned style of implicit rule.
Implicit Rule Search Algorithm  The precise algorithm for applying implicit rules.

Defining and Redefining Pattern Rules

Introduction to Pattern Rules  An introduction to pattern rules.
Pattern Rule Examples  Examples of pattern rules.
Automatic Variables  use automatic variables in the commands of implicit rules.
How Patterns Match  How patterns match.
Match-Anything Pattern Rules  Precautions you should take prior to defining rules that can match any target file whatever.
Canceling Implicit Rules  override or cancel built-in rules.

Using make to Update Archive Files

Archive Members as Targets  Archive members as targets.
Implicit Rule for Archive Member Targets  The implicit rule for archive member targets.
Dangers When Using Archives  Dangers to watch out for when using archives.
Suffix Rules for Archive Files   write a special kind of suffix rule for updating archives.

Implicit Rule for Archive Member Targets

Updating Archive Symbol Directories  update archive symbol directories.

Makefile Conventions

General Conventions for Makefiles  
Utilities in Makefiles  
Variables for Specifying Commands  
Variables for Installation Directories  
Standard Targets for Users  
Install Command Categories  Three categories of commands in the `install'

Copying This Manual


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Overview of make

The make utility automatically determines which pieces of a large program need to be recompiled, and issues commands to recompile them. This manual describes GNU make, which was implemented by Richard Stallman and Roland McGrath. Development since Version 76 has been handled by Paul Smith.

GNU make conforms to section 2 of IEEE Standard 1002-1992 (POSIX.2).

Our examples show C programs, since they are most common, but use make with any programming language whose compiler can be run with a shell command. Indeed, make is not limited to programs. use it to describe any task where some files must be updated automatically from others whenever the others change.

Preparing and Running Make  
How to Read This Manual  On Reading this Text
Problems and Bugs  

Preparing and Running Make

To prepare to use make, you must write a file called the makefile that describes the relationships among files in your program and provides commands for updating each file. In a program, typically, the executable file is updated from object files, which are in turn made by compiling source files.

Once a suitable makefile exists, each time you change some source files, this simple shell command:

 
make

suffices to perform all necessary recompilations. The make program uses the makefile data base and the last-modification times of the files to decide which of the files need to be updated. For each of those files, it issues the commands recorded in the data base.

provide command line arguments to make to control which files should be recompiled, or how. See section Run make.


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How to Read This Manual

If you are new to make, or are looking for a general introduction, read the first few sections of each chapter, skipping the later sections. In each chapter, the first few sections contain introductory or general information and the later sections contain specialized or technical information. The exception is the second chapter, An Introduction to Makefiles, all of which is introductory.

If you are familiar with other make programs, see Features of GNU make, which lists the enhancements GNU make has, and Incompatibilities and Missing Features, which explains the few things GNU make lacks that others have.

For a quick summary, see Summary of Options, A. Quick Reference, and Special Built-in Target Names.


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Problems and Bugs

If you have problems with GNU make or think you've found a bug, please report it to the developers; we cannot promise to do anything but we might well want to fix it.

Before reporting a bug, make sure you've actually found a real bug. Carefully reread the documentation and see if it really says do what you're trying to do. If it's not clear whether you should be able to do something or not, report that too; it's a bug in the documentation!

Before reporting a bug or trying to fix it yourself, try to isolate it to the smallest possible makefile that reproduces the problem. Then send us the makefile and the exact results make gave you, including any error or warning messages. Please don't paraphrase these messages: it's best to cut and paste them into your report. When generating this small makefile, be sure to not use any non-free or unusual tools in your commands: almost always emulate what such a tool would do with simple shell commands. Finally, be sure to explain what you expected to occur; this will help us decide whether the problem was really in the documentation.

Once you have a precise problem report it in one of two ways. Either send electronic mail to:

 
    bug-make@gnu.org

or use our Web-based project management tool, at:

 
    http://savannah.gnu.org/projects/make/

In addition to the information above, please be careful to include the version number of make you are using. get this information with the command make --version. Be sure also to include the type of machine and operating system you are using. One way to obtain this information is by looking at the final lines of output from the command make --help.


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An Introduction to Makefiles

You need a file called a makefile to tell make what to do. Most often, the makefile tells make how to compile and link a program.

In this chapter, we will discuss a simple makefile that describes how to compile and link a text editor which consists of eight C source files and three header files. The makefile can also tell make how to run miscellaneous commands when explicitly asked (for example, to remove certain files as a clean-up operation). To see a more complex example of a makefile, see C. Complex Makefile Example.

When make recompiles the editor, each changed C source file must be recompiled. If a header file has changed, each C source file that includes the header file must be recompiled to be safe. Each compilation produces an object file corresponding to the source file. Finally, if any source file has been recompiled, all the object files, whether newly made or saved from previous compilations, must be linked together to produce the new executable editor.

What a Rule Looks Like  What a rule looks like.
A Simple Makefile  
How make Processes a Makefile  How make Processes This Makefile
Variables Make Makefiles Simpler  
Letting make Deduce the Commands  
Another Style of Makefile  
Rules for Cleaning the Directory  


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What a Rule Looks Like

A simple makefile consists of "rules" with the following shape:

 
target ... : prerequisites ...
        command
        ...
        ...

A target is usually the name of a file that is generated by a program; examples of targets are executable or object files. A target can also be the name of an action to carry out, such as clean (see section Phony Targets).

A prerequisite is a file that is used as input to create the target. A target often depends on several files.

A command is an action that make carries out. A rule may have more than one command, each on its own line. Please note: you need to put a tab character at the beginning of every command line! This is an obscurity that catches the unwary.

Usually a command is in a rule with prerequisites and serves to create a target file if any of the prerequisites change. However, the rule that specifies commands for the target need not have prerequisites. For example, the rule containing the delete command associated with the target clean does not have prerequisites.

A rule, then, explains how and when to remake certain files which are the targets of the particular rule. make carries out the commands on the prerequisites to create or update the target. A rule can also explain how and when to carry out an action. See section Writing Rules.

A makefile may contain other text besides rules, but a simple makefile need only contain rules. Rules may look somewhat more complicated than shown in this template, but all fit the pattern more or less.


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A Simple Makefile

Here is a straightforward makefile that describes the way an executable file called edit depends on eight object files which, in turn, depend on eight C source and three header files.

In this example, all the C files include defs.h, but only those defining editing commands include command.h, and only low level files that change the editor buffer include buffer.h.

 
edit : main.o kbd.o command.o display.o \
       insert.o search.o files.o utils.o
        cc -o edit main.o kbd.o command.o display.o \
                   insert.o search.o files.o utils.o

main.o : main.c defs.h
        cc -c main.c
kbd.o : kbd.c defs.h command.h
        cc -c kbd.c
command.o : command.c defs.h command.h
        cc -c command.c
display.o : display.c defs.h buffer.h
        cc -c display.c
insert.o : insert.c defs.h buffer.h
        cc -c insert.c
search.o : search.c defs.h buffer.h
        cc -c search.c
files.o : files.c defs.h buffer.h command.h
        cc -c files.c
utils.o : utils.c defs.h
        cc -c utils.c
clean :
        rm edit main.o kbd.o command.o display.o \
           insert.o search.o files.o utils.o

We split each long line into two lines using backslash-newline; this is like using one long line, but is easier to read.

To use this makefile to create the executable file called edit, type:

 
make

To use this makefile to delete the executable file and all the object files from the directory, type:

 
make clean

In the example makefile, the targets include the executable file edit, and the object files main.o and kbd.o. The prerequisites are files such as main.c and defs.h. In fact, each .o file is both a target and a prerequisite. Commands include cc -c main.c and cc -c kbd.c.

When a target is a file, it needs to be recompiled or relinked if any of its prerequisites change. In addition, any prerequisites that are themselves automatically generated should be updated first. In this example, edit depends on each of the eight object files; the object file main.o depends on the source file main.c and on the header file defs.h.

A shell command follows each line that contains a target and prerequisites. These shell commands say how to update the target file. A tab character must come at the beginning of every command line to distinguish commands lines from other lines in the makefile. (Bear in mind that make does not know anything about how the commands work. It is up to you to supply commands that will update the target file properly. All make does is execute the commands in the rule you have specified when the target file needs to be updated.)

The target clean is not a file, but merely the name of an action. Since you normally do not want to carry out the actions in this rule, clean is not a prerequisite of any other rule. Consequently, make never does anything with it unless you tell it specifically. Note that this rule not only is not a prerequisite, it also does not have any prerequisites, so the only purpose of the rule is to run the specified commands. Targets that do not refer to files but are just actions are called phony targets. See section Phony Targets, for information about this kind of target. See section Errors in Commands, to see how to cause make to ignore errors from rm or any other command.


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How make Processes a Makefile

By default, make starts with the first target (not targets whose names start with .). This is called the default goal. (Goals are the targets that make strives ultimately to update. See section Arguments to Specify the Goals.)

In the simple example of the previous section, the default goal is to update the executable program edit; therefore, we put that rule first.

Thus, when you give the command:

 
make

make reads the makefile in the current directory and begins by processing the first rule. In the example, this rule is for relinking edit; but before make can fully process this rule, it must process the rules for the files that edit depends on, which in this case are the object files. Each of these files is processed according to its own rule. These rules say to update each .o file by compiling its source file. The recompilation must be done if the source file, or any of the header files named as prerequisites, is more recent than the object file, or if the object file does not exist.

The other rules are processed because their targets appear as prerequisites of the goal. If some other rule is not depended on by the goal (or anything it depends on, etc.), that rule is not processed, unless you tell make to do so (with a command such as make clean).

Before recompiling an object file, make considers updating its prerequisites, the source file and header files. This makefile does not specify anything to be done for them--the .c and .h files are not the targets of any rules--so make does nothing for these files. But make would update automatically generated C programs, such as those made by Bison or Yacc, by their own rules at this time.

After recompiling whichever object files need it, make decides whether to relink edit. This must be done if the file edit does not exist, or if any of the object files are newer than it. If an object file was just recompiled, it is now newer than edit, so edit is relinked.

Thus, if we change the file insert.c and run make, make will compile that file to update insert.o, and then link edit. If we change the file command.h and run make, make will recompile the object files kbd.o, command.o and files.o and then link the file edit.


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Variables Make Makefiles Simpler

In our example, we had to list all the object files twice in the rule for edit (repeated here):

 
edit : main.o kbd.o command.o display.o \
              insert.o search.o files.o utils.o
        cc -o edit main.o kbd.o command.o display.o \
                   insert.o search.o files.o utils.o

Such duplication is error-prone; if a new object file is added to the system, we might add it to one list and forget the other. We can eliminate the risk and simplify the makefile by using a variable. Variables allow a text string to be defined once and substituted in multiple places later (see section Use Variables).

It is standard practice for every makefile to have a variable named objects, OBJECTS, objs, OBJS, obj, or OBJ which is a list of all object file names. We would define such a variable objects with a line like this in the makefile:

 
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

Then, each place we want to put a list of the object file names, we can substitute the variable's value by writing $(objects) (see section Use Variables).

Here is how the complete simple makefile looks when you use a variable for the object files:

 
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)
main.o : main.c defs.h
        cc -c main.c
kbd.o : kbd.c defs.h command.h
        cc -c kbd.c
command.o : command.c defs.h command.h
        cc -c command.c
display.o : display.c defs.h buffer.h
        cc -c display.c
insert.o : insert.c defs.h buffer.h
        cc -c insert.c
search.o : search.c defs.h buffer.h
        cc -c search.c
files.o : files.c defs.h buffer.h command.h
        cc -c files.c
utils.o : utils.c defs.h
        cc -c utils.c
clean :
        rm edit $(objects)


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Letting make Deduce the Commands

It is not necessary to spell out the commands for compiling the individual C source files, because make can figure them out: it has an implicit rule for updating a .o file from a correspondingly named .c file using a cc -c command. For example, it will use the command cc -c main.c -o main.o to compile main.c into main.o. We can therefore omit the commands from the rules for the object files. See section Using Implicit Rules.

When a .c file is used automatically in this way, it is also automatically added to the list of prerequisites. We can therefore omit the .c files from the prerequisites, provided we omit the commands.

Here is the entire example, with both of these changes, and a variable objects as suggested above:

 
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)

main.o : defs.h
kbd.o : defs.h command.h
command.o : defs.h command.h
display.o : defs.h buffer.h
insert.o : defs.h buffer.h
search.o : defs.h buffer.h
files.o : defs.h buffer.h command.h
utils.o : defs.h

.PHONY : clean
clean :
        rm edit $(objects)

This is how we would write the makefile in actual practice. (The complications associated with clean are described elsewhere. See Phony Targets, and Errors in Commands.)

Because implicit rules are so convenient, they are important. You will see them used frequently.


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Another Style of Makefile

When the objects of a makefile are created only by implicit rules, an alternative style of makefile is possible. In this style of makefile, you group entries by their prerequisites instead of by their targets. Here is what one looks like:

 
objects = main.o kbd.o command.o display.o \
          insert.o search.o files.o utils.o

edit : $(objects)
        cc -o edit $(objects)

$(objects) : defs.h
kbd.o command.o files.o : command.h
display.o insert.o search.o files.o : buffer.h

Here defs.h is given as a prerequisite of all the object files; command.h and buffer.h are prerequisites of the specific object files listed for them.

Whether this is better is a matter of taste: it is more compact, but some people dislike it because they find it clearer to put all the information about each target in one place.


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Rules for Cleaning the Directory

Compiling a program is not the only thing you might want to write rules for. Makefiles commonly tell how to do a few other things besides compiling a program: for example, how to delete all the object files and executables so that the directory is clean.

Here is how we could write a make rule for cleaning our example editor:

 
clean:
        rm edit $(objects)

In practice, we might want to write the rule in a somewhat more complicated manner to handle unanticipated situations. We would do this:

 
.PHONY : clean
clean :
        -rm edit $(objects)

This prevents make from getting confused by an actual file called clean and causes it to continue in spite of errors from rm. (See Phony Targets, and Errors in Commands.)

A rule such as this should not be placed at the beginning of the makefile, because we do not want it to run by default! Thus, in the example makefile, we want the rule for edit, which recompiles the editor, to remain the default goal.

Since clean is not a prerequisite of edit, this rule will not run at all if we give the command make with no arguments. In order to make the rule run, we have to type make clean. See section Run make.


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Writing Makefiles

The information that tells make how to recompile a system comes from reading a data base called the makefile.

What Makefiles Contain  What makefiles contain.
What Name to Give Your Makefile  name your makefile.
Including Other Makefiles  How one makefile can use another makefile.
The Variable MAKEFILES  The environment can specify extra makefiles.
The Variable MAKEFILE_LIST  Discover which makefiles have been read.
Other Special Variables  Other special variables.
How Makefiles Are Remade  How makefiles get remade.
Overriding Part of Another Makefile  override part of one makefile with another makefile.
How make Reads a Makefile  How makefiles are parsed.


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What Makefiles Contain

Makefiles contain five kinds of things: explicit rules, implicit rules, variable definitions, directives, and comments. Rules, variables, and directives are described at length in later chapters.